iew.hh revision 2292 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __CPU_O3_IEW_HH__
30#define __CPU_O3_IEW_HH__
31
32#include <queue>
33
34#include "base/statistics.hh"
35#include "base/timebuf.hh"
36#include "config/full_system.hh"
37#include "cpu/o3/comm.hh"
38#include "cpu/o3/scoreboard.hh"
39#include "cpu/o3/lsq.hh"
40
41class FUPool;
42
43/**
44 * DefaultIEW handles both single threaded and SMT IEW(issue/execute/writeback).
45 * It handles the dispatching of instructions to the LSQ/IQ as part of the issue
46 * stage, and has the IQ try to issue instructions each cycle. The execute
47 * latency is actually tied into the issue latency to allow the IQ to be able to
48 * do back-to-back scheduling without having to speculatively schedule
49 * instructions. This happens by having the IQ have access to the functional
50 * units, and the IQ gets the execution latencies from the FUs when it issues
51 * instructions. Instructions reach the execute stage on the last cycle of
52 * their execution, which is when the IQ knows to wake up any dependent
53 * instructions, allowing back to back scheduling. The execute portion of IEW
54 * separates memory instructions from non-memory instructions, either telling
55 * the LSQ to execute the instruction, or executing the instruction directly.
56 * The writeback portion of IEW completes the instructions by waking up any
57 * dependents, and marking the register ready on the scoreboard.
58 */
59template<class Impl>
60class DefaultIEW
61{
62  private:
63    //Typedefs from Impl
64    typedef typename Impl::CPUPol CPUPol;
65    typedef typename Impl::DynInstPtr DynInstPtr;
66    typedef typename Impl::FullCPU FullCPU;
67    typedef typename Impl::Params Params;
68
69    typedef typename CPUPol::IQ IQ;
70    typedef typename CPUPol::RenameMap RenameMap;
71    typedef typename CPUPol::LSQ LSQ;
72
73    typedef typename CPUPol::TimeStruct TimeStruct;
74    typedef typename CPUPol::IEWStruct IEWStruct;
75    typedef typename CPUPol::RenameStruct RenameStruct;
76    typedef typename CPUPol::IssueStruct IssueStruct;
77
78    friend class Impl::FullCPU;
79    friend class CPUPol::IQ;
80
81  public:
82    /** Overall IEW stage status. Used to determine if the CPU can
83     * deschedule itself due to a lack of activity.
84     */
85    enum Status {
86        Active,
87        Inactive
88    };
89
90    /** Status for Issue, Execute, and Writeback stages. */
91    enum StageStatus {
92        Running,
93        Blocked,
94        Idle,
95        StartSquash,
96        Squashing,
97        Unblocking
98    };
99
100  private:
101    /** Overall stage status. */
102    Status _status;
103    /** Dispatch status. */
104    StageStatus dispatchStatus[Impl::MaxThreads];
105    /** Execute status. */
106    StageStatus exeStatus;
107    /** Writeback status. */
108    StageStatus wbStatus;
109
110  public:
111    /** LdWriteback event for a load completion. */
112    class LdWritebackEvent : public Event {
113      private:
114        /** Instruction that is writing back data to the register file. */
115        DynInstPtr inst;
116        /** Pointer to IEW stage. */
117        DefaultIEW<Impl> *iewStage;
118
119      public:
120        /** Constructs a load writeback event. */
121        LdWritebackEvent(DynInstPtr &_inst, DefaultIEW<Impl> *_iew);
122
123        /** Processes writeback event. */
124        virtual void process();
125        /** Returns the description of the writeback event. */
126        virtual const char *description();
127    };
128
129  public:
130    /** Constructs a DefaultIEW with the given parameters. */
131    DefaultIEW(Params *params);
132
133    /** Returns the name of the DefaultIEW stage. */
134    std::string name() const;
135
136    /** Registers statistics. */
137    void regStats();
138
139    /** Initializes stage; sends back the number of free IQ and LSQ entries. */
140    void initStage();
141
142    /** Sets CPU pointer for IEW, IQ, and LSQ. */
143    void setCPU(FullCPU *cpu_ptr);
144
145    /** Sets main time buffer used for backwards communication. */
146    void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
147
148    /** Sets time buffer for getting instructions coming from rename. */
149    void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
150
151    /** Sets time buffer to pass on instructions to commit. */
152    void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
153
154    /** Sets pointer to list of active threads. */
155    void setActiveThreads(std::list<unsigned> *at_ptr);
156
157    /** Sets pointer to the scoreboard. */
158    void setScoreboard(Scoreboard *sb_ptr);
159
160    /** Sets page table pointer within LSQ. */
161//    void setPageTable(PageTable *pt_ptr);
162
163    /** Squashes instructions in IEW for a specific thread. */
164    void squash(unsigned tid);
165
166    /** Wakes all dependents of a completed instruction. */
167    void wakeDependents(DynInstPtr &inst);
168
169    /** Tells memory dependence unit that a memory instruction needs to be
170     * rescheduled. It will re-execute once replayMemInst() is called.
171     */
172    void rescheduleMemInst(DynInstPtr &inst);
173
174    /** Re-executes all rescheduled memory instructions. */
175    void replayMemInst(DynInstPtr &inst);
176
177    /** Sends an instruction to commit through the time buffer. */
178    void instToCommit(DynInstPtr &inst);
179
180    /** Inserts unused instructions of a thread into the skid buffer. */
181    void skidInsert(unsigned tid);
182
183    /** Returns the max of the number of entries in all of the skid buffers. */
184    int skidCount();
185
186    /** Returns if all of the skid buffers are empty. */
187    bool skidsEmpty();
188
189    /** Updates overall IEW status based on all of the stages' statuses. */
190    void updateStatus();
191
192    /** Resets entries of the IQ and the LSQ. */
193    void resetEntries();
194
195    /** Tells the CPU to wakeup if it has descheduled itself due to no
196     * activity. Used mainly by the LdWritebackEvent.
197     */
198    void wakeCPU();
199
200    /** Reports to the CPU that there is activity this cycle. */
201    void activityThisCycle();
202
203    /** Tells CPU that the IEW stage is active and running. */
204    inline void activateStage();
205
206    /** Tells CPU that the IEW stage is inactive and idle. */
207    inline void deactivateStage();
208
209//#if !FULL_SYSTEM
210    /** Returns if the LSQ has any stores to writeback. */
211    bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); }
212//#endif
213
214  private:
215    /** Sends commit proper information for a squash due to a branch
216     * mispredict.
217     */
218    void squashDueToBranch(DynInstPtr &inst, unsigned thread_id);
219
220    /** Sends commit proper information for a squash due to a memory order
221     * violation.
222     */
223    void squashDueToMemOrder(DynInstPtr &inst, unsigned thread_id);
224
225    /** Sends commit proper information for a squash due to memory becoming
226     * blocked (younger issued instructions must be retried).
227     */
228    void squashDueToMemBlocked(DynInstPtr &inst, unsigned thread_id);
229
230    /** Sets Dispatch to blocked, and signals back to other stages to block. */
231    void block(unsigned thread_id);
232
233    /** Unblocks Dispatch if the skid buffer is empty, and signals back to
234     * other stages to unblock.
235     */
236    void unblock(unsigned thread_id);
237
238    /** Determines proper actions to take given Dispatch's status. */
239    void dispatch(unsigned tid);
240
241    /** Dispatches instructions to IQ and LSQ. */
242    void dispatchInsts(unsigned tid);
243
244    /** Executes instructions. In the case of memory operations, it informs the
245     * LSQ to execute the instructions. Also handles any redirects that occur
246     * due to the executed instructions.
247     */
248    void executeInsts();
249
250    /** Writebacks instructions. In our model, the instruction's execute()
251     * function atomically reads registers, executes, and writes registers.
252     * Thus this writeback only wakes up dependent instructions, and informs
253     * the scoreboard of registers becoming ready.
254     */
255    void writebackInsts();
256
257    /** Returns the number of valid, non-squashed instructions coming from
258     * rename to dispatch.
259     */
260    unsigned validInstsFromRename();
261
262    /** Reads the stall signals. */
263    void readStallSignals(unsigned tid);
264
265    /** Checks if any of the stall conditions are currently true. */
266    bool checkStall(unsigned tid);
267
268    /** Processes inputs and changes state accordingly. */
269    void checkSignalsAndUpdate(unsigned tid);
270
271    /** Sorts instructions coming from rename into lists separated by thread. */
272    void sortInsts();
273
274  public:
275    /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and
276     * Writeback to run for one cycle.
277     */
278    void tick();
279
280  private:
281    /** Pointer to main time buffer used for backwards communication. */
282    TimeBuffer<TimeStruct> *timeBuffer;
283
284    /** Wire to write information heading to previous stages. */
285    typename TimeBuffer<TimeStruct>::wire toFetch;
286
287    /** Wire to get commit's output from backwards time buffer. */
288    typename TimeBuffer<TimeStruct>::wire fromCommit;
289
290    /** Wire to write information heading to previous stages. */
291    typename TimeBuffer<TimeStruct>::wire toRename;
292
293    /** Rename instruction queue interface. */
294    TimeBuffer<RenameStruct> *renameQueue;
295
296    /** Wire to get rename's output from rename queue. */
297    typename TimeBuffer<RenameStruct>::wire fromRename;
298
299    /** Issue stage queue. */
300    TimeBuffer<IssueStruct> issueToExecQueue;
301
302    /** Wire to read information from the issue stage time queue. */
303    typename TimeBuffer<IssueStruct>::wire fromIssue;
304
305    /**
306     * IEW stage time buffer.  Holds ROB indices of instructions that
307     * can be marked as completed.
308     */
309    TimeBuffer<IEWStruct> *iewQueue;
310
311    /** Wire to write infromation heading to commit. */
312    typename TimeBuffer<IEWStruct>::wire toCommit;
313
314    /** Queue of all instructions coming from rename this cycle. */
315    std::queue<DynInstPtr> insts[Impl::MaxThreads];
316
317    /** Skid buffer between rename and IEW. */
318    std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
319
320    /** Scoreboard pointer. */
321    Scoreboard* scoreboard;
322
323  public:
324    /** Instruction queue. */
325    IQ instQueue;
326
327    /** Load / store queue. */
328    LSQ ldstQueue;
329
330    /** Pointer to the functional unit pool. */
331    FUPool *fuPool;
332
333  private:
334    /** CPU pointer. */
335    FullCPU *cpu;
336
337    /** Records if IEW has written to the time buffer this cycle, so that the
338     * CPU can deschedule itself if there is no activity.
339     */
340    bool wroteToTimeBuffer;
341
342    /** Source of possible stalls. */
343    struct Stalls {
344        bool commit;
345    };
346
347    /** Stages that are telling IEW to stall. */
348    Stalls stalls[Impl::MaxThreads];
349
350    /** Debug function to print instructions that are issued this cycle. */
351    void printAvailableInsts();
352
353  public:
354    /** Records if the LSQ needs to be updated on the next cycle, so that
355     * IEW knows if there will be activity on the next cycle.
356     */
357    bool updateLSQNextCycle;
358
359  private:
360    /** Records if there is a fetch redirect on this cycle for each thread. */
361    bool fetchRedirect[Impl::MaxThreads];
362
363    /** Used to track if all instructions have been dispatched this cycle.
364     * If they have not, then blocking must have occurred, and the instructions
365     * would already be added to the skid buffer.
366     * @todo: Fix this hack.
367     */
368    bool dispatchedAllInsts;
369
370    /** Records if the queues have been changed (inserted or issued insts),
371     * so that IEW knows to broadcast the updated amount of free entries.
372     */
373    bool updatedQueues;
374
375    /** Commit to IEW delay, in ticks. */
376    unsigned commitToIEWDelay;
377
378    /** Rename to IEW delay, in ticks. */
379    unsigned renameToIEWDelay;
380
381    /**
382     * Issue to execute delay, in ticks.  What this actually represents is
383     * the amount of time it takes for an instruction to wake up, be
384     * scheduled, and sent to a FU for execution.
385     */
386    unsigned issueToExecuteDelay;
387
388    /** Width of issue's read path, in instructions.  The read path is both
389     *  the skid buffer and the rename instruction queue.
390     *  Note to self: is this really different than issueWidth?
391     */
392    unsigned issueReadWidth;
393
394    /** Width of issue, in instructions. */
395    unsigned issueWidth;
396
397    /** Width of execute, in instructions.  Might make more sense to break
398     *  down into FP vs int.
399     */
400    unsigned executeWidth;
401
402    /** Index into queue of instructions being written back. */
403    unsigned wbNumInst;
404
405    /** Cycle number within the queue of instructions being written back.
406     * Used in case there are too many instructions writing back at the current
407     * cycle and writesbacks need to be scheduled for the future. See comments
408     * in instToCommit().
409     */
410    unsigned wbCycle;
411
412    /** Number of active threads. */
413    unsigned numThreads;
414
415    /** Pointer to list of active threads. */
416    std::list<unsigned> *activeThreads;
417
418    /** Maximum size of the skid buffer. */
419    unsigned skidBufferMax;
420
421    /** Stat for total number of idle cycles. */
422    Stats::Scalar<> iewIdleCycles;
423    /** Stat for total number of squashing cycles. */
424    Stats::Scalar<> iewSquashCycles;
425    /** Stat for total number of blocking cycles. */
426    Stats::Scalar<> iewBlockCycles;
427    /** Stat for total number of unblocking cycles. */
428    Stats::Scalar<> iewUnblockCycles;
429    /** Stat for total number of instructions dispatched. */
430    Stats::Scalar<> iewDispatchedInsts;
431    /** Stat for total number of squashed instructions dispatch skips. */
432    Stats::Scalar<> iewDispSquashedInsts;
433    /** Stat for total number of dispatched load instructions. */
434    Stats::Scalar<> iewDispLoadInsts;
435    /** Stat for total number of dispatched store instructions. */
436    Stats::Scalar<> iewDispStoreInsts;
437    /** Stat for total number of dispatched non speculative instructions. */
438    Stats::Scalar<> iewDispNonSpecInsts;
439    /** Stat for number of times the IQ becomes full. */
440    Stats::Scalar<> iewIQFullEvents;
441    /** Stat for number of times the LSQ becomes full. */
442    Stats::Scalar<> iewLSQFullEvents;
443    /** Stat for total number of executed instructions. */
444    Stats::Scalar<> iewExecutedInsts;
445    /** Stat for total number of executed load instructions. */
446    Stats::Scalar<> iewExecLoadInsts;
447    /** Stat for total number of executed store instructions. */
448    Stats::Scalar<> iewExecStoreInsts;
449    /** Stat for total number of squashed instructions skipped at execute. */
450    Stats::Scalar<> iewExecSquashedInsts;
451    /** Stat for total number of memory ordering violation events. */
452    Stats::Scalar<> memOrderViolationEvents;
453    /** Stat for total number of incorrect predicted taken branches. */
454    Stats::Scalar<> predictedTakenIncorrect;
455    /** Stat for total number of incorrect predicted not taken branches. */
456    Stats::Scalar<> predictedNotTakenIncorrect;
457    /** Stat for total number of mispredicted branches detected at execute. */
458    Stats::Formula branchMispredicts;
459};
460
461#endif // __CPU_O3_IEW_HH__
462