iew.hh revision 1858 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29//Todo: Update with statuses.
30//Need to handle delaying writes to the writeback bus if it's full at the
31//given time.
32
33#ifndef __CPU_O3_CPU_SIMPLE_IEW_HH__
34#define __CPU_O3_CPU_SIMPLE_IEW_HH__
35
36#include <queue>
37
38#include "config/full_system.hh"
39#include "base/statistics.hh"
40#include "base/timebuf.hh"
41#include "cpu/o3/comm.hh"
42
43template<class Impl>
44class SimpleIEW
45{
46  private:
47    //Typedefs from Impl
48    typedef typename Impl::ISA ISA;
49    typedef typename Impl::CPUPol CPUPol;
50    typedef typename Impl::DynInstPtr DynInstPtr;
51    typedef typename Impl::FullCPU FullCPU;
52    typedef typename Impl::Params Params;
53
54    typedef typename CPUPol::IQ IQ;
55    typedef typename CPUPol::RenameMap RenameMap;
56    typedef typename CPUPol::LDSTQ LDSTQ;
57
58    typedef typename CPUPol::TimeStruct TimeStruct;
59    typedef typename CPUPol::IEWStruct IEWStruct;
60    typedef typename CPUPol::RenameStruct RenameStruct;
61    typedef typename CPUPol::IssueStruct IssueStruct;
62
63    friend class Impl::FullCPU;
64  public:
65    enum Status {
66        Running,
67        Blocked,
68        Idle,
69        Squashing,
70        Unblocking
71    };
72
73  private:
74    Status _status;
75    Status _issueStatus;
76    Status _exeStatus;
77    Status _wbStatus;
78
79  public:
80    class WritebackEvent : public Event {
81      private:
82        DynInstPtr inst;
83        SimpleIEW<Impl> *iewStage;
84
85      public:
86        WritebackEvent(DynInstPtr &_inst, SimpleIEW<Impl> *_iew);
87
88        virtual void process();
89        virtual const char *description();
90    };
91
92  public:
93    SimpleIEW(Params &params);
94
95    void regStats();
96
97    void setCPU(FullCPU *cpu_ptr);
98
99    void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
100
101    void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
102
103    void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
104
105    void setRenameMap(RenameMap *rm_ptr);
106
107    void squash();
108
109    void squashDueToBranch(DynInstPtr &inst);
110
111    void squashDueToMem(DynInstPtr &inst);
112
113    void block();
114
115    inline void unblock();
116
117    void wakeDependents(DynInstPtr &inst);
118
119    void instToCommit(DynInstPtr &inst);
120
121  private:
122    void dispatchInsts();
123
124    void executeInsts();
125
126  public:
127    void tick();
128
129    void iew();
130
131    //Interfaces to objects inside and outside of IEW.
132    /** Time buffer interface. */
133    TimeBuffer<TimeStruct> *timeBuffer;
134
135    /** Wire to get commit's output from backwards time buffer. */
136    typename TimeBuffer<TimeStruct>::wire fromCommit;
137
138    /** Wire to write information heading to previous stages. */
139    typename TimeBuffer<TimeStruct>::wire toRename;
140
141    /** Rename instruction queue interface. */
142    TimeBuffer<RenameStruct> *renameQueue;
143
144    /** Wire to get rename's output from rename queue. */
145    typename TimeBuffer<RenameStruct>::wire fromRename;
146
147    /** Issue stage queue. */
148    TimeBuffer<IssueStruct> issueToExecQueue;
149
150    /** Wire to read information from the issue stage time queue. */
151    typename TimeBuffer<IssueStruct>::wire fromIssue;
152
153    /**
154     * IEW stage time buffer.  Holds ROB indices of instructions that
155     * can be marked as completed.
156     */
157    TimeBuffer<IEWStruct> *iewQueue;
158
159    /** Wire to write infromation heading to commit. */
160    typename TimeBuffer<IEWStruct>::wire toCommit;
161
162    //Will need internal queue to hold onto instructions coming from
163    //the rename stage in case of a stall.
164    /** Skid buffer between rename and IEW. */
165    std::queue<RenameStruct> skidBuffer;
166
167  protected:
168    /** Instruction queue. */
169    IQ instQueue;
170
171    LDSTQ ldstQueue;
172
173#if !FULL_SYSTEM
174  public:
175    void lsqWriteback();
176#endif
177
178  private:
179    /** Pointer to rename map.  Might not want this stage to directly
180     *  access this though...
181     */
182    RenameMap *renameMap;
183
184    /** CPU interface. */
185    FullCPU *cpu;
186
187  private:
188    /** Commit to IEW delay, in ticks. */
189    unsigned commitToIEWDelay;
190
191    /** Rename to IEW delay, in ticks. */
192    unsigned renameToIEWDelay;
193
194    /**
195     * Issue to execute delay, in ticks.  What this actually represents is
196     * the amount of time it takes for an instruction to wake up, be
197     * scheduled, and sent to a FU for execution.
198     */
199    unsigned issueToExecuteDelay;
200
201    /** Width of issue's read path, in instructions.  The read path is both
202     *  the skid buffer and the rename instruction queue.
203     *  Note to self: is this really different than issueWidth?
204     */
205    unsigned issueReadWidth;
206
207    /** Width of issue, in instructions. */
208    unsigned issueWidth;
209
210    /** Width of execute, in instructions.  Might make more sense to break
211     *  down into FP vs int.
212     */
213    unsigned executeWidth;
214
215    /** Number of cycles stage has been squashing.  Used so that the stage
216     *  knows when it can start unblocking, which is when the previous stage
217     *  has received the stall signal and clears up its outputs.
218     */
219    unsigned cyclesSquashing;
220
221    Stats::Scalar<> iewIdleCycles;
222    Stats::Scalar<> iewSquashCycles;
223    Stats::Scalar<> iewBlockCycles;
224    Stats::Scalar<> iewUnblockCycles;
225//    Stats::Scalar<> iewWBInsts;
226    Stats::Scalar<> iewDispatchedInsts;
227    Stats::Scalar<> iewDispSquashedInsts;
228    Stats::Scalar<> iewDispLoadInsts;
229    Stats::Scalar<> iewDispStoreInsts;
230    Stats::Scalar<> iewDispNonSpecInsts;
231    Stats::Scalar<> iewIQFullEvents;
232    Stats::Scalar<> iewExecutedInsts;
233    Stats::Scalar<> iewExecLoadInsts;
234    Stats::Scalar<> iewExecStoreInsts;
235    Stats::Scalar<> iewExecSquashedInsts;
236    Stats::Scalar<> memOrderViolationEvents;
237    Stats::Scalar<> predictedTakenIncorrect;
238};
239
240#endif // __CPU_O3_CPU_IEW_HH__
241