iew.hh revision 1461 
1//Todo: Update with statuses.
2//Need to handle delaying writes to the writeback bus if it's full at the
3//given time.  Load store queue.
4
5#ifndef __CPU_BETA_CPU_SIMPLE_IEW_HH__
6#define __CPU_BETA_CPU_SIMPLE_IEW_HH__
7
8#include <queue>
9
10#include "base/statistics.hh"
11#include "base/timebuf.hh"
12#include "cpu/beta_cpu/comm.hh"
13
14//Can IEW even stall?  Space should be available/allocated already...maybe
15//if there's not enough write ports on the ROB or waiting for CDB
16//arbitration.
17template<class Impl, class IQ>
18class SimpleIEW
19{
20  private:
21    //Typedefs from Impl
22    typedef typename Impl::ISA ISA;
23    typedef typename Impl::CPUPol CPUPol;
24    typedef typename Impl::DynInstPtr DynInstPtr;
25    typedef typename Impl::FullCPU FullCPU;
26    typedef typename Impl::Params Params;
27
28    typedef typename CPUPol::RenameMap RenameMap;
29    typedef typename CPUPol::LDSTQ LDSTQ;
30
31    typedef typename CPUPol::TimeStruct TimeStruct;
32    typedef typename CPUPol::IEWStruct IEWStruct;
33    typedef typename CPUPol::RenameStruct RenameStruct;
34    typedef typename CPUPol::IssueStruct IssueStruct;
35
36  public:
37    enum Status {
38        Running,
39        Blocked,
40        Idle,
41        Squashing,
42        Unblocking
43    };
44
45  private:
46    Status _status;
47    Status _issueStatus;
48    Status _exeStatus;
49    Status _wbStatus;
50
51  public:
52    void squash();
53
54    void squashDueToBranch(DynInstPtr &inst);
55
56    void squashDueToMem(DynInstPtr &inst);
57
58    void block();
59
60    inline void unblock();
61
62  public:
63    SimpleIEW(Params &params);
64
65    void regStats();
66
67    void setCPU(FullCPU *cpu_ptr);
68
69    void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
70
71    void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
72
73    void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
74
75    void setRenameMap(RenameMap *rm_ptr);
76
77    void wakeDependents(DynInstPtr &inst);
78
79    void tick();
80
81    void iew();
82
83  private:
84    void dispatchInsts();
85
86    void executeInsts();
87
88    //Interfaces to objects inside and outside of IEW.
89    /** Time buffer interface. */
90    TimeBuffer<TimeStruct> *timeBuffer;
91
92    /** Wire to get commit's output from backwards time buffer. */
93    typename TimeBuffer<TimeStruct>::wire fromCommit;
94
95    /** Wire to write information heading to previous stages. */
96    typename TimeBuffer<TimeStruct>::wire toRename;
97
98    /** Rename instruction queue interface. */
99    TimeBuffer<RenameStruct> *renameQueue;
100
101    /** Wire to get rename's output from rename queue. */
102    typename TimeBuffer<RenameStruct>::wire fromRename;
103
104    /** Issue stage queue. */
105    TimeBuffer<IssueStruct> issueToExecQueue;
106
107    /** Wire to read information from the issue stage time queue. */
108    typename TimeBuffer<IssueStruct>::wire fromIssue;
109
110    /**
111     * IEW stage time buffer.  Holds ROB indices of instructions that
112     * can be marked as completed.
113     */
114    TimeBuffer<IEWStruct> *iewQueue;
115
116    /** Wire to write infromation heading to commit. */
117    typename TimeBuffer<IEWStruct>::wire toCommit;
118
119    //Will need internal queue to hold onto instructions coming from
120    //the rename stage in case of a stall.
121    /** Skid buffer between rename and IEW. */
122    std::queue<RenameStruct> skidBuffer;
123
124    /** Instruction queue. */
125    IQ instQueue;
126
127    LDSTQ ldstQueue;
128
129    /** Pointer to rename map.  Might not want this stage to directly
130     *  access this though...
131     */
132    RenameMap *renameMap;
133
134    /** CPU interface. */
135    FullCPU *cpu;
136
137  private:
138    /** Commit to IEW delay, in ticks. */
139    unsigned commitToIEWDelay;
140
141    /** Rename to IEW delay, in ticks. */
142    unsigned renameToIEWDelay;
143
144    /**
145     * Issue to execute delay, in ticks.  What this actually represents is
146     * the amount of time it takes for an instruction to wake up, be
147     * scheduled, and sent to a FU for execution.
148     */
149    unsigned issueToExecuteDelay;
150
151    /** Width of issue's read path, in instructions.  The read path is both
152     *  the skid buffer and the rename instruction queue.
153     *  Note to self: is this really different than issueWidth?
154     */
155    unsigned issueReadWidth;
156
157    /** Width of issue, in instructions. */
158    unsigned issueWidth;
159
160    /** Width of execute, in instructions.  Might make more sense to break
161     *  down into FP vs int.
162     */
163    unsigned executeWidth;
164
165    /** Number of cycles stage has been squashing.  Used so that the stage
166     *  knows when it can start unblocking, which is when the previous stage
167     *  has received the stall signal and clears up its outputs.
168     */
169    unsigned cyclesSquashing;
170
171    Stats::Scalar<> iewIdleCycles;
172    Stats::Scalar<> iewSquashCycles;
173    Stats::Scalar<> iewBlockCycles;
174    Stats::Scalar<> iewUnblockCycles;
175//    Stats::Scalar<> iewWBInsts;
176    Stats::Scalar<> iewDispatchedInsts;
177    Stats::Scalar<> iewDispSquashedInsts;
178    Stats::Scalar<> iewDispLoadInsts;
179    Stats::Scalar<> iewDispStoreInsts;
180    Stats::Scalar<> iewDispNonSpecInsts;
181    Stats::Scalar<> iewIQFullEvents;
182    Stats::Scalar<> iewExecutedInsts;
183    Stats::Scalar<> iewExecLoadInsts;
184    Stats::Scalar<> iewExecStoreInsts;
185    Stats::Scalar<> iewExecSquashedInsts;
186    Stats::Scalar<> memOrderViolationEvents;
187    Stats::Scalar<> predictedTakenIncorrect;
188};
189
190#endif // __CPU_BETA_CPU_IEW_HH__
191