iew.hh revision 11246
12330SN/A/*
213610Sgiacomo.gabrielli@arm.com * Copyright (c) 2010-2012, 2014 ARM Limited
39920Syasuko.eckert@amd.com * All rights reserved
48733Sgeoffrey.blake@arm.com *
58733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall
68733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual
78733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating
88733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software
98733Sgeoffrey.blake@arm.com * licensed hereunder.  You may use the software subject to the license
108733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated
118733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software,
128733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form.
138733Sgeoffrey.blake@arm.com *
148733Sgeoffrey.blake@arm.com * Copyright (c) 2004-2006 The Regents of The University of Michigan
152330SN/A * All rights reserved.
162330SN/A *
172330SN/A * Redistribution and use in source and binary forms, with or without
182330SN/A * modification, are permitted provided that the following conditions are
192330SN/A * met: redistributions of source code must retain the above copyright
202330SN/A * notice, this list of conditions and the following disclaimer;
212330SN/A * redistributions in binary form must reproduce the above copyright
222330SN/A * notice, this list of conditions and the following disclaimer in the
232330SN/A * documentation and/or other materials provided with the distribution;
242330SN/A * neither the name of the copyright holders nor the names of its
252330SN/A * contributors may be used to endorse or promote products derived from
262330SN/A * this software without specific prior written permission.
272330SN/A *
282330SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
292330SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
302330SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
312330SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
322330SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
332330SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
342330SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
352330SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
362330SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
372330SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
382330SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
392330SN/A *
402689Sktlim@umich.edu * Authors: Kevin Lim
412689Sktlim@umich.edu */
422330SN/A
432330SN/A#ifndef __CPU_O3_IEW_HH__
442683Sktlim@umich.edu#define __CPU_O3_IEW_HH__
452683Sktlim@umich.edu
462315SN/A#include <queue>
472972Sgblack@eecs.umich.edu#include <set>
486658Snate@binkert.org
492315SN/A#include "base/statistics.hh"
502683Sktlim@umich.edu#include "cpu/o3/comm.hh"
512680SN/A#include "cpu/o3/lsq.hh"
528733Sgeoffrey.blake@arm.com#include "cpu/o3/scoreboard.hh"
532315SN/A#include "cpu/timebuf.hh"
542315SN/A#include "debug/IEW.hh"
553548Sgblack@eecs.umich.edu#include "sim/probe/probe.hh"
563548Sgblack@eecs.umich.edu
573548Sgblack@eecs.umich.edustruct DerivO3CPUParams;
583548Sgblack@eecs.umich.educlass FUPool;
599020Sgblack@eecs.umich.edu
602330SN/A/**
612315SN/A * DefaultIEW handles both single threaded and SMT IEW
622350SN/A * (issue/execute/writeback).  It handles the dispatching of
632680SN/A * instructions to the LSQ/IQ as part of the issue stage, and has the
642680SN/A * IQ try to issue instructions each cycle. The execute latency is
652683Sktlim@umich.edu * actually tied into the issue latency to allow the IQ to be able to
662683Sktlim@umich.edu * do back-to-back scheduling without having to speculatively schedule
672683Sktlim@umich.edu * instructions. This happens by having the IQ have access to the
682683Sktlim@umich.edu * functional units, and the IQ gets the execution latencies from the
692350SN/A * FUs when it issues instructions. Instructions reach the execute
702680SN/A * stage on the last cycle of their execution, which is when the IQ
712680SN/A * knows to wake up any dependent instructions, allowing back to back
722315SN/A * scheduling. The execute portion of IEW separates memory
732315SN/A * instructions from non-memory instructions, either telling the LSQ
742680SN/A * to execute the instruction, or executing the instruction directly.
752683Sktlim@umich.edu * The writeback portion of IEW completes the instructions by waking
762683Sktlim@umich.edu * up any dependents, and marking the register ready on the
772330SN/A * scoreboard.
782315SN/A */
792315SN/Atemplate<class Impl>
802315SN/Aclass DefaultIEW
812683Sktlim@umich.edu{
822683Sktlim@umich.edu  private:
832680SN/A    //Typedefs from Impl
842683Sktlim@umich.edu    typedef typename Impl::CPUPol CPUPol;
852683Sktlim@umich.edu    typedef typename Impl::DynInstPtr DynInstPtr;
862683Sktlim@umich.edu    typedef typename Impl::O3CPU O3CPU;
872683Sktlim@umich.edu
882683Sktlim@umich.edu    typedef typename CPUPol::IQ IQ;
892315SN/A    typedef typename CPUPol::RenameMap RenameMap;
902315SN/A    typedef typename CPUPol::LSQ LSQ;
912315SN/A
922315SN/A    typedef typename CPUPol::TimeStruct TimeStruct;
932680SN/A    typedef typename CPUPol::IEWStruct IEWStruct;
942315SN/A    typedef typename CPUPol::RenameStruct RenameStruct;
9510190Sakash.bagdia@arm.com    typedef typename CPUPol::IssueStruct IssueStruct;
9610190Sakash.bagdia@arm.com
9710110Sandreas.hansson@arm.com  public:
988733Sgeoffrey.blake@arm.com    /** Overall IEW stage status. Used to determine if the CPU can
9911005Sandreas.sandberg@arm.com     * deschedule itself due to a lack of activity.
1008733Sgeoffrey.blake@arm.com     */
10111005Sandreas.sandberg@arm.com    enum Status {
1022315SN/A        Active,
1038733Sgeoffrey.blake@arm.com        Inactive
1048733Sgeoffrey.blake@arm.com    };
1052315SN/A
1062315SN/A    /** Status for Issue, Execute, and Writeback stages. */
1078733Sgeoffrey.blake@arm.com    enum StageStatus {
10810110Sandreas.hansson@arm.com        Running,
1098733Sgeoffrey.blake@arm.com        Blocked,
1108733Sgeoffrey.blake@arm.com        Idle,
1118733Sgeoffrey.blake@arm.com        StartSquash,
1128733Sgeoffrey.blake@arm.com        Squashing,
1138733Sgeoffrey.blake@arm.com        Unblocking
1142315SN/A    };
11512406Sgabeblack@google.com
1164997Sgblack@eecs.umich.edu  private:
11712406Sgabeblack@google.com    /** Overall stage status. */
1184997Sgblack@eecs.umich.edu    Status _status;
1198887Sgeoffrey.blake@arm.com    /** Dispatch status. */
1208887Sgeoffrey.blake@arm.com    StageStatus dispatchStatus[Impl::MaxThreads];
1218887Sgeoffrey.blake@arm.com    /** Execute status. */
1228887Sgeoffrey.blake@arm.com    StageStatus exeStatus;
1238733Sgeoffrey.blake@arm.com    /** Writeback status. */
1249020Sgblack@eecs.umich.edu    StageStatus wbStatus;
1258733Sgeoffrey.blake@arm.com
1262680SN/A    /** Probe points. */
1272315SN/A    ProbePointArg<DynInstPtr> *ppMispredict;
1283548Sgblack@eecs.umich.edu    ProbePointArg<DynInstPtr> *ppDispatch;
1293548Sgblack@eecs.umich.edu    /** To probe when instruction execution begins. */
1302690Sktlim@umich.edu    ProbePointArg<DynInstPtr> *ppExecute;
1317679Sgblack@eecs.umich.edu    /** To probe when instruction execution is complete. */
1327679Sgblack@eecs.umich.edu    ProbePointArg<DynInstPtr> *ppToCommit;
13311886Sbrandon.potter@amd.com
13411886Sbrandon.potter@amd.com  public:
1358852Sandreas.hansson@arm.com    /** Constructs a DefaultIEW with the given parameters. */
1362690Sktlim@umich.edu    DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params);
1378852Sandreas.hansson@arm.com
1388706Sandreas.hansson@arm.com    /** Returns the name of the DefaultIEW stage. */
1398733Sgeoffrey.blake@arm.com    std::string name() const;
1408733Sgeoffrey.blake@arm.com
1418733Sgeoffrey.blake@arm.com    /** Registers statistics. */
1428733Sgeoffrey.blake@arm.com    void regStats();
1438733Sgeoffrey.blake@arm.com
1448733Sgeoffrey.blake@arm.com    /** Registers probes. */
1458733Sgeoffrey.blake@arm.com    void regProbePoints();
1468733Sgeoffrey.blake@arm.com
1478809Sgblack@eecs.umich.edu    /** Initializes stage; sends back the number of free IQ and LSQ entries. */
1488852Sandreas.hansson@arm.com    void startupStage();
1492690Sktlim@umich.edu
1508733Sgeoffrey.blake@arm.com    /** Sets main time buffer used for backwards communication. */
15111877Sbrandon.potter@amd.com    void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
15211877Sbrandon.potter@amd.com
1532315SN/A    /** Sets time buffer for getting instructions coming from rename. */
1542680SN/A    void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
1552315SN/A
1562315SN/A    /** Sets time buffer to pass on instructions to commit. */
1572330SN/A    void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
1582680SN/A
1592680SN/A    /** Sets pointer to list of active threads. */
1602330SN/A    void setActiveThreads(std::list<ThreadID> *at_ptr);
1612315SN/A
16210407Smitch.hayenga@arm.com    /** Sets pointer to the scoreboard. */
16310407Smitch.hayenga@arm.com    void setScoreboard(Scoreboard *sb_ptr);
1642315SN/A
1652315SN/A    /** Perform sanity checks after a drain. */
16610407Smitch.hayenga@arm.com    void drainSanityCheck() const;
1672315SN/A
1682315SN/A    /** Has the stage drained? */
16910407Smitch.hayenga@arm.com    bool isDrained() const;
1702315SN/A
1712680SN/A    /** Takes over from another CPU's thread. */
1722315SN/A    void takeOverFrom();
1732680SN/A
1742315SN/A    /** Squashes instructions in IEW for a specific thread. */
1752680SN/A    void squash(ThreadID tid);
1763225Sktlim@umich.edu
1772315SN/A    /** Wakes all dependents of a completed instruction. */
1782315SN/A    void wakeDependents(DynInstPtr &inst);
1798733Sgeoffrey.blake@arm.com
1808733Sgeoffrey.blake@arm.com    /** Tells memory dependence unit that a memory instruction needs to be
1818733Sgeoffrey.blake@arm.com     * rescheduled. It will re-execute once replayMemInst() is called.
1828733Sgeoffrey.blake@arm.com     */
1838733Sgeoffrey.blake@arm.com    void rescheduleMemInst(DynInstPtr &inst);
1842315SN/A
1852680SN/A    /** Re-executes all rescheduled memory instructions. */
1862315SN/A    void replayMemInst(DynInstPtr &inst);
1872680SN/A
1882680SN/A    /** Moves memory instruction onto the list of cache blocked instructions */
1892315SN/A    void blockMemInst(DynInstPtr &inst);
1902680SN/A
1912680SN/A    /** Notifies that the cache has become unblocked */
1922315SN/A    void cacheUnblocked();
1932315SN/A
1942680SN/A    /** Sends an instruction to commit through the time buffer. */
1952315SN/A    void instToCommit(DynInstPtr &inst);
1962680SN/A
1972680SN/A    /** Inserts unused instructions of a thread into the skid buffer. */
1982315SN/A    void skidInsert(ThreadID tid);
1992315SN/A
2002315SN/A    /** Returns the max of the number of entries in all of the skid buffers. */
2012315SN/A    int skidCount();
2022680SN/A
2032680SN/A    /** Returns if all of the skid buffers are empty. */
2042315SN/A    bool skidsEmpty();
2052315SN/A
2062315SN/A    /** Updates overall IEW status based on all of the stages' statuses. */
2072315SN/A    void updateStatus();
2082315SN/A
20913557Sgabeblack@google.com    /** Resets entries of the IQ and the LSQ. */
2102315SN/A    void resetEntries();
21113557Sgabeblack@google.com
21213557Sgabeblack@google.com    /** Tells the CPU to wakeup if it has descheduled itself due to no
21313557Sgabeblack@google.com     * activity. Used mainly by the LdWritebackEvent.
21413557Sgabeblack@google.com     */
21513557Sgabeblack@google.com    void wakeCPU();
2162315SN/A
21712109SRekai.GonzalezAlberquilla@arm.com    /** Reports to the CPU that there is activity this cycle. */
21812109SRekai.GonzalezAlberquilla@arm.com    void activityThisCycle();
21912109SRekai.GonzalezAlberquilla@arm.com
22012109SRekai.GonzalezAlberquilla@arm.com    /** Tells CPU that the IEW stage is active and running. */
22112109SRekai.GonzalezAlberquilla@arm.com    inline void activateStage();
22212109SRekai.GonzalezAlberquilla@arm.com
22312109SRekai.GonzalezAlberquilla@arm.com    /** Tells CPU that the IEW stage is inactive and idle. */
22412109SRekai.GonzalezAlberquilla@arm.com    inline void deactivateStage();
22512109SRekai.GonzalezAlberquilla@arm.com
22612109SRekai.GonzalezAlberquilla@arm.com    /** Returns if the LSQ has any stores to writeback. */
22712109SRekai.GonzalezAlberquilla@arm.com    bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); }
22812109SRekai.GonzalezAlberquilla@arm.com
22912109SRekai.GonzalezAlberquilla@arm.com    /** Returns if the LSQ has any stores to writeback. */
23012109SRekai.GonzalezAlberquilla@arm.com    bool hasStoresToWB(ThreadID tid) { return ldstQueue.hasStoresToWB(tid); }
23112109SRekai.GonzalezAlberquilla@arm.com
23212109SRekai.GonzalezAlberquilla@arm.com    /** Check misprediction  */
23312109SRekai.GonzalezAlberquilla@arm.com    void checkMisprediction(DynInstPtr &inst);
23412109SRekai.GonzalezAlberquilla@arm.com
23512109SRekai.GonzalezAlberquilla@arm.com  private:
23612109SRekai.GonzalezAlberquilla@arm.com    /** Sends commit proper information for a squash due to a branch
23712109SRekai.GonzalezAlberquilla@arm.com     * mispredict.
23812109SRekai.GonzalezAlberquilla@arm.com     */
23912109SRekai.GonzalezAlberquilla@arm.com    void squashDueToBranch(DynInstPtr &inst, ThreadID tid);
24012109SRekai.GonzalezAlberquilla@arm.com
24112109SRekai.GonzalezAlberquilla@arm.com    /** Sends commit proper information for a squash due to a memory order
24212109SRekai.GonzalezAlberquilla@arm.com     * violation.
24312109SRekai.GonzalezAlberquilla@arm.com     */
24412109SRekai.GonzalezAlberquilla@arm.com    void squashDueToMemOrder(DynInstPtr &inst, ThreadID tid);
24512109SRekai.GonzalezAlberquilla@arm.com
24612109SRekai.GonzalezAlberquilla@arm.com    /** Sets Dispatch to blocked, and signals back to other stages to block. */
24712109SRekai.GonzalezAlberquilla@arm.com    void block(ThreadID tid);
24812109SRekai.GonzalezAlberquilla@arm.com
24912109SRekai.GonzalezAlberquilla@arm.com    /** Unblocks Dispatch if the skid buffer is empty, and signals back to
25012109SRekai.GonzalezAlberquilla@arm.com     * other stages to unblock.
25112109SRekai.GonzalezAlberquilla@arm.com     */
25212109SRekai.GonzalezAlberquilla@arm.com    void unblock(ThreadID tid);
25312109SRekai.GonzalezAlberquilla@arm.com
25412109SRekai.GonzalezAlberquilla@arm.com    /** Determines proper actions to take given Dispatch's status. */
25512109SRekai.GonzalezAlberquilla@arm.com    void dispatch(ThreadID tid);
25612109SRekai.GonzalezAlberquilla@arm.com
25712109SRekai.GonzalezAlberquilla@arm.com    /** Dispatches instructions to IQ and LSQ. */
25812109SRekai.GonzalezAlberquilla@arm.com    void dispatchInsts(ThreadID tid);
25912109SRekai.GonzalezAlberquilla@arm.com
26012109SRekai.GonzalezAlberquilla@arm.com    /** Executes instructions. In the case of memory operations, it informs the
26112109SRekai.GonzalezAlberquilla@arm.com     * LSQ to execute the instructions. Also handles any redirects that occur
26212109SRekai.GonzalezAlberquilla@arm.com     * due to the executed instructions.
26312109SRekai.GonzalezAlberquilla@arm.com     */
26412109SRekai.GonzalezAlberquilla@arm.com    void executeInsts();
26512109SRekai.GonzalezAlberquilla@arm.com
26613610Sgiacomo.gabrielli@arm.com    /** Writebacks instructions. In our model, the instruction's execute()
26713610Sgiacomo.gabrielli@arm.com     * function atomically reads registers, executes, and writes registers.
26813610Sgiacomo.gabrielli@arm.com     * Thus this writeback only wakes up dependent instructions, and informs
26913610Sgiacomo.gabrielli@arm.com     * the scoreboard of registers becoming ready.
27013610Sgiacomo.gabrielli@arm.com     */
27113610Sgiacomo.gabrielli@arm.com    void writebackInsts();
2729920Syasuko.eckert@amd.com
2739920Syasuko.eckert@amd.com    /** Returns the number of valid, non-squashed instructions coming from
2749920Syasuko.eckert@amd.com     * rename to dispatch.
27513557Sgabeblack@google.com     */
27613557Sgabeblack@google.com    unsigned validInstsFromRename();
2772315SN/A
2782680SN/A    /** Checks if any of the stall conditions are currently true. */
2792680SN/A    bool checkStall(ThreadID tid);
2802315SN/A
2812315SN/A    /** Processes inputs and changes state accordingly. */
28213557Sgabeblack@google.com    void checkSignalsAndUpdate(ThreadID tid);
28313557Sgabeblack@google.com
2842669SN/A    /** Removes instructions from rename from a thread's instruction list. */
2852680SN/A    void emptyRenameInsts(ThreadID tid);
2862680SN/A
2872315SN/A    /** Sorts instructions coming from rename into lists separated by thread. */
2882315SN/A    void sortInsts();
28913557Sgabeblack@google.com
29013557Sgabeblack@google.com  public:
29112109SRekai.GonzalezAlberquilla@arm.com    /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and
29212109SRekai.GonzalezAlberquilla@arm.com     * Writeback to run for one cycle.
29312109SRekai.GonzalezAlberquilla@arm.com     */
29412109SRekai.GonzalezAlberquilla@arm.com    void tick();
29512109SRekai.GonzalezAlberquilla@arm.com
29613557Sgabeblack@google.com  private:
29713557Sgabeblack@google.com    /** Updates execution stats based on the instruction. */
29812109SRekai.GonzalezAlberquilla@arm.com    void updateExeInstStats(DynInstPtr &inst);
29912109SRekai.GonzalezAlberquilla@arm.com
30012109SRekai.GonzalezAlberquilla@arm.com    /** Pointer to main time buffer used for backwards communication. */
30112109SRekai.GonzalezAlberquilla@arm.com    TimeBuffer<TimeStruct> *timeBuffer;
30212109SRekai.GonzalezAlberquilla@arm.com
30313557Sgabeblack@google.com    /** Wire to write information heading to previous stages. */
30413610Sgiacomo.gabrielli@arm.com    typename TimeBuffer<TimeStruct>::wire toFetch;
30513610Sgiacomo.gabrielli@arm.com
30613610Sgiacomo.gabrielli@arm.com    /** Wire to get commit's output from backwards time buffer. */
30713610Sgiacomo.gabrielli@arm.com    typename TimeBuffer<TimeStruct>::wire fromCommit;
30813610Sgiacomo.gabrielli@arm.com
30913610Sgiacomo.gabrielli@arm.com    /** Wire to write information heading to previous stages. */
31013610Sgiacomo.gabrielli@arm.com    typename TimeBuffer<TimeStruct>::wire toRename;
31113557Sgabeblack@google.com
3129920Syasuko.eckert@amd.com    /** Rename instruction queue interface. */
3139920Syasuko.eckert@amd.com    TimeBuffer<RenameStruct> *renameQueue;
3149920Syasuko.eckert@amd.com
3159920Syasuko.eckert@amd.com    /** Wire to get rename's output from rename queue. */
3169920Syasuko.eckert@amd.com    typename TimeBuffer<RenameStruct>::wire fromRename;
3178733Sgeoffrey.blake@arm.com
3188733Sgeoffrey.blake@arm.com    /** Issue stage queue. */
3198733Sgeoffrey.blake@arm.com    TimeBuffer<IssueStruct> issueToExecQueue;
3202315SN/A
3218733Sgeoffrey.blake@arm.com    /** Wire to read information from the issue stage time queue. */
32213557Sgabeblack@google.com    typename TimeBuffer<IssueStruct>::wire fromIssue;
32313557Sgabeblack@google.com
3242315SN/A    /**
3258733Sgeoffrey.blake@arm.com     * IEW stage time buffer.  Holds ROB indices of instructions that
3268733Sgeoffrey.blake@arm.com     * can be marked as completed.
3278733Sgeoffrey.blake@arm.com     */
3282315SN/A    TimeBuffer<IEWStruct> *iewQueue;
3298733Sgeoffrey.blake@arm.com
3302315SN/A    /** Wire to write infromation heading to commit. */
3312315SN/A    typename TimeBuffer<IEWStruct>::wire toCommit;
33213557Sgabeblack@google.com
33313557Sgabeblack@google.com    /** Queue of all instructions coming from rename this cycle. */
33411886Sbrandon.potter@amd.com    std::queue<DynInstPtr> insts[Impl::MaxThreads];
33511886Sbrandon.potter@amd.com
33611886Sbrandon.potter@amd.com    /** Skid buffer between rename and IEW. */
33711886Sbrandon.potter@amd.com    std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
33811886Sbrandon.potter@amd.com
33913557Sgabeblack@google.com    /** Scoreboard pointer. */
34013557Sgabeblack@google.com    Scoreboard* scoreboard;
3412315SN/A
3428733Sgeoffrey.blake@arm.com  private:
3432315SN/A    /** CPU pointer. */
3442315SN/A    O3CPU *cpu;
3458733Sgeoffrey.blake@arm.com
3468733Sgeoffrey.blake@arm.com    /** Records if IEW has written to the time buffer this cycle, so that the
3478733Sgeoffrey.blake@arm.com     * CPU can deschedule itself if there is no activity.
3482669SN/A     */
3498733Sgeoffrey.blake@arm.com    bool wroteToTimeBuffer;
3508733Sgeoffrey.blake@arm.com
3518733Sgeoffrey.blake@arm.com    /** Debug function to print instructions that are issued this cycle. */
3528733Sgeoffrey.blake@arm.com    void printAvailableInsts();
3538733Sgeoffrey.blake@arm.com
3548733Sgeoffrey.blake@arm.com  public:
3558733Sgeoffrey.blake@arm.com    /** Instruction queue. */
3562669SN/A    IQ instQueue;
35713557Sgabeblack@google.com
3584172Ssaidi@eecs.umich.edu    /** Load / store queue. */
3594172Ssaidi@eecs.umich.edu    LSQ ldstQueue;
36013557Sgabeblack@google.com
3612680SN/A    /** Pointer to the functional unit pool. */
3622315SN/A    FUPool *fuPool;
36313557Sgabeblack@google.com    /** Records if the LSQ needs to be updated on the next cycle, so that
36413582Sgabeblack@google.com     * IEW knows if there will be activity on the next cycle.
3654172Ssaidi@eecs.umich.edu     */
3668733Sgeoffrey.blake@arm.com    bool updateLSQNextCycle;
3678733Sgeoffrey.blake@arm.com
3684172Ssaidi@eecs.umich.edu  private:
3694172Ssaidi@eecs.umich.edu    /** Records if there is a fetch redirect on this cycle for each thread. */
3704172Ssaidi@eecs.umich.edu    bool fetchRedirect[Impl::MaxThreads];
3712315SN/A
37213557Sgabeblack@google.com    /** Records if the queues have been changed (inserted or issued insts),
37313582Sgabeblack@google.com     * so that IEW knows to broadcast the updated amount of free entries.
3742315SN/A     */
3758733Sgeoffrey.blake@arm.com    bool updatedQueues;
3768733Sgeoffrey.blake@arm.com
3772680SN/A    /** Commit to IEW delay. */
3783468Sgblack@eecs.umich.edu    Cycles commitToIEWDelay;
3792315SN/A
3802315SN/A    /** Rename to IEW delay. */
38113557Sgabeblack@google.com    Cycles renameToIEWDelay;
38213557Sgabeblack@google.com
38313557Sgabeblack@google.com    /**
38412106SRekai.GonzalezAlberquilla@arm.com     * Issue to execute delay. What this actually represents is
38512106SRekai.GonzalezAlberquilla@arm.com     * the amount of time it takes for an instruction to wake up, be
3868733Sgeoffrey.blake@arm.com     * scheduled, and sent to a FU for execution.
3872315SN/A     */
3882680SN/A    Cycles issueToExecuteDelay;
3892315SN/A
39013557Sgabeblack@google.com    /** Width of dispatch, in instructions. */
39113557Sgabeblack@google.com    unsigned dispatchWidth;
3922315SN/A
3932680SN/A    /** Width of issue, in instructions. */
3942315SN/A    unsigned issueWidth;
3952315SN/A
3962680SN/A    /** Index into queue of instructions being written back. */
3979426SAndreas.Sandberg@ARM.com    unsigned wbNumInst;
39813557Sgabeblack@google.com
3999426SAndreas.Sandberg@ARM.com    /** Cycle number within the queue of instructions being written back.
40013557Sgabeblack@google.com     * Used in case there are too many instructions writing back at the current
40113557Sgabeblack@google.com     * cycle and writesbacks need to be scheduled for the future. See comments
40213557Sgabeblack@google.com     * in instToCommit().
40313557Sgabeblack@google.com     */
40413557Sgabeblack@google.com    unsigned wbCycle;
4059426SAndreas.Sandberg@ARM.com
40613557Sgabeblack@google.com    /** Writeback width. */
40713557Sgabeblack@google.com    unsigned wbWidth;
40813557Sgabeblack@google.com
40913557Sgabeblack@google.com    /** Number of active threads. */
41013557Sgabeblack@google.com    ThreadID numThreads;
4119426SAndreas.Sandberg@ARM.com
41213557Sgabeblack@google.com    /** Pointer to list of active threads. */
41313557Sgabeblack@google.com    std::list<ThreadID> *activeThreads;
41413557Sgabeblack@google.com
41513557Sgabeblack@google.com    /** Maximum size of the skid buffer. */
41613557Sgabeblack@google.com    unsigned skidBufferMax;
4179920Syasuko.eckert@amd.com
41813557Sgabeblack@google.com    /** Stat for total number of idle cycles. */
41913557Sgabeblack@google.com    Stats::Scalar iewIdleCycles;
42013557Sgabeblack@google.com    /** Stat for total number of squashing cycles. */
42113557Sgabeblack@google.com    Stats::Scalar iewSquashCycles;
42213557Sgabeblack@google.com    /** Stat for total number of blocking cycles. */
42312109SRekai.GonzalezAlberquilla@arm.com    Stats::Scalar iewBlockCycles;
42412109SRekai.GonzalezAlberquilla@arm.com    /** Stat for total number of unblocking cycles. */
42512109SRekai.GonzalezAlberquilla@arm.com    Stats::Scalar iewUnblockCycles;
42612109SRekai.GonzalezAlberquilla@arm.com    /** Stat for total number of instructions dispatched. */
42713557Sgabeblack@google.com    Stats::Scalar iewDispatchedInsts;
42813557Sgabeblack@google.com    /** Stat for total number of squashed instructions dispatch skips. */
42913557Sgabeblack@google.com    Stats::Scalar iewDispSquashedInsts;
43013557Sgabeblack@google.com    /** Stat for total number of dispatched load instructions. */
43113557Sgabeblack@google.com    Stats::Scalar iewDispLoadInsts;
43212109SRekai.GonzalezAlberquilla@arm.com    /** Stat for total number of dispatched store instructions. */
43312109SRekai.GonzalezAlberquilla@arm.com    Stats::Scalar iewDispStoreInsts;
43412109SRekai.GonzalezAlberquilla@arm.com    /** Stat for total number of dispatched non speculative instructions. */
43512109SRekai.GonzalezAlberquilla@arm.com    Stats::Scalar iewDispNonSpecInsts;
43612109SRekai.GonzalezAlberquilla@arm.com    /** Stat for number of times the IQ becomes full. */
43712109SRekai.GonzalezAlberquilla@arm.com    Stats::Scalar iewIQFullEvents;
43812109SRekai.GonzalezAlberquilla@arm.com    /** Stat for number of times the LSQ becomes full. */
43912109SRekai.GonzalezAlberquilla@arm.com    Stats::Scalar iewLSQFullEvents;
44012109SRekai.GonzalezAlberquilla@arm.com    /** Stat for total number of memory ordering violation events. */
44112109SRekai.GonzalezAlberquilla@arm.com    Stats::Scalar memOrderViolationEvents;
44212109SRekai.GonzalezAlberquilla@arm.com    /** Stat for total number of incorrect predicted taken branches. */
44312109SRekai.GonzalezAlberquilla@arm.com    Stats::Scalar predictedTakenIncorrect;
44413610Sgiacomo.gabrielli@arm.com    /** Stat for total number of incorrect predicted not taken branches. */
44513610Sgiacomo.gabrielli@arm.com    Stats::Scalar predictedNotTakenIncorrect;
44613610Sgiacomo.gabrielli@arm.com    /** Stat for total number of mispredicted branches detected at execute. */
44713610Sgiacomo.gabrielli@arm.com    Stats::Formula branchMispredicts;
44813610Sgiacomo.gabrielli@arm.com
44913610Sgiacomo.gabrielli@arm.com    /** Stat for total number of executed instructions. */
45013610Sgiacomo.gabrielli@arm.com    Stats::Scalar iewExecutedInsts;
45113610Sgiacomo.gabrielli@arm.com    /** Stat for total number of executed load instructions. */
45213610Sgiacomo.gabrielli@arm.com    Stats::Vector iewExecLoadInsts;
4539920Syasuko.eckert@amd.com    /** Stat for total number of executed store instructions. */
4549920Syasuko.eckert@amd.com//    Stats::Scalar iewExecStoreInsts;
4559920Syasuko.eckert@amd.com    /** Stat for total number of squashed instructions skipped at execute. */
4569920Syasuko.eckert@amd.com    Stats::Scalar iewExecSquashedInsts;
4579920Syasuko.eckert@amd.com    /** Number of executed software prefetches. */
4582315SN/A    Stats::Vector iewExecutedSwp;
4592315SN/A    /** Number of executed nops. */
4602315SN/A    Stats::Vector iewExecutedNop;
461    /** Number of executed meomory references. */
462    Stats::Vector iewExecutedRefs;
463    /** Number of executed branches. */
464    Stats::Vector iewExecutedBranches;
465    /** Number of executed store instructions. */
466    Stats::Formula iewExecStoreInsts;
467    /** Number of instructions executed per cycle. */
468    Stats::Formula iewExecRate;
469
470    /** Number of instructions sent to commit. */
471    Stats::Vector iewInstsToCommit;
472    /** Number of instructions that writeback. */
473    Stats::Vector writebackCount;
474    /** Number of instructions that wake consumers. */
475    Stats::Vector producerInst;
476    /** Number of instructions that wake up from producers. */
477    Stats::Vector consumerInst;
478    /** Number of instructions per cycle written back. */
479    Stats::Formula wbRate;
480    /** Average number of woken instructions per writeback. */
481    Stats::Formula wbFanout;
482};
483
484#endif // __CPU_O3_IEW_HH__
485