iew.hh revision 1061 
1//Todo: Update with statuses.
2//Need to handle delaying writes to the writeback bus if it's full at the
3//given time.  Load store queue.
4
5#ifndef __SIMPLE_IEW_HH__
6#define __SIMPLE_IEW_HH__
7
8#include <queue>
9
10#include "base/timebuf.hh"
11#include "cpu/beta_cpu/comm.hh"
12
13//Can IEW even stall?  Space should be available/allocated already...maybe
14//if there's not enough write ports on the ROB or waiting for CDB
15//arbitration.
16template<class Impl, class IQ>
17class SimpleIEW
18{
19  private:
20    //Typedefs from Impl
21    typedef typename Impl::ISA ISA;
22    typedef typename Impl::CPUPol CPUPol;
23    typedef typename Impl::DynInstPtr DynInstPtr;
24    typedef typename Impl::FullCPU FullCPU;
25    typedef typename Impl::Params Params;
26
27    typedef typename CPUPol::RenameMap RenameMap;
28    typedef typename CPUPol::LDSTQ LDSTQ;
29
30    typedef typename CPUPol::TimeStruct TimeStruct;
31    typedef typename CPUPol::IEWStruct IEWStruct;
32    typedef typename CPUPol::RenameStruct RenameStruct;
33    typedef typename CPUPol::IssueStruct IssueStruct;
34
35  public:
36    enum Status {
37        Running,
38        Blocked,
39        Idle,
40        Squashing,
41        Unblocking
42    };
43
44  private:
45    Status _status;
46    Status _issueStatus;
47    Status _exeStatus;
48    Status _wbStatus;
49
50  public:
51    void squash();
52
53    void squash(DynInstPtr &inst);
54
55    void block();
56
57    inline void unblock();
58
59  public:
60    SimpleIEW(Params &params);
61
62    void setCPU(FullCPU *cpu_ptr);
63
64    void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
65
66    void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
67
68    void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
69
70    void setRenameMap(RenameMap *rm_ptr);
71
72    void wakeDependents(DynInstPtr &inst);
73
74    void tick();
75
76    void iew();
77
78  private:
79    //Interfaces to objects inside and outside of IEW.
80    /** Time buffer interface. */
81    TimeBuffer<TimeStruct> *timeBuffer;
82
83    /** Wire to get commit's output from backwards time buffer. */
84    typename TimeBuffer<TimeStruct>::wire fromCommit;
85
86    /** Wire to write information heading to previous stages. */
87    typename TimeBuffer<TimeStruct>::wire toRename;
88
89    /** Rename instruction queue interface. */
90    TimeBuffer<RenameStruct> *renameQueue;
91
92    /** Wire to get rename's output from rename queue. */
93    typename TimeBuffer<RenameStruct>::wire fromRename;
94
95    /** Issue stage queue. */
96    TimeBuffer<IssueStruct> issueToExecQueue;
97
98    /** Wire to read information from the issue stage time queue. */
99    typename TimeBuffer<IssueStruct>::wire fromIssue;
100
101    /**
102     * IEW stage time buffer.  Holds ROB indices of instructions that
103     * can be marked as completed.
104     */
105    TimeBuffer<IEWStruct> *iewQueue;
106
107    /** Wire to write infromation heading to commit. */
108    typename TimeBuffer<IEWStruct>::wire toCommit;
109
110    //Will need internal queue to hold onto instructions coming from
111    //the rename stage in case of a stall.
112    /** Skid buffer between rename and IEW. */
113    std::queue<RenameStruct> skidBuffer;
114
115    /** Instruction queue. */
116    IQ instQueue;
117
118    LDSTQ ldstQueue;
119
120    /** Pointer to rename map.  Might not want this stage to directly
121     *  access this though...
122     */
123    RenameMap *renameMap;
124
125    /** CPU interface. */
126    FullCPU *cpu;
127
128  private:
129    /** Commit to IEW delay, in ticks. */
130    unsigned commitToIEWDelay;
131
132    /** Rename to IEW delay, in ticks. */
133    unsigned renameToIEWDelay;
134
135    /**
136     * Issue to execute delay, in ticks.  What this actually represents is
137     * the amount of time it takes for an instruction to wake up, be
138     * scheduled, and sent to a FU for execution.
139     */
140    unsigned issueToExecuteDelay;
141
142    /** Width of issue's read path, in instructions.  The read path is both
143     *  the skid buffer and the rename instruction queue.
144     *  Note to self: is this really different than issueWidth?
145     */
146    unsigned issueReadWidth;
147
148    /** Width of issue, in instructions. */
149    unsigned issueWidth;
150
151    /** Width of execute, in instructions.  Might make more sense to break
152     *  down into FP vs int.
153     */
154    unsigned executeWidth;
155
156    /** Number of cycles stage has been squashing.  Used so that the stage
157     *  knows when it can start unblocking, which is when the previous stage
158     *  has received the stall signal and clears up its outputs.
159     */
160    unsigned cyclesSquashing;
161
162    //Will implement later
163    //Load queue interface (probably one and the same)
164    //Store queue interface
165};
166
167#endif
168