iew.hh revision 10023
17841Sgblack@eecs.umich.edu/* 28332Snate@binkert.org * Copyright (c) 2010-2012 ARM Limited 37841Sgblack@eecs.umich.edu * All rights reserved 47841Sgblack@eecs.umich.edu * 57841Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67841Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77841Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87841Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97841Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107841Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117841Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127841Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137841Sgblack@eecs.umich.edu * 147841Sgblack@eecs.umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 157841Sgblack@eecs.umich.edu * All rights reserved. 167841Sgblack@eecs.umich.edu * 177841Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 187841Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 197841Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 207841Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 217841Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 227841Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 237841Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 247841Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 257841Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 267841Sgblack@eecs.umich.edu * this software without specific prior written permission. 277841Sgblack@eecs.umich.edu * 287841Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 297841Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 307841Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3111793Sbrandon.potter@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3211793Sbrandon.potter@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 337841Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 347841Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 357841Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 367841Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 377841Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 387841Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 397841Sgblack@eecs.umich.edu * 407841Sgblack@eecs.umich.edu * Authors: Kevin Lim 417841Sgblack@eecs.umich.edu */ 427841Sgblack@eecs.umich.edu 437841Sgblack@eecs.umich.edu#ifndef __CPU_O3_IEW_HH__ 447841Sgblack@eecs.umich.edu#define __CPU_O3_IEW_HH__ 457841Sgblack@eecs.umich.edu 467841Sgblack@eecs.umich.edu#include <queue> 477841Sgblack@eecs.umich.edu#include <set> 487841Sgblack@eecs.umich.edu 497841Sgblack@eecs.umich.edu#include "base/statistics.hh" 507841Sgblack@eecs.umich.edu#include "cpu/o3/comm.hh" 517841Sgblack@eecs.umich.edu#include "cpu/o3/lsq.hh" 527841Sgblack@eecs.umich.edu#include "cpu/o3/scoreboard.hh" 537841Sgblack@eecs.umich.edu#include "cpu/timebuf.hh" 547841Sgblack@eecs.umich.edu#include "debug/IEW.hh" 557841Sgblack@eecs.umich.edu#include "sim/probe/probe.hh" 567841Sgblack@eecs.umich.edu 577841Sgblack@eecs.umich.edustruct DerivO3CPUParams; 587841Sgblack@eecs.umich.educlass FUPool; 597841Sgblack@eecs.umich.edu 607841Sgblack@eecs.umich.edu/** 617841Sgblack@eecs.umich.edu * DefaultIEW handles both single threaded and SMT IEW 627841Sgblack@eecs.umich.edu * (issue/execute/writeback). It handles the dispatching of 637841Sgblack@eecs.umich.edu * instructions to the LSQ/IQ as part of the issue stage, and has the 647841Sgblack@eecs.umich.edu * IQ try to issue instructions each cycle. The execute latency is 657841Sgblack@eecs.umich.edu * actually tied into the issue latency to allow the IQ to be able to 667841Sgblack@eecs.umich.edu * do back-to-back scheduling without having to speculatively schedule 677841Sgblack@eecs.umich.edu * instructions. This happens by having the IQ have access to the 687841Sgblack@eecs.umich.edu * functional units, and the IQ gets the execution latencies from the 697841Sgblack@eecs.umich.edu * FUs when it issues instructions. Instructions reach the execute 707841Sgblack@eecs.umich.edu * stage on the last cycle of their execution, which is when the IQ 717841Sgblack@eecs.umich.edu * knows to wake up any dependent instructions, allowing back to back 727841Sgblack@eecs.umich.edu * scheduling. The execute portion of IEW separates memory 737841Sgblack@eecs.umich.edu * instructions from non-memory instructions, either telling the LSQ 747841Sgblack@eecs.umich.edu * to execute the instruction, or executing the instruction directly. 757841Sgblack@eecs.umich.edu * The writeback portion of IEW completes the instructions by waking 767841Sgblack@eecs.umich.edu * up any dependents, and marking the register ready on the 777841Sgblack@eecs.umich.edu * scoreboard. 787841Sgblack@eecs.umich.edu */ 797841Sgblack@eecs.umich.edutemplate<class Impl> 807841Sgblack@eecs.umich.educlass DefaultIEW 817841Sgblack@eecs.umich.edu{ 827841Sgblack@eecs.umich.edu private: 837841Sgblack@eecs.umich.edu //Typedefs from Impl 847841Sgblack@eecs.umich.edu typedef typename Impl::CPUPol CPUPol; 857841Sgblack@eecs.umich.edu typedef typename Impl::DynInstPtr DynInstPtr; 867841Sgblack@eecs.umich.edu typedef typename Impl::O3CPU O3CPU; 877841Sgblack@eecs.umich.edu 887841Sgblack@eecs.umich.edu typedef typename CPUPol::IQ IQ; 897841Sgblack@eecs.umich.edu typedef typename CPUPol::RenameMap RenameMap; 907841Sgblack@eecs.umich.edu typedef typename CPUPol::LSQ LSQ; 917841Sgblack@eecs.umich.edu 927841Sgblack@eecs.umich.edu typedef typename CPUPol::TimeStruct TimeStruct; 937841Sgblack@eecs.umich.edu typedef typename CPUPol::IEWStruct IEWStruct; 947841Sgblack@eecs.umich.edu typedef typename CPUPol::RenameStruct RenameStruct; 95 typedef typename CPUPol::IssueStruct IssueStruct; 96 97 public: 98 /** Overall IEW stage status. Used to determine if the CPU can 99 * deschedule itself due to a lack of activity. 100 */ 101 enum Status { 102 Active, 103 Inactive 104 }; 105 106 /** Status for Issue, Execute, and Writeback stages. */ 107 enum StageStatus { 108 Running, 109 Blocked, 110 Idle, 111 StartSquash, 112 Squashing, 113 Unblocking 114 }; 115 116 private: 117 /** Overall stage status. */ 118 Status _status; 119 /** Dispatch status. */ 120 StageStatus dispatchStatus[Impl::MaxThreads]; 121 /** Execute status. */ 122 StageStatus exeStatus; 123 /** Writeback status. */ 124 StageStatus wbStatus; 125 126 /** Probe points. */ 127 ProbePointArg<DynInstPtr> *ppMispredict; 128 ProbePointArg<DynInstPtr> *ppDispatch; 129 130 public: 131 /** Constructs a DefaultIEW with the given parameters. */ 132 DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params); 133 134 /** Returns the name of the DefaultIEW stage. */ 135 std::string name() const; 136 137 /** Registers statistics. */ 138 void regStats(); 139 140 /** Registers probes. */ 141 void regProbePoints(); 142 143 /** Initializes stage; sends back the number of free IQ and LSQ entries. */ 144 void startupStage(); 145 146 /** Sets main time buffer used for backwards communication. */ 147 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 148 149 /** Sets time buffer for getting instructions coming from rename. */ 150 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 151 152 /** Sets time buffer to pass on instructions to commit. */ 153 void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 154 155 /** Sets pointer to list of active threads. */ 156 void setActiveThreads(std::list<ThreadID> *at_ptr); 157 158 /** Sets pointer to the scoreboard. */ 159 void setScoreboard(Scoreboard *sb_ptr); 160 161 /** Perform sanity checks after a drain. */ 162 void drainSanityCheck() const; 163 164 /** Has the stage drained? */ 165 bool isDrained() const; 166 167 /** Takes over from another CPU's thread. */ 168 void takeOverFrom(); 169 170 /** Squashes instructions in IEW for a specific thread. */ 171 void squash(ThreadID tid); 172 173 /** Wakes all dependents of a completed instruction. */ 174 void wakeDependents(DynInstPtr &inst); 175 176 /** Tells memory dependence unit that a memory instruction needs to be 177 * rescheduled. It will re-execute once replayMemInst() is called. 178 */ 179 void rescheduleMemInst(DynInstPtr &inst); 180 181 /** Re-executes all rescheduled memory instructions. */ 182 void replayMemInst(DynInstPtr &inst); 183 184 /** Sends an instruction to commit through the time buffer. */ 185 void instToCommit(DynInstPtr &inst); 186 187 /** Inserts unused instructions of a thread into the skid buffer. */ 188 void skidInsert(ThreadID tid); 189 190 /** Returns the max of the number of entries in all of the skid buffers. */ 191 int skidCount(); 192 193 /** Returns if all of the skid buffers are empty. */ 194 bool skidsEmpty(); 195 196 /** Updates overall IEW status based on all of the stages' statuses. */ 197 void updateStatus(); 198 199 /** Resets entries of the IQ and the LSQ. */ 200 void resetEntries(); 201 202 /** Tells the CPU to wakeup if it has descheduled itself due to no 203 * activity. Used mainly by the LdWritebackEvent. 204 */ 205 void wakeCPU(); 206 207 /** Reports to the CPU that there is activity this cycle. */ 208 void activityThisCycle(); 209 210 /** Tells CPU that the IEW stage is active and running. */ 211 inline void activateStage(); 212 213 /** Tells CPU that the IEW stage is inactive and idle. */ 214 inline void deactivateStage(); 215 216 /** Returns if the LSQ has any stores to writeback. */ 217 bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); } 218 219 /** Returns if the LSQ has any stores to writeback. */ 220 bool hasStoresToWB(ThreadID tid) { return ldstQueue.hasStoresToWB(tid); } 221 222 void incrWb(InstSeqNum &sn) 223 { 224 ++wbOutstanding; 225 if (wbOutstanding == wbMax) 226 ableToIssue = false; 227 DPRINTF(IEW, "wbOutstanding: %i [sn:%lli]\n", wbOutstanding, sn); 228 assert(wbOutstanding <= wbMax); 229#ifdef DEBUG 230 wbList.insert(sn); 231#endif 232 } 233 234 void decrWb(InstSeqNum &sn) 235 { 236 if (wbOutstanding == wbMax) 237 ableToIssue = true; 238 wbOutstanding--; 239 DPRINTF(IEW, "wbOutstanding: %i [sn:%lli]\n", wbOutstanding, sn); 240 assert(wbOutstanding >= 0); 241#ifdef DEBUG 242 assert(wbList.find(sn) != wbList.end()); 243 wbList.erase(sn); 244#endif 245 } 246 247#ifdef DEBUG 248 std::set<InstSeqNum> wbList; 249 250 void dumpWb() 251 { 252 std::set<InstSeqNum>::iterator wb_it = wbList.begin(); 253 while (wb_it != wbList.end()) { 254 cprintf("[sn:%lli]\n", 255 (*wb_it)); 256 wb_it++; 257 } 258 } 259#endif 260 261 bool canIssue() { return ableToIssue; } 262 263 bool ableToIssue; 264 265 /** Check misprediction */ 266 void checkMisprediction(DynInstPtr &inst); 267 268 private: 269 /** Sends commit proper information for a squash due to a branch 270 * mispredict. 271 */ 272 void squashDueToBranch(DynInstPtr &inst, ThreadID tid); 273 274 /** Sends commit proper information for a squash due to a memory order 275 * violation. 276 */ 277 void squashDueToMemOrder(DynInstPtr &inst, ThreadID tid); 278 279 /** Sends commit proper information for a squash due to memory becoming 280 * blocked (younger issued instructions must be retried). 281 */ 282 void squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid); 283 284 /** Sets Dispatch to blocked, and signals back to other stages to block. */ 285 void block(ThreadID tid); 286 287 /** Unblocks Dispatch if the skid buffer is empty, and signals back to 288 * other stages to unblock. 289 */ 290 void unblock(ThreadID tid); 291 292 /** Determines proper actions to take given Dispatch's status. */ 293 void dispatch(ThreadID tid); 294 295 /** Dispatches instructions to IQ and LSQ. */ 296 void dispatchInsts(ThreadID tid); 297 298 /** Executes instructions. In the case of memory operations, it informs the 299 * LSQ to execute the instructions. Also handles any redirects that occur 300 * due to the executed instructions. 301 */ 302 void executeInsts(); 303 304 /** Writebacks instructions. In our model, the instruction's execute() 305 * function atomically reads registers, executes, and writes registers. 306 * Thus this writeback only wakes up dependent instructions, and informs 307 * the scoreboard of registers becoming ready. 308 */ 309 void writebackInsts(); 310 311 /** Returns the number of valid, non-squashed instructions coming from 312 * rename to dispatch. 313 */ 314 unsigned validInstsFromRename(); 315 316 /** Reads the stall signals. */ 317 void readStallSignals(ThreadID tid); 318 319 /** Checks if any of the stall conditions are currently true. */ 320 bool checkStall(ThreadID tid); 321 322 /** Processes inputs and changes state accordingly. */ 323 void checkSignalsAndUpdate(ThreadID tid); 324 325 /** Removes instructions from rename from a thread's instruction list. */ 326 void emptyRenameInsts(ThreadID tid); 327 328 /** Sorts instructions coming from rename into lists separated by thread. */ 329 void sortInsts(); 330 331 public: 332 /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and 333 * Writeback to run for one cycle. 334 */ 335 void tick(); 336 337 private: 338 /** Updates execution stats based on the instruction. */ 339 void updateExeInstStats(DynInstPtr &inst); 340 341 /** Pointer to main time buffer used for backwards communication. */ 342 TimeBuffer<TimeStruct> *timeBuffer; 343 344 /** Wire to write information heading to previous stages. */ 345 typename TimeBuffer<TimeStruct>::wire toFetch; 346 347 /** Wire to get commit's output from backwards time buffer. */ 348 typename TimeBuffer<TimeStruct>::wire fromCommit; 349 350 /** Wire to write information heading to previous stages. */ 351 typename TimeBuffer<TimeStruct>::wire toRename; 352 353 /** Rename instruction queue interface. */ 354 TimeBuffer<RenameStruct> *renameQueue; 355 356 /** Wire to get rename's output from rename queue. */ 357 typename TimeBuffer<RenameStruct>::wire fromRename; 358 359 /** Issue stage queue. */ 360 TimeBuffer<IssueStruct> issueToExecQueue; 361 362 /** Wire to read information from the issue stage time queue. */ 363 typename TimeBuffer<IssueStruct>::wire fromIssue; 364 365 /** 366 * IEW stage time buffer. Holds ROB indices of instructions that 367 * can be marked as completed. 368 */ 369 TimeBuffer<IEWStruct> *iewQueue; 370 371 /** Wire to write infromation heading to commit. */ 372 typename TimeBuffer<IEWStruct>::wire toCommit; 373 374 /** Queue of all instructions coming from rename this cycle. */ 375 std::queue<DynInstPtr> insts[Impl::MaxThreads]; 376 377 /** Skid buffer between rename and IEW. */ 378 std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads]; 379 380 /** Scoreboard pointer. */ 381 Scoreboard* scoreboard; 382 383 private: 384 /** CPU pointer. */ 385 O3CPU *cpu; 386 387 /** Records if IEW has written to the time buffer this cycle, so that the 388 * CPU can deschedule itself if there is no activity. 389 */ 390 bool wroteToTimeBuffer; 391 392 /** Source of possible stalls. */ 393 struct Stalls { 394 bool commit; 395 }; 396 397 /** Stages that are telling IEW to stall. */ 398 Stalls stalls[Impl::MaxThreads]; 399 400 /** Debug function to print instructions that are issued this cycle. */ 401 void printAvailableInsts(); 402 403 public: 404 /** Instruction queue. */ 405 IQ instQueue; 406 407 /** Load / store queue. */ 408 LSQ ldstQueue; 409 410 /** Pointer to the functional unit pool. */ 411 FUPool *fuPool; 412 /** Records if the LSQ needs to be updated on the next cycle, so that 413 * IEW knows if there will be activity on the next cycle. 414 */ 415 bool updateLSQNextCycle; 416 417 private: 418 /** Records if there is a fetch redirect on this cycle for each thread. */ 419 bool fetchRedirect[Impl::MaxThreads]; 420 421 /** Records if the queues have been changed (inserted or issued insts), 422 * so that IEW knows to broadcast the updated amount of free entries. 423 */ 424 bool updatedQueues; 425 426 /** Commit to IEW delay. */ 427 Cycles commitToIEWDelay; 428 429 /** Rename to IEW delay. */ 430 Cycles renameToIEWDelay; 431 432 /** 433 * Issue to execute delay. What this actually represents is 434 * the amount of time it takes for an instruction to wake up, be 435 * scheduled, and sent to a FU for execution. 436 */ 437 Cycles issueToExecuteDelay; 438 439 /** Width of dispatch, in instructions. */ 440 unsigned dispatchWidth; 441 442 /** Width of issue, in instructions. */ 443 unsigned issueWidth; 444 445 /** Index into queue of instructions being written back. */ 446 unsigned wbNumInst; 447 448 /** Cycle number within the queue of instructions being written back. 449 * Used in case there are too many instructions writing back at the current 450 * cycle and writesbacks need to be scheduled for the future. See comments 451 * in instToCommit(). 452 */ 453 unsigned wbCycle; 454 455 /** Number of instructions in flight that will writeback. */ 456 457 /** Number of instructions in flight that will writeback. */ 458 int wbOutstanding; 459 460 /** Writeback width. */ 461 unsigned wbWidth; 462 463 /** Writeback width * writeback depth, where writeback depth is 464 * the number of cycles of writing back instructions that can be 465 * buffered. */ 466 unsigned wbMax; 467 468 /** Number of active threads. */ 469 ThreadID numThreads; 470 471 /** Pointer to list of active threads. */ 472 std::list<ThreadID> *activeThreads; 473 474 /** Maximum size of the skid buffer. */ 475 unsigned skidBufferMax; 476 477 /** Stat for total number of idle cycles. */ 478 Stats::Scalar iewIdleCycles; 479 /** Stat for total number of squashing cycles. */ 480 Stats::Scalar iewSquashCycles; 481 /** Stat for total number of blocking cycles. */ 482 Stats::Scalar iewBlockCycles; 483 /** Stat for total number of unblocking cycles. */ 484 Stats::Scalar iewUnblockCycles; 485 /** Stat for total number of instructions dispatched. */ 486 Stats::Scalar iewDispatchedInsts; 487 /** Stat for total number of squashed instructions dispatch skips. */ 488 Stats::Scalar iewDispSquashedInsts; 489 /** Stat for total number of dispatched load instructions. */ 490 Stats::Scalar iewDispLoadInsts; 491 /** Stat for total number of dispatched store instructions. */ 492 Stats::Scalar iewDispStoreInsts; 493 /** Stat for total number of dispatched non speculative instructions. */ 494 Stats::Scalar iewDispNonSpecInsts; 495 /** Stat for number of times the IQ becomes full. */ 496 Stats::Scalar iewIQFullEvents; 497 /** Stat for number of times the LSQ becomes full. */ 498 Stats::Scalar iewLSQFullEvents; 499 /** Stat for total number of memory ordering violation events. */ 500 Stats::Scalar memOrderViolationEvents; 501 /** Stat for total number of incorrect predicted taken branches. */ 502 Stats::Scalar predictedTakenIncorrect; 503 /** Stat for total number of incorrect predicted not taken branches. */ 504 Stats::Scalar predictedNotTakenIncorrect; 505 /** Stat for total number of mispredicted branches detected at execute. */ 506 Stats::Formula branchMispredicts; 507 508 /** Stat for total number of executed instructions. */ 509 Stats::Scalar iewExecutedInsts; 510 /** Stat for total number of executed load instructions. */ 511 Stats::Vector iewExecLoadInsts; 512 /** Stat for total number of executed store instructions. */ 513// Stats::Scalar iewExecStoreInsts; 514 /** Stat for total number of squashed instructions skipped at execute. */ 515 Stats::Scalar iewExecSquashedInsts; 516 /** Number of executed software prefetches. */ 517 Stats::Vector iewExecutedSwp; 518 /** Number of executed nops. */ 519 Stats::Vector iewExecutedNop; 520 /** Number of executed meomory references. */ 521 Stats::Vector iewExecutedRefs; 522 /** Number of executed branches. */ 523 Stats::Vector iewExecutedBranches; 524 /** Number of executed store instructions. */ 525 Stats::Formula iewExecStoreInsts; 526 /** Number of instructions executed per cycle. */ 527 Stats::Formula iewExecRate; 528 529 /** Number of instructions sent to commit. */ 530 Stats::Vector iewInstsToCommit; 531 /** Number of instructions that writeback. */ 532 Stats::Vector writebackCount; 533 /** Number of instructions that wake consumers. */ 534 Stats::Vector producerInst; 535 /** Number of instructions that wake up from producers. */ 536 Stats::Vector consumerInst; 537 /** Number of instructions that were delayed in writing back due 538 * to resource contention. 539 */ 540 Stats::Vector wbPenalized; 541 /** Number of instructions per cycle written back. */ 542 Stats::Formula wbRate; 543 /** Average number of woken instructions per writeback. */ 544 Stats::Formula wbFanout; 545 /** Number of instructions per cycle delayed in writing back . */ 546 Stats::Formula wbPenalizedRate; 547}; 548 549#endif // __CPU_O3_IEW_HH__ 550