free_list.hh revision 12105
11689SN/A/*
21689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan
39919Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc.
41689SN/A * All rights reserved.
51689SN/A *
61689SN/A * Redistribution and use in source and binary forms, with or without
71689SN/A * modification, are permitted provided that the following conditions are
81689SN/A * met: redistributions of source code must retain the above copyright
91689SN/A * notice, this list of conditions and the following disclaimer;
101689SN/A * redistributions in binary form must reproduce the above copyright
111689SN/A * notice, this list of conditions and the following disclaimer in the
121689SN/A * documentation and/or other materials provided with the distribution;
131689SN/A * neither the name of the copyright holders nor the names of its
141689SN/A * contributors may be used to endorse or promote products derived from
151689SN/A * this software without specific prior written permission.
161689SN/A *
171689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
181689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
191689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
201689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
211689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
221689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
231689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
241689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
251689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
261689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
271689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
282665Ssaidi@eecs.umich.edu *
292665Ssaidi@eecs.umich.edu * Authors: Kevin Lim
301689SN/A */
311689SN/A
322292SN/A#ifndef __CPU_O3_FREE_LIST_HH__
332292SN/A#define __CPU_O3_FREE_LIST_HH__
341060SN/A
351060SN/A#include <iostream>
361060SN/A#include <queue>
3712105Snathanael.premillieu@arm.com#include <vector>
381060SN/A
392669Sktlim@umich.edu#include "base/misc.hh"
401684SN/A#include "base/trace.hh"
411717SN/A#include "cpu/o3/comm.hh"
429919Ssteve.reinhardt@amd.com#include "cpu/o3/regfile.hh"
438232Snate@binkert.org#include "debug/FreeList.hh"
441060SN/A
451060SN/A/**
469919Ssteve.reinhardt@amd.com * Free list for a single class of registers (e.g., integer
479919Ssteve.reinhardt@amd.com * or floating point).  Because the register class is implicitly
489919Ssteve.reinhardt@amd.com * determined by the rename map instance being accessed, all
499919Ssteve.reinhardt@amd.com * architectural register index parameters and values in this class
509919Ssteve.reinhardt@amd.com * are relative (e.g., %fp2 is just index 2).
519919Ssteve.reinhardt@amd.com */
529919Ssteve.reinhardt@amd.comclass SimpleFreeList
539919Ssteve.reinhardt@amd.com{
549919Ssteve.reinhardt@amd.com  private:
559919Ssteve.reinhardt@amd.com
569919Ssteve.reinhardt@amd.com    /** The actual free list */
5712105Snathanael.premillieu@arm.com    std::queue<PhysRegIdPtr> freeRegs;
589919Ssteve.reinhardt@amd.com
599919Ssteve.reinhardt@amd.com  public:
609919Ssteve.reinhardt@amd.com
619919Ssteve.reinhardt@amd.com    SimpleFreeList() {};
629919Ssteve.reinhardt@amd.com
639919Ssteve.reinhardt@amd.com    /** Add a physical register to the free list */
6412105Snathanael.premillieu@arm.com    void addReg(PhysRegIdPtr reg) { freeRegs.push(reg); }
659919Ssteve.reinhardt@amd.com
669919Ssteve.reinhardt@amd.com    /** Get the next available register from the free list */
6712105Snathanael.premillieu@arm.com    PhysRegIdPtr getReg()
689919Ssteve.reinhardt@amd.com    {
699919Ssteve.reinhardt@amd.com        assert(!freeRegs.empty());
7012105Snathanael.premillieu@arm.com        PhysRegIdPtr free_reg = freeRegs.front();
719919Ssteve.reinhardt@amd.com        freeRegs.pop();
729919Ssteve.reinhardt@amd.com        return free_reg;
739919Ssteve.reinhardt@amd.com    }
749919Ssteve.reinhardt@amd.com
759919Ssteve.reinhardt@amd.com    /** Return the number of free registers on the list. */
769919Ssteve.reinhardt@amd.com    unsigned numFreeRegs() const { return freeRegs.size(); }
779919Ssteve.reinhardt@amd.com
789919Ssteve.reinhardt@amd.com    /** True iff there are free registers on the list. */
799919Ssteve.reinhardt@amd.com    bool hasFreeRegs() const { return !freeRegs.empty(); }
809919Ssteve.reinhardt@amd.com};
819919Ssteve.reinhardt@amd.com
829919Ssteve.reinhardt@amd.com
839919Ssteve.reinhardt@amd.com/**
841060SN/A * FreeList class that simply holds the list of free integer and floating
851060SN/A * point registers.  Can request for a free register of either type, and
861060SN/A * also send back free registers of either type.  This is a very simple
871060SN/A * class, but it should be sufficient for most implementations.  Like all
881060SN/A * other classes, it assumes that the indices for the floating point
891060SN/A * registers starts after the integer registers end.  Hence the variable
901060SN/A * numPhysicalIntRegs is logically equivalent to the baseFP dependency.
912292SN/A * Note that while this most likely should be called FreeList, the name
922292SN/A * "FreeList" is used in a typedef within the CPU Policy, and therefore no
932292SN/A * class can be named simply "FreeList".
941060SN/A * @todo: Give a better name to the base FP dependency.
951060SN/A */
969919Ssteve.reinhardt@amd.comclass UnifiedFreeList
971060SN/A{
981060SN/A  private:
999919Ssteve.reinhardt@amd.com
1009919Ssteve.reinhardt@amd.com    /** The object name, for DPRINTF.  We have to declare this
1019919Ssteve.reinhardt@amd.com     *  explicitly because Scoreboard is not a SimObject. */
1029919Ssteve.reinhardt@amd.com    const std::string _name;
1039919Ssteve.reinhardt@amd.com
1041060SN/A    /** The list of free integer registers. */
1059919Ssteve.reinhardt@amd.com    SimpleFreeList intList;
1061060SN/A
1071060SN/A    /** The list of free floating point registers. */
1089919Ssteve.reinhardt@amd.com    SimpleFreeList floatList;
1091060SN/A
1109920Syasuko.eckert@amd.com    /** The list of free condition-code registers. */
1119920Syasuko.eckert@amd.com    SimpleFreeList ccList;
1129920Syasuko.eckert@amd.com
1139919Ssteve.reinhardt@amd.com    /**
1149919Ssteve.reinhardt@amd.com     * The register file object is used only to distinguish integer
1159919Ssteve.reinhardt@amd.com     * from floating-point physical register indices.
1169919Ssteve.reinhardt@amd.com     */
1179919Ssteve.reinhardt@amd.com    PhysRegFile *regFile;
1181060SN/A
1199919Ssteve.reinhardt@amd.com    /*
1209919Ssteve.reinhardt@amd.com     * We give UnifiedRenameMap internal access so it can get at the
1219919Ssteve.reinhardt@amd.com     * internal per-class free lists and associate those with its
1229919Ssteve.reinhardt@amd.com     * per-class rename maps. See UnifiedRenameMap::init().
1239919Ssteve.reinhardt@amd.com     */
1249919Ssteve.reinhardt@amd.com    friend class UnifiedRenameMap;
1251060SN/A
1261060SN/A  public:
1272292SN/A    /** Constructs a free list.
1282292SN/A     *  @param _numPhysicalIntRegs Number of physical integer registers.
1299919Ssteve.reinhardt@amd.com     *  @param reservedIntRegs Number of integer registers already
1309919Ssteve.reinhardt@amd.com     *                         used by initial mappings.
1312292SN/A     *  @param _numPhysicalFloatRegs Number of physical fp registers.
1329919Ssteve.reinhardt@amd.com     *  @param reservedFloatRegs Number of fp registers already
1339919Ssteve.reinhardt@amd.com     *                           used by initial mappings.
1342292SN/A     */
1359919Ssteve.reinhardt@amd.com    UnifiedFreeList(const std::string &_my_name, PhysRegFile *_regFile);
1361060SN/A
1372292SN/A    /** Gives the name of the freelist. */
1389919Ssteve.reinhardt@amd.com    std::string name() const { return _name; };
1392292SN/A
1409920Syasuko.eckert@amd.com    /** Returns a pointer to the condition-code free list */
1419920Syasuko.eckert@amd.com    SimpleFreeList *getCCList() { return &ccList; }
1429920Syasuko.eckert@amd.com
1432292SN/A    /** Gets a free integer register. */
14412105Snathanael.premillieu@arm.com    PhysRegIdPtr getIntReg() { return intList.getReg(); }
1451060SN/A
1462292SN/A    /** Gets a free fp register. */
14712105Snathanael.premillieu@arm.com    PhysRegIdPtr getFloatReg() { return floatList.getReg(); }
1481060SN/A
1499920Syasuko.eckert@amd.com    /** Gets a free cc register. */
15012105Snathanael.premillieu@arm.com    PhysRegIdPtr getCCReg() { return ccList.getReg(); }
1519920Syasuko.eckert@amd.com
1522292SN/A    /** Adds a register back to the free list. */
15312105Snathanael.premillieu@arm.com    void addReg(PhysRegIdPtr freed_reg);
1541060SN/A
1552292SN/A    /** Adds an integer register back to the free list. */
15612105Snathanael.premillieu@arm.com    void addIntReg(PhysRegIdPtr freed_reg) { intList.addReg(freed_reg); }
1571060SN/A
1582292SN/A    /** Adds a fp register back to the free list. */
15912105Snathanael.premillieu@arm.com    void addFloatReg(PhysRegIdPtr freed_reg) { floatList.addReg(freed_reg); }
1601060SN/A
1619920Syasuko.eckert@amd.com    /** Adds a cc register back to the free list. */
16212105Snathanael.premillieu@arm.com    void addCCReg(PhysRegIdPtr freed_reg) { ccList.addReg(freed_reg); }
1639920Syasuko.eckert@amd.com
1642292SN/A    /** Checks if there are any free integer registers. */
1659919Ssteve.reinhardt@amd.com    bool hasFreeIntRegs() const { return intList.hasFreeRegs(); }
1661060SN/A
1672292SN/A    /** Checks if there are any free fp registers. */
1689919Ssteve.reinhardt@amd.com    bool hasFreeFloatRegs() const { return floatList.hasFreeRegs(); }
1691060SN/A
1709920Syasuko.eckert@amd.com    /** Checks if there are any free cc registers. */
1719920Syasuko.eckert@amd.com    bool hasFreeCCRegs() const { return ccList.hasFreeRegs(); }
1729920Syasuko.eckert@amd.com
1732292SN/A    /** Returns the number of free integer registers. */
1749919Ssteve.reinhardt@amd.com    unsigned numFreeIntRegs() const { return intList.numFreeRegs(); }
1751060SN/A
1762292SN/A    /** Returns the number of free fp registers. */
1779919Ssteve.reinhardt@amd.com    unsigned numFreeFloatRegs() const { return floatList.numFreeRegs(); }
1789920Syasuko.eckert@amd.com
1799920Syasuko.eckert@amd.com    /** Returns the number of free cc registers. */
1809920Syasuko.eckert@amd.com    unsigned numFreeCCRegs() const { return ccList.numFreeRegs(); }
1811060SN/A};
1821060SN/A
1831060SN/Ainline void
18412105Snathanael.premillieu@arm.comUnifiedFreeList::addReg(PhysRegIdPtr freed_reg)
1851060SN/A{
18612105Snathanael.premillieu@arm.com    DPRINTF(FreeList,"Freeing register %i (%s).\n", freed_reg->regIdx,
18712105Snathanael.premillieu@arm.com            RegClassStrings[freed_reg->regClass]);
1881060SN/A    //Might want to add in a check for whether or not this register is
1891060SN/A    //already in there.  A bit vector or something similar would be useful.
19012105Snathanael.premillieu@arm.com    switch (freed_reg->regClass) {
19112105Snathanael.premillieu@arm.com        case IntRegClass:
19212105Snathanael.premillieu@arm.com            intList.addReg(freed_reg);
19312105Snathanael.premillieu@arm.com            break;
19412105Snathanael.premillieu@arm.com        case FloatRegClass:
19512105Snathanael.premillieu@arm.com            floatList.addReg(freed_reg);
19612105Snathanael.premillieu@arm.com            break;
19712105Snathanael.premillieu@arm.com        case CCRegClass:
19812105Snathanael.premillieu@arm.com            ccList.addReg(freed_reg);
19912105Snathanael.premillieu@arm.com            break;
20012105Snathanael.premillieu@arm.com        default:
20112105Snathanael.premillieu@arm.com            panic("Unexpected RegClass (%s)",
20212105Snathanael.premillieu@arm.com                                   RegClassStrings[freed_reg->regClass]);
2031060SN/A    }
2045362Sksewell@umich.edu
2055364Sksewell@umich.edu    // These assert conditions ensure that the number of free
2065364Sksewell@umich.edu    // registers are not more than the # of total Physical  Registers.
2075364Sksewell@umich.edu    // If this were false, it would mean that registers
2085364Sksewell@umich.edu    // have been freed twice, overflowing the free register
2095364Sksewell@umich.edu    // pool and potentially crashing SMT workloads.
2105364Sksewell@umich.edu    // ----
2115364Sksewell@umich.edu    // Comment out for now so as to not potentially break
2125364Sksewell@umich.edu    // CMP and single-threaded workloads
2135364Sksewell@umich.edu    // ----
2145364Sksewell@umich.edu    // assert(freeIntRegs.size() <= numPhysicalIntRegs);
2155364Sksewell@umich.edu    // assert(freeFloatRegs.size() <= numPhysicalFloatRegs);
2161060SN/A}
2171060SN/A
2181060SN/A
2192292SN/A#endif // __CPU_O3_FREE_LIST_HH__
220