fetch_impl.hh revision 9644:07352f119e48
1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 * Korey Sewell 42 */ 43 44#include <algorithm> 45#include <cstring> 46#include <list> 47#include <map> 48#include <queue> 49 50#include "arch/isa_traits.hh" 51#include "arch/tlb.hh" 52#include "arch/utility.hh" 53#include "arch/vtophys.hh" 54#include "base/types.hh" 55#include "config/the_isa.hh" 56#include "cpu/base.hh" 57//#include "cpu/checker/cpu.hh" 58#include "cpu/o3/fetch.hh" 59#include "cpu/exetrace.hh" 60#include "debug/Activity.hh" 61#include "debug/Drain.hh" 62#include "debug/Fetch.hh" 63#include "debug/O3PipeView.hh" 64#include "mem/packet.hh" 65#include "params/DerivO3CPU.hh" 66#include "sim/byteswap.hh" 67#include "sim/core.hh" 68#include "sim/eventq.hh" 69#include "sim/full_system.hh" 70#include "sim/system.hh" 71 72using namespace std; 73 74template<class Impl> 75DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params) 76 : cpu(_cpu), 77 decodeToFetchDelay(params->decodeToFetchDelay), 78 renameToFetchDelay(params->renameToFetchDelay), 79 iewToFetchDelay(params->iewToFetchDelay), 80 commitToFetchDelay(params->commitToFetchDelay), 81 fetchWidth(params->fetchWidth), 82 retryPkt(NULL), 83 retryTid(InvalidThreadID), 84 numThreads(params->numThreads), 85 numFetchingThreads(params->smtNumFetchingThreads), 86 finishTranslationEvent(this) 87{ 88 if (numThreads > Impl::MaxThreads) 89 fatal("numThreads (%d) is larger than compiled limit (%d),\n" 90 "\tincrease MaxThreads in src/cpu/o3/impl.hh\n", 91 numThreads, static_cast<int>(Impl::MaxThreads)); 92 if (fetchWidth > Impl::MaxWidth) 93 fatal("fetchWidth (%d) is larger than compiled limit (%d),\n" 94 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 95 fetchWidth, static_cast<int>(Impl::MaxWidth)); 96 97 std::string policy = params->smtFetchPolicy; 98 99 // Convert string to lowercase 100 std::transform(policy.begin(), policy.end(), policy.begin(), 101 (int(*)(int)) tolower); 102 103 // Figure out fetch policy 104 if (policy == "singlethread") { 105 fetchPolicy = SingleThread; 106 if (numThreads > 1) 107 panic("Invalid Fetch Policy for a SMT workload."); 108 } else if (policy == "roundrobin") { 109 fetchPolicy = RoundRobin; 110 DPRINTF(Fetch, "Fetch policy set to Round Robin\n"); 111 } else if (policy == "branch") { 112 fetchPolicy = Branch; 113 DPRINTF(Fetch, "Fetch policy set to Branch Count\n"); 114 } else if (policy == "iqcount") { 115 fetchPolicy = IQ; 116 DPRINTF(Fetch, "Fetch policy set to IQ count\n"); 117 } else if (policy == "lsqcount") { 118 fetchPolicy = LSQ; 119 DPRINTF(Fetch, "Fetch policy set to LSQ count\n"); 120 } else { 121 fatal("Invalid Fetch Policy. Options Are: {SingleThread," 122 " RoundRobin,LSQcount,IQcount}\n"); 123 } 124 125 // Get the size of an instruction. 126 instSize = sizeof(TheISA::MachInst); 127 128 for (int i = 0; i < Impl::MaxThreads; i++) { 129 cacheData[i] = NULL; 130 decoder[i] = new TheISA::Decoder; 131 } 132 133 branchPred = params->branchPred; 134} 135 136template <class Impl> 137std::string 138DefaultFetch<Impl>::name() const 139{ 140 return cpu->name() + ".fetch"; 141} 142 143template <class Impl> 144void 145DefaultFetch<Impl>::regStats() 146{ 147 icacheStallCycles 148 .name(name() + ".icacheStallCycles") 149 .desc("Number of cycles fetch is stalled on an Icache miss") 150 .prereq(icacheStallCycles); 151 152 fetchedInsts 153 .name(name() + ".Insts") 154 .desc("Number of instructions fetch has processed") 155 .prereq(fetchedInsts); 156 157 fetchedBranches 158 .name(name() + ".Branches") 159 .desc("Number of branches that fetch encountered") 160 .prereq(fetchedBranches); 161 162 predictedBranches 163 .name(name() + ".predictedBranches") 164 .desc("Number of branches that fetch has predicted taken") 165 .prereq(predictedBranches); 166 167 fetchCycles 168 .name(name() + ".Cycles") 169 .desc("Number of cycles fetch has run and was not squashing or" 170 " blocked") 171 .prereq(fetchCycles); 172 173 fetchSquashCycles 174 .name(name() + ".SquashCycles") 175 .desc("Number of cycles fetch has spent squashing") 176 .prereq(fetchSquashCycles); 177 178 fetchTlbCycles 179 .name(name() + ".TlbCycles") 180 .desc("Number of cycles fetch has spent waiting for tlb") 181 .prereq(fetchTlbCycles); 182 183 fetchIdleCycles 184 .name(name() + ".IdleCycles") 185 .desc("Number of cycles fetch was idle") 186 .prereq(fetchIdleCycles); 187 188 fetchBlockedCycles 189 .name(name() + ".BlockedCycles") 190 .desc("Number of cycles fetch has spent blocked") 191 .prereq(fetchBlockedCycles); 192 193 fetchedCacheLines 194 .name(name() + ".CacheLines") 195 .desc("Number of cache lines fetched") 196 .prereq(fetchedCacheLines); 197 198 fetchMiscStallCycles 199 .name(name() + ".MiscStallCycles") 200 .desc("Number of cycles fetch has spent waiting on interrupts, or " 201 "bad addresses, or out of MSHRs") 202 .prereq(fetchMiscStallCycles); 203 204 fetchPendingDrainCycles 205 .name(name() + ".PendingDrainCycles") 206 .desc("Number of cycles fetch has spent waiting on pipes to drain") 207 .prereq(fetchPendingDrainCycles); 208 209 fetchNoActiveThreadStallCycles 210 .name(name() + ".NoActiveThreadStallCycles") 211 .desc("Number of stall cycles due to no active thread to fetch from") 212 .prereq(fetchNoActiveThreadStallCycles); 213 214 fetchPendingTrapStallCycles 215 .name(name() + ".PendingTrapStallCycles") 216 .desc("Number of stall cycles due to pending traps") 217 .prereq(fetchPendingTrapStallCycles); 218 219 fetchPendingQuiesceStallCycles 220 .name(name() + ".PendingQuiesceStallCycles") 221 .desc("Number of stall cycles due to pending quiesce instructions") 222 .prereq(fetchPendingQuiesceStallCycles); 223 224 fetchIcacheWaitRetryStallCycles 225 .name(name() + ".IcacheWaitRetryStallCycles") 226 .desc("Number of stall cycles due to full MSHR") 227 .prereq(fetchIcacheWaitRetryStallCycles); 228 229 fetchIcacheSquashes 230 .name(name() + ".IcacheSquashes") 231 .desc("Number of outstanding Icache misses that were squashed") 232 .prereq(fetchIcacheSquashes); 233 234 fetchTlbSquashes 235 .name(name() + ".ItlbSquashes") 236 .desc("Number of outstanding ITLB misses that were squashed") 237 .prereq(fetchTlbSquashes); 238 239 fetchNisnDist 240 .init(/* base value */ 0, 241 /* last value */ fetchWidth, 242 /* bucket size */ 1) 243 .name(name() + ".rateDist") 244 .desc("Number of instructions fetched each cycle (Total)") 245 .flags(Stats::pdf); 246 247 idleRate 248 .name(name() + ".idleRate") 249 .desc("Percent of cycles fetch was idle") 250 .prereq(idleRate); 251 idleRate = fetchIdleCycles * 100 / cpu->numCycles; 252 253 branchRate 254 .name(name() + ".branchRate") 255 .desc("Number of branch fetches per cycle") 256 .flags(Stats::total); 257 branchRate = fetchedBranches / cpu->numCycles; 258 259 fetchRate 260 .name(name() + ".rate") 261 .desc("Number of inst fetches per cycle") 262 .flags(Stats::total); 263 fetchRate = fetchedInsts / cpu->numCycles; 264} 265 266template<class Impl> 267void 268DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer) 269{ 270 timeBuffer = time_buffer; 271 272 // Create wires to get information from proper places in time buffer. 273 fromDecode = timeBuffer->getWire(-decodeToFetchDelay); 274 fromRename = timeBuffer->getWire(-renameToFetchDelay); 275 fromIEW = timeBuffer->getWire(-iewToFetchDelay); 276 fromCommit = timeBuffer->getWire(-commitToFetchDelay); 277} 278 279template<class Impl> 280void 281DefaultFetch<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr) 282{ 283 activeThreads = at_ptr; 284} 285 286template<class Impl> 287void 288DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 289{ 290 fetchQueue = fq_ptr; 291 292 // Create wire to write information to proper place in fetch queue. 293 toDecode = fetchQueue->getWire(0); 294} 295 296template<class Impl> 297void 298DefaultFetch<Impl>::startupStage() 299{ 300 assert(priorityList.empty()); 301 resetStage(); 302 303 // Fetch needs to start fetching instructions at the very beginning, 304 // so it must start up in active state. 305 switchToActive(); 306} 307 308template<class Impl> 309void 310DefaultFetch<Impl>::resetStage() 311{ 312 numInst = 0; 313 interruptPending = false; 314 cacheBlocked = false; 315 316 priorityList.clear(); 317 318 // Setup PC and nextPC with initial state. 319 for (ThreadID tid = 0; tid < numThreads; tid++) { 320 fetchStatus[tid] = Running; 321 pc[tid] = cpu->pcState(tid); 322 fetchOffset[tid] = 0; 323 macroop[tid] = NULL; 324 325 delayedCommit[tid] = false; 326 memReq[tid] = NULL; 327 328 stalls[tid].decode = false; 329 stalls[tid].rename = false; 330 stalls[tid].iew = false; 331 stalls[tid].commit = false; 332 stalls[tid].drain = false; 333 334 priorityList.push_back(tid); 335 } 336 337 wroteToTimeBuffer = false; 338 _status = Inactive; 339 340 // this CPU could still be unconnected if we are restoring from a 341 // checkpoint and this CPU is to be switched in, thus we can only 342 // do this here if the instruction port is actually connected, if 343 // not we have to do it as part of takeOverFrom. 344 if (cpu->getInstPort().isConnected()) 345 setIcache(); 346} 347 348template<class Impl> 349void 350DefaultFetch<Impl>::setIcache() 351{ 352 assert(cpu->getInstPort().isConnected()); 353 354 // Size of cache block. 355 cacheBlkSize = cpu->getInstPort().peerBlockSize(); 356 357 // Create mask to get rid of offset bits. 358 cacheBlkMask = (cacheBlkSize - 1); 359 360 for (ThreadID tid = 0; tid < numThreads; tid++) { 361 // Create space to store a cache line. 362 if (!cacheData[tid]) 363 cacheData[tid] = new uint8_t[cacheBlkSize]; 364 cacheDataPC[tid] = 0; 365 cacheDataValid[tid] = false; 366 } 367} 368 369template<class Impl> 370void 371DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt) 372{ 373 ThreadID tid = pkt->req->threadId(); 374 375 DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n", tid); 376 assert(!cpu->switchedOut()); 377 378 // Only change the status if it's still waiting on the icache access 379 // to return. 380 if (fetchStatus[tid] != IcacheWaitResponse || 381 pkt->req != memReq[tid]) { 382 ++fetchIcacheSquashes; 383 delete pkt->req; 384 delete pkt; 385 return; 386 } 387 388 memcpy(cacheData[tid], pkt->getPtr<uint8_t>(), cacheBlkSize); 389 cacheDataValid[tid] = true; 390 391 // Wake up the CPU (if it went to sleep and was waiting on 392 // this completion event). 393 cpu->wakeCPU(); 394 395 DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n", 396 tid); 397 398 switchToActive(); 399 400 // Only switch to IcacheAccessComplete if we're not stalled as well. 401 if (checkStall(tid)) { 402 fetchStatus[tid] = Blocked; 403 } else { 404 fetchStatus[tid] = IcacheAccessComplete; 405 } 406 407 // Reset the mem req to NULL. 408 delete pkt->req; 409 delete pkt; 410 memReq[tid] = NULL; 411} 412 413template <class Impl> 414void 415DefaultFetch<Impl>::drainResume() 416{ 417 for (ThreadID i = 0; i < Impl::MaxThreads; ++i) 418 stalls[i].drain = false; 419} 420 421template <class Impl> 422void 423DefaultFetch<Impl>::drainSanityCheck() const 424{ 425 assert(isDrained()); 426 assert(retryPkt == NULL); 427 assert(retryTid == InvalidThreadID); 428 assert(cacheBlocked == false); 429 assert(interruptPending == false); 430 431 for (ThreadID i = 0; i < numThreads; ++i) { 432 assert(!memReq[i]); 433 assert(!stalls[i].decode); 434 assert(!stalls[i].rename); 435 assert(!stalls[i].iew); 436 assert(!stalls[i].commit); 437 assert(fetchStatus[i] == Idle || stalls[i].drain); 438 } 439 440 branchPred->drainSanityCheck(); 441} 442 443template <class Impl> 444bool 445DefaultFetch<Impl>::isDrained() const 446{ 447 /* Make sure that threads are either idle of that the commit stage 448 * has signaled that draining has completed by setting the drain 449 * stall flag. This effectively forces the pipeline to be disabled 450 * until the whole system is drained (simulation may continue to 451 * drain other components). 452 */ 453 for (ThreadID i = 0; i < numThreads; ++i) { 454 if (!(fetchStatus[i] == Idle || 455 (fetchStatus[i] == Blocked && stalls[i].drain))) 456 return false; 457 } 458 459 /* The pipeline might start up again in the middle of the drain 460 * cycle if the finish translation event is scheduled, so make 461 * sure that's not the case. 462 */ 463 return !finishTranslationEvent.scheduled(); 464} 465 466template <class Impl> 467void 468DefaultFetch<Impl>::takeOverFrom() 469{ 470 assert(cpu->getInstPort().isConnected()); 471 resetStage(); 472 473} 474 475template <class Impl> 476void 477DefaultFetch<Impl>::drainStall(ThreadID tid) 478{ 479 assert(cpu->isDraining()); 480 assert(!stalls[tid].drain); 481 DPRINTF(Drain, "%i: Thread drained.\n", tid); 482 stalls[tid].drain = true; 483} 484 485template <class Impl> 486void 487DefaultFetch<Impl>::wakeFromQuiesce() 488{ 489 DPRINTF(Fetch, "Waking up from quiesce\n"); 490 // Hopefully this is safe 491 // @todo: Allow other threads to wake from quiesce. 492 fetchStatus[0] = Running; 493} 494 495template <class Impl> 496inline void 497DefaultFetch<Impl>::switchToActive() 498{ 499 if (_status == Inactive) { 500 DPRINTF(Activity, "Activating stage.\n"); 501 502 cpu->activateStage(O3CPU::FetchIdx); 503 504 _status = Active; 505 } 506} 507 508template <class Impl> 509inline void 510DefaultFetch<Impl>::switchToInactive() 511{ 512 if (_status == Active) { 513 DPRINTF(Activity, "Deactivating stage.\n"); 514 515 cpu->deactivateStage(O3CPU::FetchIdx); 516 517 _status = Inactive; 518 } 519} 520 521template <class Impl> 522bool 523DefaultFetch<Impl>::lookupAndUpdateNextPC( 524 DynInstPtr &inst, TheISA::PCState &nextPC) 525{ 526 // Do branch prediction check here. 527 // A bit of a misnomer...next_PC is actually the current PC until 528 // this function updates it. 529 bool predict_taken; 530 531 if (!inst->isControl()) { 532 TheISA::advancePC(nextPC, inst->staticInst); 533 inst->setPredTarg(nextPC); 534 inst->setPredTaken(false); 535 return false; 536 } 537 538 ThreadID tid = inst->threadNumber; 539 predict_taken = branchPred->predict(inst->staticInst, inst->seqNum, 540 nextPC, tid); 541 542 if (predict_taken) { 543 DPRINTF(Fetch, "[tid:%i]: [sn:%i]: Branch predicted to be taken to %s.\n", 544 tid, inst->seqNum, nextPC); 545 } else { 546 DPRINTF(Fetch, "[tid:%i]: [sn:%i]:Branch predicted to be not taken.\n", 547 tid, inst->seqNum); 548 } 549 550 DPRINTF(Fetch, "[tid:%i]: [sn:%i] Branch predicted to go to %s.\n", 551 tid, inst->seqNum, nextPC); 552 inst->setPredTarg(nextPC); 553 inst->setPredTaken(predict_taken); 554 555 ++fetchedBranches; 556 557 if (predict_taken) { 558 ++predictedBranches; 559 } 560 561 return predict_taken; 562} 563 564template <class Impl> 565bool 566DefaultFetch<Impl>::fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc) 567{ 568 Fault fault = NoFault; 569 570 assert(!cpu->switchedOut()); 571 572 // @todo: not sure if these should block translation. 573 //AlphaDep 574 if (cacheBlocked) { 575 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n", 576 tid); 577 return false; 578 } else if (checkInterrupt(pc) && !delayedCommit[tid]) { 579 // Hold off fetch from getting new instructions when: 580 // Cache is blocked, or 581 // while an interrupt is pending and we're not in PAL mode, or 582 // fetch is switched out. 583 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n", 584 tid); 585 return false; 586 } 587 588 // Align the fetch address so it's at the start of a cache block. 589 Addr block_PC = icacheBlockAlignPC(vaddr); 590 591 DPRINTF(Fetch, "[tid:%i] Fetching cache line %#x for addr %#x\n", 592 tid, block_PC, vaddr); 593 594 // Setup the memReq to do a read of the first instruction's address. 595 // Set the appropriate read size and flags as well. 596 // Build request here. 597 RequestPtr mem_req = 598 new Request(tid, block_PC, cacheBlkSize, Request::INST_FETCH, 599 cpu->instMasterId(), pc, cpu->thread[tid]->contextId(), tid); 600 601 memReq[tid] = mem_req; 602 603 // Initiate translation of the icache block 604 fetchStatus[tid] = ItlbWait; 605 FetchTranslation *trans = new FetchTranslation(this); 606 cpu->itb->translateTiming(mem_req, cpu->thread[tid]->getTC(), 607 trans, BaseTLB::Execute); 608 return true; 609} 610 611template <class Impl> 612void 613DefaultFetch<Impl>::finishTranslation(Fault fault, RequestPtr mem_req) 614{ 615 ThreadID tid = mem_req->threadId(); 616 Addr block_PC = mem_req->getVaddr(); 617 618 assert(!cpu->switchedOut()); 619 620 // Wake up CPU if it was idle 621 cpu->wakeCPU(); 622 623 if (fetchStatus[tid] != ItlbWait || mem_req != memReq[tid] || 624 mem_req->getVaddr() != memReq[tid]->getVaddr()) { 625 DPRINTF(Fetch, "[tid:%i] Ignoring itlb completed after squash\n", 626 tid); 627 ++fetchTlbSquashes; 628 delete mem_req; 629 return; 630 } 631 632 633 // If translation was successful, attempt to read the icache block. 634 if (fault == NoFault) { 635 // Check that we're not going off into random memory 636 // If we have, just wait around for commit to squash something and put 637 // us on the right track 638 if (!cpu->system->isMemAddr(mem_req->getPaddr())) { 639 warn("Address %#x is outside of physical memory, stopping fetch\n", 640 mem_req->getPaddr()); 641 fetchStatus[tid] = NoGoodAddr; 642 delete mem_req; 643 memReq[tid] = NULL; 644 return; 645 } 646 647 // Build packet here. 648 PacketPtr data_pkt = new Packet(mem_req, MemCmd::ReadReq); 649 data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]); 650 651 cacheDataPC[tid] = block_PC; 652 cacheDataValid[tid] = false; 653 DPRINTF(Fetch, "Fetch: Doing instruction read.\n"); 654 655 fetchedCacheLines++; 656 657 // Access the cache. 658 if (!cpu->getInstPort().sendTimingReq(data_pkt)) { 659 assert(retryPkt == NULL); 660 assert(retryTid == InvalidThreadID); 661 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid); 662 663 fetchStatus[tid] = IcacheWaitRetry; 664 retryPkt = data_pkt; 665 retryTid = tid; 666 cacheBlocked = true; 667 } else { 668 DPRINTF(Fetch, "[tid:%i]: Doing Icache access.\n", tid); 669 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache " 670 "response.\n", tid); 671 672 lastIcacheStall[tid] = curTick(); 673 fetchStatus[tid] = IcacheWaitResponse; 674 } 675 } else { 676 if (!(numInst < fetchWidth)) { 677 assert(!finishTranslationEvent.scheduled()); 678 finishTranslationEvent.setFault(fault); 679 finishTranslationEvent.setReq(mem_req); 680 cpu->schedule(finishTranslationEvent, 681 cpu->clockEdge(Cycles(1))); 682 return; 683 } 684 DPRINTF(Fetch, "[tid:%i] Got back req with addr %#x but expected %#x\n", 685 tid, mem_req->getVaddr(), memReq[tid]->getVaddr()); 686 // Translation faulted, icache request won't be sent. 687 delete mem_req; 688 memReq[tid] = NULL; 689 690 // Send the fault to commit. This thread will not do anything 691 // until commit handles the fault. The only other way it can 692 // wake up is if a squash comes along and changes the PC. 693 TheISA::PCState fetchPC = pc[tid]; 694 695 DPRINTF(Fetch, "[tid:%i]: Translation faulted, building noop.\n", tid); 696 // We will use a nop in ordier to carry the fault. 697 DynInstPtr instruction = buildInst(tid, 698 decoder[tid]->decode(TheISA::NoopMachInst, fetchPC.instAddr()), 699 NULL, fetchPC, fetchPC, false); 700 701 instruction->setPredTarg(fetchPC); 702 instruction->fault = fault; 703 wroteToTimeBuffer = true; 704 705 DPRINTF(Activity, "Activity this cycle.\n"); 706 cpu->activityThisCycle(); 707 708 fetchStatus[tid] = TrapPending; 709 710 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n", tid); 711 DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %s.\n", 712 tid, fault->name(), pc[tid]); 713 } 714 _status = updateFetchStatus(); 715} 716 717template <class Impl> 718inline void 719DefaultFetch<Impl>::doSquash(const TheISA::PCState &newPC, 720 const DynInstPtr squashInst, ThreadID tid) 721{ 722 DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %s.\n", 723 tid, newPC); 724 725 pc[tid] = newPC; 726 fetchOffset[tid] = 0; 727 if (squashInst && squashInst->pcState().instAddr() == newPC.instAddr()) 728 macroop[tid] = squashInst->macroop; 729 else 730 macroop[tid] = NULL; 731 decoder[tid]->reset(); 732 733 // Clear the icache miss if it's outstanding. 734 if (fetchStatus[tid] == IcacheWaitResponse) { 735 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n", 736 tid); 737 memReq[tid] = NULL; 738 } else if (fetchStatus[tid] == ItlbWait) { 739 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding ITLB miss.\n", 740 tid); 741 memReq[tid] = NULL; 742 } 743 744 // Get rid of the retrying packet if it was from this thread. 745 if (retryTid == tid) { 746 assert(cacheBlocked); 747 if (retryPkt) { 748 delete retryPkt->req; 749 delete retryPkt; 750 } 751 retryPkt = NULL; 752 retryTid = InvalidThreadID; 753 } 754 755 fetchStatus[tid] = Squashing; 756 757 // microops are being squashed, it is not known wheather the 758 // youngest non-squashed microop was marked delayed commit 759 // or not. Setting the flag to true ensures that the 760 // interrupts are not handled when they cannot be, though 761 // some opportunities to handle interrupts may be missed. 762 delayedCommit[tid] = true; 763 764 ++fetchSquashCycles; 765} 766 767template<class Impl> 768void 769DefaultFetch<Impl>::squashFromDecode(const TheISA::PCState &newPC, 770 const DynInstPtr squashInst, 771 const InstSeqNum seq_num, ThreadID tid) 772{ 773 DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n", tid); 774 775 doSquash(newPC, squashInst, tid); 776 777 // Tell the CPU to remove any instructions that are in flight between 778 // fetch and decode. 779 cpu->removeInstsUntil(seq_num, tid); 780} 781 782template<class Impl> 783bool 784DefaultFetch<Impl>::checkStall(ThreadID tid) const 785{ 786 bool ret_val = false; 787 788 if (cpu->contextSwitch) { 789 DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid); 790 ret_val = true; 791 } else if (stalls[tid].drain) { 792 assert(cpu->isDraining()); 793 DPRINTF(Fetch,"[tid:%i]: Drain stall detected.\n",tid); 794 ret_val = true; 795 } else if (stalls[tid].decode) { 796 DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid); 797 ret_val = true; 798 } else if (stalls[tid].rename) { 799 DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid); 800 ret_val = true; 801 } else if (stalls[tid].iew) { 802 DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid); 803 ret_val = true; 804 } else if (stalls[tid].commit) { 805 DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid); 806 ret_val = true; 807 } 808 809 return ret_val; 810} 811 812template<class Impl> 813typename DefaultFetch<Impl>::FetchStatus 814DefaultFetch<Impl>::updateFetchStatus() 815{ 816 //Check Running 817 list<ThreadID>::iterator threads = activeThreads->begin(); 818 list<ThreadID>::iterator end = activeThreads->end(); 819 820 while (threads != end) { 821 ThreadID tid = *threads++; 822 823 if (fetchStatus[tid] == Running || 824 fetchStatus[tid] == Squashing || 825 fetchStatus[tid] == IcacheAccessComplete) { 826 827 if (_status == Inactive) { 828 DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid); 829 830 if (fetchStatus[tid] == IcacheAccessComplete) { 831 DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache" 832 "completion\n",tid); 833 } 834 835 cpu->activateStage(O3CPU::FetchIdx); 836 } 837 838 return Active; 839 } 840 } 841 842 // Stage is switching from active to inactive, notify CPU of it. 843 if (_status == Active) { 844 DPRINTF(Activity, "Deactivating stage.\n"); 845 846 cpu->deactivateStage(O3CPU::FetchIdx); 847 } 848 849 return Inactive; 850} 851 852template <class Impl> 853void 854DefaultFetch<Impl>::squash(const TheISA::PCState &newPC, 855 const InstSeqNum seq_num, DynInstPtr squashInst, 856 ThreadID tid) 857{ 858 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n", tid); 859 860 doSquash(newPC, squashInst, tid); 861 862 // Tell the CPU to remove any instructions that are not in the ROB. 863 cpu->removeInstsNotInROB(tid); 864} 865 866template <class Impl> 867void 868DefaultFetch<Impl>::tick() 869{ 870 list<ThreadID>::iterator threads = activeThreads->begin(); 871 list<ThreadID>::iterator end = activeThreads->end(); 872 bool status_change = false; 873 874 wroteToTimeBuffer = false; 875 876 for (ThreadID i = 0; i < Impl::MaxThreads; ++i) { 877 issuePipelinedIfetch[i] = false; 878 } 879 880 while (threads != end) { 881 ThreadID tid = *threads++; 882 883 // Check the signals for each thread to determine the proper status 884 // for each thread. 885 bool updated_status = checkSignalsAndUpdate(tid); 886 status_change = status_change || updated_status; 887 } 888 889 DPRINTF(Fetch, "Running stage.\n"); 890 891 if (FullSystem) { 892 if (fromCommit->commitInfo[0].interruptPending) { 893 interruptPending = true; 894 } 895 896 if (fromCommit->commitInfo[0].clearInterrupt) { 897 interruptPending = false; 898 } 899 } 900 901 for (threadFetched = 0; threadFetched < numFetchingThreads; 902 threadFetched++) { 903 // Fetch each of the actively fetching threads. 904 fetch(status_change); 905 } 906 907 // Record number of instructions fetched this cycle for distribution. 908 fetchNisnDist.sample(numInst); 909 910 if (status_change) { 911 // Change the fetch stage status if there was a status change. 912 _status = updateFetchStatus(); 913 } 914 915 // If there was activity this cycle, inform the CPU of it. 916 if (wroteToTimeBuffer || cpu->contextSwitch) { 917 DPRINTF(Activity, "Activity this cycle.\n"); 918 919 cpu->activityThisCycle(); 920 } 921 922 // Issue the next I-cache request if possible. 923 for (ThreadID i = 0; i < Impl::MaxThreads; ++i) { 924 if (issuePipelinedIfetch[i]) { 925 pipelineIcacheAccesses(i); 926 } 927 } 928 929 // Reset the number of the instruction we've fetched. 930 numInst = 0; 931} 932 933template <class Impl> 934bool 935DefaultFetch<Impl>::checkSignalsAndUpdate(ThreadID tid) 936{ 937 // Update the per thread stall statuses. 938 if (fromDecode->decodeBlock[tid]) { 939 stalls[tid].decode = true; 940 } 941 942 if (fromDecode->decodeUnblock[tid]) { 943 assert(stalls[tid].decode); 944 assert(!fromDecode->decodeBlock[tid]); 945 stalls[tid].decode = false; 946 } 947 948 if (fromRename->renameBlock[tid]) { 949 stalls[tid].rename = true; 950 } 951 952 if (fromRename->renameUnblock[tid]) { 953 assert(stalls[tid].rename); 954 assert(!fromRename->renameBlock[tid]); 955 stalls[tid].rename = false; 956 } 957 958 if (fromIEW->iewBlock[tid]) { 959 stalls[tid].iew = true; 960 } 961 962 if (fromIEW->iewUnblock[tid]) { 963 assert(stalls[tid].iew); 964 assert(!fromIEW->iewBlock[tid]); 965 stalls[tid].iew = false; 966 } 967 968 if (fromCommit->commitBlock[tid]) { 969 stalls[tid].commit = true; 970 } 971 972 if (fromCommit->commitUnblock[tid]) { 973 assert(stalls[tid].commit); 974 assert(!fromCommit->commitBlock[tid]); 975 stalls[tid].commit = false; 976 } 977 978 // Check squash signals from commit. 979 if (fromCommit->commitInfo[tid].squash) { 980 981 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash " 982 "from commit.\n",tid); 983 // In any case, squash. 984 squash(fromCommit->commitInfo[tid].pc, 985 fromCommit->commitInfo[tid].doneSeqNum, 986 fromCommit->commitInfo[tid].squashInst, tid); 987 988 // If it was a branch mispredict on a control instruction, update the 989 // branch predictor with that instruction, otherwise just kill the 990 // invalid state we generated in after sequence number 991 if (fromCommit->commitInfo[tid].mispredictInst && 992 fromCommit->commitInfo[tid].mispredictInst->isControl()) { 993 branchPred->squash(fromCommit->commitInfo[tid].doneSeqNum, 994 fromCommit->commitInfo[tid].pc, 995 fromCommit->commitInfo[tid].branchTaken, 996 tid); 997 } else { 998 branchPred->squash(fromCommit->commitInfo[tid].doneSeqNum, 999 tid); 1000 } 1001 1002 return true; 1003 } else if (fromCommit->commitInfo[tid].doneSeqNum) { 1004 // Update the branch predictor if it wasn't a squashed instruction 1005 // that was broadcasted. 1006 branchPred->update(fromCommit->commitInfo[tid].doneSeqNum, tid); 1007 } 1008 1009 // Check ROB squash signals from commit. 1010 if (fromCommit->commitInfo[tid].robSquashing) { 1011 DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid); 1012 1013 // Continue to squash. 1014 fetchStatus[tid] = Squashing; 1015 1016 return true; 1017 } 1018 1019 // Check squash signals from decode. 1020 if (fromDecode->decodeInfo[tid].squash) { 1021 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash " 1022 "from decode.\n",tid); 1023 1024 // Update the branch predictor. 1025 if (fromDecode->decodeInfo[tid].branchMispredict) { 1026 branchPred->squash(fromDecode->decodeInfo[tid].doneSeqNum, 1027 fromDecode->decodeInfo[tid].nextPC, 1028 fromDecode->decodeInfo[tid].branchTaken, 1029 tid); 1030 } else { 1031 branchPred->squash(fromDecode->decodeInfo[tid].doneSeqNum, 1032 tid); 1033 } 1034 1035 if (fetchStatus[tid] != Squashing) { 1036 1037 DPRINTF(Fetch, "Squashing from decode with PC = %s\n", 1038 fromDecode->decodeInfo[tid].nextPC); 1039 // Squash unless we're already squashing 1040 squashFromDecode(fromDecode->decodeInfo[tid].nextPC, 1041 fromDecode->decodeInfo[tid].squashInst, 1042 fromDecode->decodeInfo[tid].doneSeqNum, 1043 tid); 1044 1045 return true; 1046 } 1047 } 1048 1049 if (checkStall(tid) && 1050 fetchStatus[tid] != IcacheWaitResponse && 1051 fetchStatus[tid] != IcacheWaitRetry && 1052 fetchStatus[tid] != ItlbWait && 1053 fetchStatus[tid] != QuiescePending) { 1054 DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid); 1055 1056 fetchStatus[tid] = Blocked; 1057 1058 return true; 1059 } 1060 1061 if (fetchStatus[tid] == Blocked || 1062 fetchStatus[tid] == Squashing) { 1063 // Switch status to running if fetch isn't being told to block or 1064 // squash this cycle. 1065 DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n", 1066 tid); 1067 1068 fetchStatus[tid] = Running; 1069 1070 return true; 1071 } 1072 1073 // If we've reached this point, we have not gotten any signals that 1074 // cause fetch to change its status. Fetch remains the same as before. 1075 return false; 1076} 1077 1078template<class Impl> 1079typename Impl::DynInstPtr 1080DefaultFetch<Impl>::buildInst(ThreadID tid, StaticInstPtr staticInst, 1081 StaticInstPtr curMacroop, TheISA::PCState thisPC, 1082 TheISA::PCState nextPC, bool trace) 1083{ 1084 // Get a sequence number. 1085 InstSeqNum seq = cpu->getAndIncrementInstSeq(); 1086 1087 // Create a new DynInst from the instruction fetched. 1088 DynInstPtr instruction = 1089 new DynInst(staticInst, curMacroop, thisPC, nextPC, seq, cpu); 1090 instruction->setTid(tid); 1091 1092 instruction->setASID(tid); 1093 1094 instruction->setThreadState(cpu->thread[tid]); 1095 1096 DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x (%d) created " 1097 "[sn:%lli].\n", tid, thisPC.instAddr(), 1098 thisPC.microPC(), seq); 1099 1100 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", tid, 1101 instruction->staticInst-> 1102 disassemble(thisPC.instAddr())); 1103 1104#if TRACING_ON 1105 if (trace) { 1106 instruction->traceData = 1107 cpu->getTracer()->getInstRecord(curTick(), cpu->tcBase(tid), 1108 instruction->staticInst, thisPC, curMacroop); 1109 } 1110#else 1111 instruction->traceData = NULL; 1112#endif 1113 1114 // Add instruction to the CPU's list of instructions. 1115 instruction->setInstListIt(cpu->addInst(instruction)); 1116 1117 // Write the instruction to the first slot in the queue 1118 // that heads to decode. 1119 assert(numInst < fetchWidth); 1120 toDecode->insts[toDecode->size++] = instruction; 1121 1122 // Keep track of if we can take an interrupt at this boundary 1123 delayedCommit[tid] = instruction->isDelayedCommit(); 1124 1125 return instruction; 1126} 1127 1128template<class Impl> 1129void 1130DefaultFetch<Impl>::fetch(bool &status_change) 1131{ 1132 ////////////////////////////////////////// 1133 // Start actual fetch 1134 ////////////////////////////////////////// 1135 ThreadID tid = getFetchingThread(fetchPolicy); 1136 1137 assert(!cpu->switchedOut()); 1138 1139 if (tid == InvalidThreadID) { 1140 // Breaks looping condition in tick() 1141 threadFetched = numFetchingThreads; 1142 1143 if (numThreads == 1) { // @todo Per-thread stats 1144 profileStall(0); 1145 } 1146 1147 return; 1148 } 1149 1150 DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid); 1151 1152 // The current PC. 1153 TheISA::PCState thisPC = pc[tid]; 1154 1155 Addr pcOffset = fetchOffset[tid]; 1156 Addr fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask; 1157 1158 bool inRom = isRomMicroPC(thisPC.microPC()); 1159 1160 // If returning from the delay of a cache miss, then update the status 1161 // to running, otherwise do the cache access. Possibly move this up 1162 // to tick() function. 1163 if (fetchStatus[tid] == IcacheAccessComplete) { 1164 DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n", tid); 1165 1166 fetchStatus[tid] = Running; 1167 status_change = true; 1168 } else if (fetchStatus[tid] == Running) { 1169 // Align the fetch PC so its at the start of a cache block. 1170 Addr block_PC = icacheBlockAlignPC(fetchAddr); 1171 1172 // If buffer is no longer valid or fetchAddr has moved to point 1173 // to the next cache block, AND we have no remaining ucode 1174 // from a macro-op, then start fetch from icache. 1175 if (!(cacheDataValid[tid] && block_PC == cacheDataPC[tid]) 1176 && !inRom && !macroop[tid]) { 1177 DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read " 1178 "instruction, starting at PC %s.\n", tid, thisPC); 1179 1180 fetchCacheLine(fetchAddr, tid, thisPC.instAddr()); 1181 1182 if (fetchStatus[tid] == IcacheWaitResponse) 1183 ++icacheStallCycles; 1184 else if (fetchStatus[tid] == ItlbWait) 1185 ++fetchTlbCycles; 1186 else 1187 ++fetchMiscStallCycles; 1188 return; 1189 } else if ((checkInterrupt(thisPC.instAddr()) && !delayedCommit[tid])) { 1190 // Stall CPU if an interrupt is posted and we're not issuing 1191 // an delayed commit micro-op currently (delayed commit instructions 1192 // are not interruptable by interrupts, only faults) 1193 ++fetchMiscStallCycles; 1194 DPRINTF(Fetch, "[tid:%i]: Fetch is stalled!\n", tid); 1195 return; 1196 } 1197 } else { 1198 if (fetchStatus[tid] == Idle) { 1199 ++fetchIdleCycles; 1200 DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid); 1201 } 1202 1203 // Status is Idle, so fetch should do nothing. 1204 return; 1205 } 1206 1207 ++fetchCycles; 1208 1209 TheISA::PCState nextPC = thisPC; 1210 1211 StaticInstPtr staticInst = NULL; 1212 StaticInstPtr curMacroop = macroop[tid]; 1213 1214 // If the read of the first instruction was successful, then grab the 1215 // instructions from the rest of the cache line and put them into the 1216 // queue heading to decode. 1217 1218 DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to " 1219 "decode.\n", tid); 1220 1221 // Need to keep track of whether or not a predicted branch 1222 // ended this fetch block. 1223 bool predictedBranch = false; 1224 1225 TheISA::MachInst *cacheInsts = 1226 reinterpret_cast<TheISA::MachInst *>(cacheData[tid]); 1227 1228 const unsigned numInsts = cacheBlkSize / instSize; 1229 unsigned blkOffset = (fetchAddr - cacheDataPC[tid]) / instSize; 1230 1231 // Loop through instruction memory from the cache. 1232 // Keep issuing while fetchWidth is available and branch is not 1233 // predicted taken 1234 while (numInst < fetchWidth && !predictedBranch) { 1235 1236 // We need to process more memory if we aren't going to get a 1237 // StaticInst from the rom, the current macroop, or what's already 1238 // in the decoder. 1239 bool needMem = !inRom && !curMacroop && 1240 !decoder[tid]->instReady(); 1241 fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask; 1242 Addr block_PC = icacheBlockAlignPC(fetchAddr); 1243 1244 if (needMem) { 1245 // If buffer is no longer valid or fetchAddr has moved to point 1246 // to the next cache block then start fetch from icache. 1247 if (!cacheDataValid[tid] || block_PC != cacheDataPC[tid]) 1248 break; 1249 1250 if (blkOffset >= numInsts) { 1251 // We need to process more memory, but we've run out of the 1252 // current block. 1253 break; 1254 } 1255 1256 if (ISA_HAS_DELAY_SLOT && pcOffset == 0) { 1257 // Walk past any annulled delay slot instructions. 1258 Addr pcAddr = thisPC.instAddr() & BaseCPU::PCMask; 1259 while (fetchAddr != pcAddr && blkOffset < numInsts) { 1260 blkOffset++; 1261 fetchAddr += instSize; 1262 } 1263 if (blkOffset >= numInsts) 1264 break; 1265 } 1266 1267 MachInst inst = TheISA::gtoh(cacheInsts[blkOffset]); 1268 decoder[tid]->moreBytes(thisPC, fetchAddr, inst); 1269 1270 if (decoder[tid]->needMoreBytes()) { 1271 blkOffset++; 1272 fetchAddr += instSize; 1273 pcOffset += instSize; 1274 } 1275 } 1276 1277 // Extract as many instructions and/or microops as we can from 1278 // the memory we've processed so far. 1279 do { 1280 if (!(curMacroop || inRom)) { 1281 if (decoder[tid]->instReady()) { 1282 staticInst = decoder[tid]->decode(thisPC); 1283 1284 // Increment stat of fetched instructions. 1285 ++fetchedInsts; 1286 1287 if (staticInst->isMacroop()) { 1288 curMacroop = staticInst; 1289 } else { 1290 pcOffset = 0; 1291 } 1292 } else { 1293 // We need more bytes for this instruction so blkOffset and 1294 // pcOffset will be updated 1295 break; 1296 } 1297 } 1298 // Whether we're moving to a new macroop because we're at the 1299 // end of the current one, or the branch predictor incorrectly 1300 // thinks we are... 1301 bool newMacro = false; 1302 if (curMacroop || inRom) { 1303 if (inRom) { 1304 staticInst = cpu->microcodeRom.fetchMicroop( 1305 thisPC.microPC(), curMacroop); 1306 } else { 1307 staticInst = curMacroop->fetchMicroop(thisPC.microPC()); 1308 } 1309 newMacro |= staticInst->isLastMicroop(); 1310 } 1311 1312 DynInstPtr instruction = 1313 buildInst(tid, staticInst, curMacroop, 1314 thisPC, nextPC, true); 1315 1316 numInst++; 1317 1318#if TRACING_ON 1319 if (DTRACE(O3PipeView)) { 1320 instruction->fetchTick = curTick(); 1321 } 1322#endif 1323 1324 nextPC = thisPC; 1325 1326 // If we're branching after this instruction, quite fetching 1327 // from the same block then. 1328 predictedBranch |= thisPC.branching(); 1329 predictedBranch |= 1330 lookupAndUpdateNextPC(instruction, nextPC); 1331 if (predictedBranch) { 1332 DPRINTF(Fetch, "Branch detected with PC = %s\n", thisPC); 1333 } 1334 1335 newMacro |= thisPC.instAddr() != nextPC.instAddr(); 1336 1337 // Move to the next instruction, unless we have a branch. 1338 thisPC = nextPC; 1339 inRom = isRomMicroPC(thisPC.microPC()); 1340 1341 if (newMacro) { 1342 fetchAddr = thisPC.instAddr() & BaseCPU::PCMask; 1343 blkOffset = (fetchAddr - cacheDataPC[tid]) / instSize; 1344 pcOffset = 0; 1345 curMacroop = NULL; 1346 } 1347 1348 if (instruction->isQuiesce()) { 1349 DPRINTF(Fetch, 1350 "Quiesce instruction encountered, halting fetch!"); 1351 fetchStatus[tid] = QuiescePending; 1352 status_change = true; 1353 break; 1354 } 1355 } while ((curMacroop || decoder[tid]->instReady()) && 1356 numInst < fetchWidth); 1357 } 1358 1359 if (predictedBranch) { 1360 DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch " 1361 "instruction encountered.\n", tid); 1362 } else if (numInst >= fetchWidth) { 1363 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth " 1364 "for this cycle.\n", tid); 1365 } else if (blkOffset >= cacheBlkSize) { 1366 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache " 1367 "block.\n", tid); 1368 } 1369 1370 macroop[tid] = curMacroop; 1371 fetchOffset[tid] = pcOffset; 1372 1373 if (numInst > 0) { 1374 wroteToTimeBuffer = true; 1375 } 1376 1377 pc[tid] = thisPC; 1378 1379 // pipeline a fetch if we're crossing a cache boundary and not in 1380 // a state that would preclude fetching 1381 fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask; 1382 Addr block_PC = icacheBlockAlignPC(fetchAddr); 1383 issuePipelinedIfetch[tid] = block_PC != cacheDataPC[tid] && 1384 fetchStatus[tid] != IcacheWaitResponse && 1385 fetchStatus[tid] != ItlbWait && 1386 fetchStatus[tid] != IcacheWaitRetry && 1387 fetchStatus[tid] != QuiescePending && 1388 !curMacroop; 1389} 1390 1391template<class Impl> 1392void 1393DefaultFetch<Impl>::recvRetry() 1394{ 1395 if (retryPkt != NULL) { 1396 assert(cacheBlocked); 1397 assert(retryTid != InvalidThreadID); 1398 assert(fetchStatus[retryTid] == IcacheWaitRetry); 1399 1400 if (cpu->getInstPort().sendTimingReq(retryPkt)) { 1401 fetchStatus[retryTid] = IcacheWaitResponse; 1402 retryPkt = NULL; 1403 retryTid = InvalidThreadID; 1404 cacheBlocked = false; 1405 } 1406 } else { 1407 assert(retryTid == InvalidThreadID); 1408 // Access has been squashed since it was sent out. Just clear 1409 // the cache being blocked. 1410 cacheBlocked = false; 1411 } 1412} 1413 1414/////////////////////////////////////// 1415// // 1416// SMT FETCH POLICY MAINTAINED HERE // 1417// // 1418/////////////////////////////////////// 1419template<class Impl> 1420ThreadID 1421DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority) 1422{ 1423 if (numThreads > 1) { 1424 switch (fetch_priority) { 1425 1426 case SingleThread: 1427 return 0; 1428 1429 case RoundRobin: 1430 return roundRobin(); 1431 1432 case IQ: 1433 return iqCount(); 1434 1435 case LSQ: 1436 return lsqCount(); 1437 1438 case Branch: 1439 return branchCount(); 1440 1441 default: 1442 return InvalidThreadID; 1443 } 1444 } else { 1445 list<ThreadID>::iterator thread = activeThreads->begin(); 1446 if (thread == activeThreads->end()) { 1447 return InvalidThreadID; 1448 } 1449 1450 ThreadID tid = *thread; 1451 1452 if (fetchStatus[tid] == Running || 1453 fetchStatus[tid] == IcacheAccessComplete || 1454 fetchStatus[tid] == Idle) { 1455 return tid; 1456 } else { 1457 return InvalidThreadID; 1458 } 1459 } 1460} 1461 1462 1463template<class Impl> 1464ThreadID 1465DefaultFetch<Impl>::roundRobin() 1466{ 1467 list<ThreadID>::iterator pri_iter = priorityList.begin(); 1468 list<ThreadID>::iterator end = priorityList.end(); 1469 1470 ThreadID high_pri; 1471 1472 while (pri_iter != end) { 1473 high_pri = *pri_iter; 1474 1475 assert(high_pri <= numThreads); 1476 1477 if (fetchStatus[high_pri] == Running || 1478 fetchStatus[high_pri] == IcacheAccessComplete || 1479 fetchStatus[high_pri] == Idle) { 1480 1481 priorityList.erase(pri_iter); 1482 priorityList.push_back(high_pri); 1483 1484 return high_pri; 1485 } 1486 1487 pri_iter++; 1488 } 1489 1490 return InvalidThreadID; 1491} 1492 1493template<class Impl> 1494ThreadID 1495DefaultFetch<Impl>::iqCount() 1496{ 1497 std::priority_queue<unsigned> PQ; 1498 std::map<unsigned, ThreadID> threadMap; 1499 1500 list<ThreadID>::iterator threads = activeThreads->begin(); 1501 list<ThreadID>::iterator end = activeThreads->end(); 1502 1503 while (threads != end) { 1504 ThreadID tid = *threads++; 1505 unsigned iqCount = fromIEW->iewInfo[tid].iqCount; 1506 1507 PQ.push(iqCount); 1508 threadMap[iqCount] = tid; 1509 } 1510 1511 while (!PQ.empty()) { 1512 ThreadID high_pri = threadMap[PQ.top()]; 1513 1514 if (fetchStatus[high_pri] == Running || 1515 fetchStatus[high_pri] == IcacheAccessComplete || 1516 fetchStatus[high_pri] == Idle) 1517 return high_pri; 1518 else 1519 PQ.pop(); 1520 1521 } 1522 1523 return InvalidThreadID; 1524} 1525 1526template<class Impl> 1527ThreadID 1528DefaultFetch<Impl>::lsqCount() 1529{ 1530 std::priority_queue<unsigned> PQ; 1531 std::map<unsigned, ThreadID> threadMap; 1532 1533 list<ThreadID>::iterator threads = activeThreads->begin(); 1534 list<ThreadID>::iterator end = activeThreads->end(); 1535 1536 while (threads != end) { 1537 ThreadID tid = *threads++; 1538 unsigned ldstqCount = fromIEW->iewInfo[tid].ldstqCount; 1539 1540 PQ.push(ldstqCount); 1541 threadMap[ldstqCount] = tid; 1542 } 1543 1544 while (!PQ.empty()) { 1545 ThreadID high_pri = threadMap[PQ.top()]; 1546 1547 if (fetchStatus[high_pri] == Running || 1548 fetchStatus[high_pri] == IcacheAccessComplete || 1549 fetchStatus[high_pri] == Idle) 1550 return high_pri; 1551 else 1552 PQ.pop(); 1553 } 1554 1555 return InvalidThreadID; 1556} 1557 1558template<class Impl> 1559ThreadID 1560DefaultFetch<Impl>::branchCount() 1561{ 1562#if 0 1563 list<ThreadID>::iterator thread = activeThreads->begin(); 1564 assert(thread != activeThreads->end()); 1565 ThreadID tid = *thread; 1566#endif 1567 1568 panic("Branch Count Fetch policy unimplemented\n"); 1569 return InvalidThreadID; 1570} 1571 1572template<class Impl> 1573void 1574DefaultFetch<Impl>::pipelineIcacheAccesses(ThreadID tid) 1575{ 1576 if (!issuePipelinedIfetch[tid]) { 1577 return; 1578 } 1579 1580 // The next PC to access. 1581 TheISA::PCState thisPC = pc[tid]; 1582 1583 if (isRomMicroPC(thisPC.microPC())) { 1584 return; 1585 } 1586 1587 Addr pcOffset = fetchOffset[tid]; 1588 Addr fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask; 1589 1590 // Align the fetch PC so its at the start of a cache block. 1591 Addr block_PC = icacheBlockAlignPC(fetchAddr); 1592 1593 // Unless buffer already got the block, fetch it from icache. 1594 if (!(cacheDataValid[tid] && block_PC == cacheDataPC[tid])) { 1595 DPRINTF(Fetch, "[tid:%i]: Issuing a pipelined I-cache access, " 1596 "starting at PC %s.\n", tid, thisPC); 1597 1598 fetchCacheLine(fetchAddr, tid, thisPC.instAddr()); 1599 } 1600} 1601 1602template<class Impl> 1603void 1604DefaultFetch<Impl>::profileStall(ThreadID tid) { 1605 DPRINTF(Fetch,"There are no more threads available to fetch from.\n"); 1606 1607 // @todo Per-thread stats 1608 1609 if (stalls[tid].drain) { 1610 ++fetchPendingDrainCycles; 1611 DPRINTF(Fetch, "Fetch is waiting for a drain!\n"); 1612 } else if (activeThreads->empty()) { 1613 ++fetchNoActiveThreadStallCycles; 1614 DPRINTF(Fetch, "Fetch has no active thread!\n"); 1615 } else if (fetchStatus[tid] == Blocked) { 1616 ++fetchBlockedCycles; 1617 DPRINTF(Fetch, "[tid:%i]: Fetch is blocked!\n", tid); 1618 } else if (fetchStatus[tid] == Squashing) { 1619 ++fetchSquashCycles; 1620 DPRINTF(Fetch, "[tid:%i]: Fetch is squashing!\n", tid); 1621 } else if (fetchStatus[tid] == IcacheWaitResponse) { 1622 ++icacheStallCycles; 1623 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n", 1624 tid); 1625 } else if (fetchStatus[tid] == ItlbWait) { 1626 ++fetchTlbCycles; 1627 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting ITLB walk to " 1628 "finish!\n", tid); 1629 } else if (fetchStatus[tid] == TrapPending) { 1630 ++fetchPendingTrapStallCycles; 1631 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting for a pending trap!\n", 1632 tid); 1633 } else if (fetchStatus[tid] == QuiescePending) { 1634 ++fetchPendingQuiesceStallCycles; 1635 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting for a pending quiesce " 1636 "instruction!\n", tid); 1637 } else if (fetchStatus[tid] == IcacheWaitRetry) { 1638 ++fetchIcacheWaitRetryStallCycles; 1639 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting for an I-cache retry!\n", 1640 tid); 1641 } else if (fetchStatus[tid] == NoGoodAddr) { 1642 DPRINTF(Fetch, "[tid:%i]: Fetch predicted non-executable address\n", 1643 tid); 1644 } else { 1645 DPRINTF(Fetch, "[tid:%i]: Unexpected fetch stall reason (Status: %i).\n", 1646 tid, fetchStatus[tid]); 1647 } 1648} 1649