fetch_impl.hh revision 9040:cdfe09f9bdee 
1/*
2 * Copyright (c) 2010-2011 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 *          Korey Sewell
42 */
43
44#include <algorithm>
45#include <cstring>
46#include <list>
47#include <map>
48#include <queue>
49
50#include "arch/isa_traits.hh"
51#include "arch/tlb.hh"
52#include "arch/utility.hh"
53#include "arch/vtophys.hh"
54#include "base/types.hh"
55#include "config/the_isa.hh"
56#include "cpu/base.hh"
57//#include "cpu/checker/cpu.hh"
58#include "cpu/o3/fetch.hh"
59#include "cpu/exetrace.hh"
60#include "debug/Activity.hh"
61#include "debug/Fetch.hh"
62#include "mem/packet.hh"
63#include "params/DerivO3CPU.hh"
64#include "sim/byteswap.hh"
65#include "sim/core.hh"
66#include "sim/eventq.hh"
67#include "sim/full_system.hh"
68#include "sim/system.hh"
69
70using namespace std;
71
72template<class Impl>
73DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params)
74    : cpu(_cpu),
75      branchPred(params),
76      numInst(0),
77      decodeToFetchDelay(params->decodeToFetchDelay),
78      renameToFetchDelay(params->renameToFetchDelay),
79      iewToFetchDelay(params->iewToFetchDelay),
80      commitToFetchDelay(params->commitToFetchDelay),
81      fetchWidth(params->fetchWidth),
82      cacheBlocked(false),
83      retryPkt(NULL),
84      retryTid(InvalidThreadID),
85      numThreads(params->numThreads),
86      numFetchingThreads(params->smtNumFetchingThreads),
87      interruptPending(false),
88      drainPending(false),
89      switchedOut(false),
90      finishTranslationEvent(this)
91{
92    if (numThreads > Impl::MaxThreads)
93        fatal("numThreads (%d) is larger than compiled limit (%d),\n"
94              "\tincrease MaxThreads in src/cpu/o3/impl.hh\n",
95              numThreads, static_cast<int>(Impl::MaxThreads));
96    if (fetchWidth > Impl::MaxWidth)
97        fatal("fetchWidth (%d) is larger than compiled limit (%d),\n"
98             "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
99             fetchWidth, static_cast<int>(Impl::MaxWidth));
100
101    // Set fetch stage's status to inactive.
102    _status = Inactive;
103
104    std::string policy = params->smtFetchPolicy;
105
106    // Convert string to lowercase
107    std::transform(policy.begin(), policy.end(), policy.begin(),
108                   (int(*)(int)) tolower);
109
110    // Figure out fetch policy
111    if (policy == "singlethread") {
112        fetchPolicy = SingleThread;
113        if (numThreads > 1)
114            panic("Invalid Fetch Policy for a SMT workload.");
115    } else if (policy == "roundrobin") {
116        fetchPolicy = RoundRobin;
117        DPRINTF(Fetch, "Fetch policy set to Round Robin\n");
118    } else if (policy == "branch") {
119        fetchPolicy = Branch;
120        DPRINTF(Fetch, "Fetch policy set to Branch Count\n");
121    } else if (policy == "iqcount") {
122        fetchPolicy = IQ;
123        DPRINTF(Fetch, "Fetch policy set to IQ count\n");
124    } else if (policy == "lsqcount") {
125        fetchPolicy = LSQ;
126        DPRINTF(Fetch, "Fetch policy set to LSQ count\n");
127    } else {
128        fatal("Invalid Fetch Policy. Options Are: {SingleThread,"
129              " RoundRobin,LSQcount,IQcount}\n");
130    }
131
132    // Get the size of an instruction.
133    instSize = sizeof(TheISA::MachInst);
134
135    for (int i = 0; i < Impl::MaxThreads; i++)
136        decoder[i] = new TheISA::Decoder(NULL);
137}
138
139template <class Impl>
140std::string
141DefaultFetch<Impl>::name() const
142{
143    return cpu->name() + ".fetch";
144}
145
146template <class Impl>
147void
148DefaultFetch<Impl>::regStats()
149{
150    icacheStallCycles
151        .name(name() + ".icacheStallCycles")
152        .desc("Number of cycles fetch is stalled on an Icache miss")
153        .prereq(icacheStallCycles);
154
155    fetchedInsts
156        .name(name() + ".Insts")
157        .desc("Number of instructions fetch has processed")
158        .prereq(fetchedInsts);
159
160    fetchedBranches
161        .name(name() + ".Branches")
162        .desc("Number of branches that fetch encountered")
163        .prereq(fetchedBranches);
164
165    predictedBranches
166        .name(name() + ".predictedBranches")
167        .desc("Number of branches that fetch has predicted taken")
168        .prereq(predictedBranches);
169
170    fetchCycles
171        .name(name() + ".Cycles")
172        .desc("Number of cycles fetch has run and was not squashing or"
173              " blocked")
174        .prereq(fetchCycles);
175
176    fetchSquashCycles
177        .name(name() + ".SquashCycles")
178        .desc("Number of cycles fetch has spent squashing")
179        .prereq(fetchSquashCycles);
180
181    fetchTlbCycles
182        .name(name() + ".TlbCycles")
183        .desc("Number of cycles fetch has spent waiting for tlb")
184        .prereq(fetchTlbCycles);
185
186    fetchIdleCycles
187        .name(name() + ".IdleCycles")
188        .desc("Number of cycles fetch was idle")
189        .prereq(fetchIdleCycles);
190
191    fetchBlockedCycles
192        .name(name() + ".BlockedCycles")
193        .desc("Number of cycles fetch has spent blocked")
194        .prereq(fetchBlockedCycles);
195
196    fetchedCacheLines
197        .name(name() + ".CacheLines")
198        .desc("Number of cache lines fetched")
199        .prereq(fetchedCacheLines);
200
201    fetchMiscStallCycles
202        .name(name() + ".MiscStallCycles")
203        .desc("Number of cycles fetch has spent waiting on interrupts, or "
204              "bad addresses, or out of MSHRs")
205        .prereq(fetchMiscStallCycles);
206
207    fetchPendingDrainCycles
208        .name(name() + ".PendingDrainCycles")
209        .desc("Number of cycles fetch has spent waiting on pipes to drain")
210        .prereq(fetchPendingDrainCycles);
211
212    fetchNoActiveThreadStallCycles
213        .name(name() + ".NoActiveThreadStallCycles")
214        .desc("Number of stall cycles due to no active thread to fetch from")
215        .prereq(fetchNoActiveThreadStallCycles);
216
217    fetchPendingTrapStallCycles
218        .name(name() + ".PendingTrapStallCycles")
219        .desc("Number of stall cycles due to pending traps")
220        .prereq(fetchPendingTrapStallCycles);
221
222    fetchPendingQuiesceStallCycles
223        .name(name() + ".PendingQuiesceStallCycles")
224        .desc("Number of stall cycles due to pending quiesce instructions")
225        .prereq(fetchPendingQuiesceStallCycles);
226
227    fetchIcacheWaitRetryStallCycles
228        .name(name() + ".IcacheWaitRetryStallCycles")
229        .desc("Number of stall cycles due to full MSHR")
230        .prereq(fetchIcacheWaitRetryStallCycles);
231
232    fetchIcacheSquashes
233        .name(name() + ".IcacheSquashes")
234        .desc("Number of outstanding Icache misses that were squashed")
235        .prereq(fetchIcacheSquashes);
236
237    fetchTlbSquashes
238        .name(name() + ".ItlbSquashes")
239        .desc("Number of outstanding ITLB misses that were squashed")
240        .prereq(fetchTlbSquashes);
241
242    fetchNisnDist
243        .init(/* base value */ 0,
244              /* last value */ fetchWidth,
245              /* bucket size */ 1)
246        .name(name() + ".rateDist")
247        .desc("Number of instructions fetched each cycle (Total)")
248        .flags(Stats::pdf);
249
250    idleRate
251        .name(name() + ".idleRate")
252        .desc("Percent of cycles fetch was idle")
253        .prereq(idleRate);
254    idleRate = fetchIdleCycles * 100 / cpu->numCycles;
255
256    branchRate
257        .name(name() + ".branchRate")
258        .desc("Number of branch fetches per cycle")
259        .flags(Stats::total);
260    branchRate = fetchedBranches / cpu->numCycles;
261
262    fetchRate
263        .name(name() + ".rate")
264        .desc("Number of inst fetches per cycle")
265        .flags(Stats::total);
266    fetchRate = fetchedInsts / cpu->numCycles;
267
268    branchPred.regStats();
269}
270
271template<class Impl>
272void
273DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
274{
275    timeBuffer = time_buffer;
276
277    // Create wires to get information from proper places in time buffer.
278    fromDecode = timeBuffer->getWire(-decodeToFetchDelay);
279    fromRename = timeBuffer->getWire(-renameToFetchDelay);
280    fromIEW = timeBuffer->getWire(-iewToFetchDelay);
281    fromCommit = timeBuffer->getWire(-commitToFetchDelay);
282}
283
284template<class Impl>
285void
286DefaultFetch<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr)
287{
288    activeThreads = at_ptr;
289}
290
291template<class Impl>
292void
293DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
294{
295    fetchQueue = fq_ptr;
296
297    // Create wire to write information to proper place in fetch queue.
298    toDecode = fetchQueue->getWire(0);
299}
300
301template<class Impl>
302void
303DefaultFetch<Impl>::initStage()
304{
305    // Setup PC and nextPC with initial state.
306    for (ThreadID tid = 0; tid < numThreads; tid++) {
307        pc[tid] = cpu->pcState(tid);
308        fetchOffset[tid] = 0;
309        macroop[tid] = NULL;
310        delayedCommit[tid] = false;
311    }
312
313    for (ThreadID tid = 0; tid < numThreads; tid++) {
314
315        fetchStatus[tid] = Running;
316
317        priorityList.push_back(tid);
318
319        memReq[tid] = NULL;
320
321        stalls[tid].decode = false;
322        stalls[tid].rename = false;
323        stalls[tid].iew = false;
324        stalls[tid].commit = false;
325    }
326
327    // Schedule fetch to get the correct PC from the CPU
328    // scheduleFetchStartupEvent(1);
329
330    // Fetch needs to start fetching instructions at the very beginning,
331    // so it must start up in active state.
332    switchToActive();
333}
334
335template<class Impl>
336void
337DefaultFetch<Impl>::setIcache()
338{
339    assert(cpu->getInstPort().isConnected());
340
341    // Size of cache block.
342    cacheBlkSize = cpu->getInstPort().peerBlockSize();
343
344    // Create mask to get rid of offset bits.
345    cacheBlkMask = (cacheBlkSize - 1);
346
347    for (ThreadID tid = 0; tid < numThreads; tid++) {
348        // Create space to store a cache line.
349        cacheData[tid] = new uint8_t[cacheBlkSize];
350        cacheDataPC[tid] = 0;
351        cacheDataValid[tid] = false;
352    }
353}
354
355template<class Impl>
356void
357DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
358{
359    ThreadID tid = pkt->req->threadId();
360
361    DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n", tid);
362
363    assert(!pkt->wasNacked());
364
365    // Only change the status if it's still waiting on the icache access
366    // to return.
367    if (fetchStatus[tid] != IcacheWaitResponse ||
368        pkt->req != memReq[tid] ||
369        isSwitchedOut()) {
370        ++fetchIcacheSquashes;
371        delete pkt->req;
372        delete pkt;
373        return;
374    }
375
376    memcpy(cacheData[tid], pkt->getPtr<uint8_t>(), cacheBlkSize);
377    cacheDataValid[tid] = true;
378
379    if (!drainPending) {
380        // Wake up the CPU (if it went to sleep and was waiting on
381        // this completion event).
382        cpu->wakeCPU();
383
384        DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",
385                tid);
386
387        switchToActive();
388    }
389
390    // Only switch to IcacheAccessComplete if we're not stalled as well.
391    if (checkStall(tid)) {
392        fetchStatus[tid] = Blocked;
393    } else {
394        fetchStatus[tid] = IcacheAccessComplete;
395    }
396
397    // Reset the mem req to NULL.
398    delete pkt->req;
399    delete pkt;
400    memReq[tid] = NULL;
401}
402
403template <class Impl>
404bool
405DefaultFetch<Impl>::drain()
406{
407    // Fetch is ready to drain at any time.
408    cpu->signalDrained();
409    drainPending = true;
410    return true;
411}
412
413template <class Impl>
414void
415DefaultFetch<Impl>::resume()
416{
417    drainPending = false;
418}
419
420template <class Impl>
421void
422DefaultFetch<Impl>::switchOut()
423{
424    switchedOut = true;
425    // Branch predictor needs to have its state cleared.
426    branchPred.switchOut();
427}
428
429template <class Impl>
430void
431DefaultFetch<Impl>::takeOverFrom()
432{
433    // the instruction port is now connected so we can get the block
434    // size
435    setIcache();
436
437    // Reset all state
438    for (ThreadID i = 0; i < Impl::MaxThreads; ++i) {
439        stalls[i].decode = 0;
440        stalls[i].rename = 0;
441        stalls[i].iew = 0;
442        stalls[i].commit = 0;
443        pc[i] = cpu->pcState(i);
444        fetchStatus[i] = Running;
445    }
446    numInst = 0;
447    wroteToTimeBuffer = false;
448    _status = Inactive;
449    switchedOut = false;
450    interruptPending = false;
451    branchPred.takeOverFrom();
452}
453
454template <class Impl>
455void
456DefaultFetch<Impl>::wakeFromQuiesce()
457{
458    DPRINTF(Fetch, "Waking up from quiesce\n");
459    // Hopefully this is safe
460    // @todo: Allow other threads to wake from quiesce.
461    fetchStatus[0] = Running;
462}
463
464template <class Impl>
465inline void
466DefaultFetch<Impl>::switchToActive()
467{
468    if (_status == Inactive) {
469        DPRINTF(Activity, "Activating stage.\n");
470
471        cpu->activateStage(O3CPU::FetchIdx);
472
473        _status = Active;
474    }
475}
476
477template <class Impl>
478inline void
479DefaultFetch<Impl>::switchToInactive()
480{
481    if (_status == Active) {
482        DPRINTF(Activity, "Deactivating stage.\n");
483
484        cpu->deactivateStage(O3CPU::FetchIdx);
485
486        _status = Inactive;
487    }
488}
489
490template <class Impl>
491bool
492DefaultFetch<Impl>::lookupAndUpdateNextPC(
493        DynInstPtr &inst, TheISA::PCState &nextPC)
494{
495    // Do branch prediction check here.
496    // A bit of a misnomer...next_PC is actually the current PC until
497    // this function updates it.
498    bool predict_taken;
499
500    if (!inst->isControl()) {
501        TheISA::advancePC(nextPC, inst->staticInst);
502        inst->setPredTarg(nextPC);
503        inst->setPredTaken(false);
504        return false;
505    }
506
507    ThreadID tid = inst->threadNumber;
508    predict_taken = branchPred.predict(inst, nextPC, tid);
509
510    if (predict_taken) {
511        DPRINTF(Fetch, "[tid:%i]: [sn:%i]:  Branch predicted to be taken to %s.\n",
512                tid, inst->seqNum, nextPC);
513    } else {
514        DPRINTF(Fetch, "[tid:%i]: [sn:%i]:Branch predicted to be not taken.\n",
515                tid, inst->seqNum);
516    }
517
518    DPRINTF(Fetch, "[tid:%i]: [sn:%i] Branch predicted to go to %s.\n",
519            tid, inst->seqNum, nextPC);
520    inst->setPredTarg(nextPC);
521    inst->setPredTaken(predict_taken);
522
523    ++fetchedBranches;
524
525    if (predict_taken) {
526        ++predictedBranches;
527    }
528
529    return predict_taken;
530}
531
532template <class Impl>
533bool
534DefaultFetch<Impl>::fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc)
535{
536    Fault fault = NoFault;
537
538    // @todo: not sure if these should block translation.
539    //AlphaDep
540    if (cacheBlocked) {
541        DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n",
542                tid);
543        return false;
544    } else if (isSwitchedOut()) {
545        DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, switched out\n",
546                tid);
547        return false;
548    } else if (checkInterrupt(pc) && !delayedCommit[tid]) {
549        // Hold off fetch from getting new instructions when:
550        // Cache is blocked, or
551        // while an interrupt is pending and we're not in PAL mode, or
552        // fetch is switched out.
553        DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n",
554                tid);
555        return false;
556    }
557
558    // Align the fetch address so it's at the start of a cache block.
559    Addr block_PC = icacheBlockAlignPC(vaddr);
560
561    DPRINTF(Fetch, "[tid:%i] Fetching cache line %#x for addr %#x\n",
562            tid, block_PC, vaddr);
563
564    // Setup the memReq to do a read of the first instruction's address.
565    // Set the appropriate read size and flags as well.
566    // Build request here.
567    RequestPtr mem_req =
568        new Request(tid, block_PC, cacheBlkSize, Request::INST_FETCH,
569                    cpu->instMasterId(), pc, cpu->thread[tid]->contextId(), tid);
570
571    memReq[tid] = mem_req;
572
573    // Initiate translation of the icache block
574    fetchStatus[tid] = ItlbWait;
575    FetchTranslation *trans = new FetchTranslation(this);
576    cpu->itb->translateTiming(mem_req, cpu->thread[tid]->getTC(),
577                              trans, BaseTLB::Execute);
578    return true;
579}
580
581template <class Impl>
582void
583DefaultFetch<Impl>::finishTranslation(Fault fault, RequestPtr mem_req)
584{
585    ThreadID tid = mem_req->threadId();
586    Addr block_PC = mem_req->getVaddr();
587
588    // Wake up CPU if it was idle
589    cpu->wakeCPU();
590
591    if (fetchStatus[tid] != ItlbWait || mem_req != memReq[tid] ||
592        mem_req->getVaddr() != memReq[tid]->getVaddr() || isSwitchedOut()) {
593        DPRINTF(Fetch, "[tid:%i] Ignoring itlb completed after squash\n",
594                tid);
595        ++fetchTlbSquashes;
596        delete mem_req;
597        return;
598    }
599
600
601    // If translation was successful, attempt to read the icache block.
602    if (fault == NoFault) {
603        // Check that we're not going off into random memory
604        // If we have, just wait around for commit to squash something and put
605        // us on the right track
606        if (!cpu->system->isMemAddr(mem_req->getPaddr())) {
607            warn("Address %#x is outside of physical memory, stopping fetch\n",
608                    mem_req->getPaddr());
609            fetchStatus[tid] = NoGoodAddr;
610            delete mem_req;
611            memReq[tid] = NULL;
612            return;
613        }
614
615        // Build packet here.
616        PacketPtr data_pkt = new Packet(mem_req, MemCmd::ReadReq);
617        data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]);
618
619        cacheDataPC[tid] = block_PC;
620        cacheDataValid[tid] = false;
621        DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
622
623        fetchedCacheLines++;
624
625        // Access the cache.
626        if (!cpu->getInstPort().sendTimingReq(data_pkt)) {
627            assert(retryPkt == NULL);
628            assert(retryTid == InvalidThreadID);
629            DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
630
631            fetchStatus[tid] = IcacheWaitRetry;
632            retryPkt = data_pkt;
633            retryTid = tid;
634            cacheBlocked = true;
635        } else {
636            DPRINTF(Fetch, "[tid:%i]: Doing Icache access.\n", tid);
637            DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
638                    "response.\n", tid);
639
640            lastIcacheStall[tid] = curTick();
641            fetchStatus[tid] = IcacheWaitResponse;
642        }
643    } else {
644        if (!(numInst < fetchWidth)) {
645            assert(!finishTranslationEvent.scheduled());
646            finishTranslationEvent.setFault(fault);
647            finishTranslationEvent.setReq(mem_req);
648            cpu->schedule(finishTranslationEvent, cpu->nextCycle(curTick() + cpu->ticks(1)));
649            return;
650        }
651        DPRINTF(Fetch, "[tid:%i] Got back req with addr %#x but expected %#x\n",
652                tid, mem_req->getVaddr(), memReq[tid]->getVaddr());
653        // Translation faulted, icache request won't be sent.
654        delete mem_req;
655        memReq[tid] = NULL;
656
657        // Send the fault to commit.  This thread will not do anything
658        // until commit handles the fault.  The only other way it can
659        // wake up is if a squash comes along and changes the PC.
660        TheISA::PCState fetchPC = pc[tid];
661
662        DPRINTF(Fetch, "[tid:%i]: Translation faulted, building noop.\n", tid);
663        // We will use a nop in ordier to carry the fault.
664        DynInstPtr instruction = buildInst(tid, TheISA::NoopStaticInst,
665                NULL, fetchPC, fetchPC, false);
666
667        instruction->setPredTarg(fetchPC);
668        instruction->fault = fault;
669        wroteToTimeBuffer = true;
670
671        DPRINTF(Activity, "Activity this cycle.\n");
672        cpu->activityThisCycle();
673
674        fetchStatus[tid] = TrapPending;
675
676        DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n", tid);
677        DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %s.\n",
678                tid, fault->name(), pc[tid]);
679    }
680    _status = updateFetchStatus();
681}
682
683template <class Impl>
684inline void
685DefaultFetch<Impl>::doSquash(const TheISA::PCState &newPC,
686                             const DynInstPtr squashInst, ThreadID tid)
687{
688    DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %s.\n",
689            tid, newPC);
690
691    pc[tid] = newPC;
692    fetchOffset[tid] = 0;
693    if (squashInst && squashInst->pcState().instAddr() == newPC.instAddr())
694        macroop[tid] = squashInst->macroop;
695    else
696        macroop[tid] = NULL;
697    decoder[tid]->reset();
698
699    // Clear the icache miss if it's outstanding.
700    if (fetchStatus[tid] == IcacheWaitResponse) {
701        DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
702                tid);
703        memReq[tid] = NULL;
704    } else if (fetchStatus[tid] == ItlbWait) {
705        DPRINTF(Fetch, "[tid:%i]: Squashing outstanding ITLB miss.\n",
706                tid);
707        memReq[tid] = NULL;
708    }
709
710    // Get rid of the retrying packet if it was from this thread.
711    if (retryTid == tid) {
712        assert(cacheBlocked);
713        if (retryPkt) {
714            delete retryPkt->req;
715            delete retryPkt;
716        }
717        retryPkt = NULL;
718        retryTid = InvalidThreadID;
719    }
720
721    fetchStatus[tid] = Squashing;
722
723    // microops are being squashed, it is not known wheather the
724    // youngest non-squashed microop was  marked delayed commit
725    // or not. Setting the flag to true ensures that the
726    // interrupts are not handled when they cannot be, though
727    // some opportunities to handle interrupts may be missed.
728    delayedCommit[tid] = true;
729
730    ++fetchSquashCycles;
731}
732
733template<class Impl>
734void
735DefaultFetch<Impl>::squashFromDecode(const TheISA::PCState &newPC,
736                                     const DynInstPtr squashInst,
737                                     const InstSeqNum seq_num, ThreadID tid)
738{
739    DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n", tid);
740
741    doSquash(newPC, squashInst, tid);
742
743    // Tell the CPU to remove any instructions that are in flight between
744    // fetch and decode.
745    cpu->removeInstsUntil(seq_num, tid);
746}
747
748template<class Impl>
749bool
750DefaultFetch<Impl>::checkStall(ThreadID tid) const
751{
752    bool ret_val = false;
753
754    if (cpu->contextSwitch) {
755        DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid);
756        ret_val = true;
757    } else if (stalls[tid].decode) {
758        DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid);
759        ret_val = true;
760    } else if (stalls[tid].rename) {
761        DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid);
762        ret_val = true;
763    } else if (stalls[tid].iew) {
764        DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid);
765        ret_val = true;
766    } else if (stalls[tid].commit) {
767        DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid);
768        ret_val = true;
769    }
770
771    return ret_val;
772}
773
774template<class Impl>
775typename DefaultFetch<Impl>::FetchStatus
776DefaultFetch<Impl>::updateFetchStatus()
777{
778    //Check Running
779    list<ThreadID>::iterator threads = activeThreads->begin();
780    list<ThreadID>::iterator end = activeThreads->end();
781
782    while (threads != end) {
783        ThreadID tid = *threads++;
784
785        if (fetchStatus[tid] == Running ||
786            fetchStatus[tid] == Squashing ||
787            fetchStatus[tid] == IcacheAccessComplete) {
788
789            if (_status == Inactive) {
790                DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid);
791
792                if (fetchStatus[tid] == IcacheAccessComplete) {
793                    DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache"
794                            "completion\n",tid);
795                }
796
797                cpu->activateStage(O3CPU::FetchIdx);
798            }
799
800            return Active;
801        }
802    }
803
804    // Stage is switching from active to inactive, notify CPU of it.
805    if (_status == Active) {
806        DPRINTF(Activity, "Deactivating stage.\n");
807
808        cpu->deactivateStage(O3CPU::FetchIdx);
809    }
810
811    return Inactive;
812}
813
814template <class Impl>
815void
816DefaultFetch<Impl>::squash(const TheISA::PCState &newPC,
817                           const InstSeqNum seq_num, DynInstPtr squashInst,
818                           ThreadID tid)
819{
820    DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n", tid);
821
822    doSquash(newPC, squashInst, tid);
823
824    // Tell the CPU to remove any instructions that are not in the ROB.
825    cpu->removeInstsNotInROB(tid);
826}
827
828template <class Impl>
829void
830DefaultFetch<Impl>::tick()
831{
832    list<ThreadID>::iterator threads = activeThreads->begin();
833    list<ThreadID>::iterator end = activeThreads->end();
834    bool status_change = false;
835
836    wroteToTimeBuffer = false;
837
838    for (ThreadID i = 0; i < Impl::MaxThreads; ++i) {
839        issuePipelinedIfetch[i] = false;
840    }
841
842    while (threads != end) {
843        ThreadID tid = *threads++;
844
845        // Check the signals for each thread to determine the proper status
846        // for each thread.
847        bool updated_status = checkSignalsAndUpdate(tid);
848        status_change =  status_change || updated_status;
849    }
850
851    DPRINTF(Fetch, "Running stage.\n");
852
853    if (FullSystem) {
854        if (fromCommit->commitInfo[0].interruptPending) {
855            interruptPending = true;
856        }
857
858        if (fromCommit->commitInfo[0].clearInterrupt) {
859            interruptPending = false;
860        }
861    }
862
863    for (threadFetched = 0; threadFetched < numFetchingThreads;
864         threadFetched++) {
865        // Fetch each of the actively fetching threads.
866        fetch(status_change);
867    }
868
869    // Record number of instructions fetched this cycle for distribution.
870    fetchNisnDist.sample(numInst);
871
872    if (status_change) {
873        // Change the fetch stage status if there was a status change.
874        _status = updateFetchStatus();
875    }
876
877    // If there was activity this cycle, inform the CPU of it.
878    if (wroteToTimeBuffer || cpu->contextSwitch) {
879        DPRINTF(Activity, "Activity this cycle.\n");
880
881        cpu->activityThisCycle();
882    }
883
884    // Issue the next I-cache request if possible.
885    for (ThreadID i = 0; i < Impl::MaxThreads; ++i) {
886        if (issuePipelinedIfetch[i]) {
887            pipelineIcacheAccesses(i);
888        }
889    }
890
891    // Reset the number of the instruction we've fetched.
892    numInst = 0;
893}
894
895template <class Impl>
896bool
897DefaultFetch<Impl>::checkSignalsAndUpdate(ThreadID tid)
898{
899    // Update the per thread stall statuses.
900    if (fromDecode->decodeBlock[tid]) {
901        stalls[tid].decode = true;
902    }
903
904    if (fromDecode->decodeUnblock[tid]) {
905        assert(stalls[tid].decode);
906        assert(!fromDecode->decodeBlock[tid]);
907        stalls[tid].decode = false;
908    }
909
910    if (fromRename->renameBlock[tid]) {
911        stalls[tid].rename = true;
912    }
913
914    if (fromRename->renameUnblock[tid]) {
915        assert(stalls[tid].rename);
916        assert(!fromRename->renameBlock[tid]);
917        stalls[tid].rename = false;
918    }
919
920    if (fromIEW->iewBlock[tid]) {
921        stalls[tid].iew = true;
922    }
923
924    if (fromIEW->iewUnblock[tid]) {
925        assert(stalls[tid].iew);
926        assert(!fromIEW->iewBlock[tid]);
927        stalls[tid].iew = false;
928    }
929
930    if (fromCommit->commitBlock[tid]) {
931        stalls[tid].commit = true;
932    }
933
934    if (fromCommit->commitUnblock[tid]) {
935        assert(stalls[tid].commit);
936        assert(!fromCommit->commitBlock[tid]);
937        stalls[tid].commit = false;
938    }
939
940    // Check squash signals from commit.
941    if (fromCommit->commitInfo[tid].squash) {
942
943        DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
944                "from commit.\n",tid);
945        // In any case, squash.
946        squash(fromCommit->commitInfo[tid].pc,
947               fromCommit->commitInfo[tid].doneSeqNum,
948               fromCommit->commitInfo[tid].squashInst, tid);
949
950        // If it was a branch mispredict on a control instruction, update the
951        // branch predictor with that instruction, otherwise just kill the
952        // invalid state we generated in after sequence number
953        if (fromCommit->commitInfo[tid].mispredictInst &&
954            fromCommit->commitInfo[tid].mispredictInst->isControl()) {
955            branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
956                              fromCommit->commitInfo[tid].pc,
957                              fromCommit->commitInfo[tid].branchTaken,
958                              tid);
959        } else {
960            branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
961                              tid);
962        }
963
964        return true;
965    } else if (fromCommit->commitInfo[tid].doneSeqNum) {
966        // Update the branch predictor if it wasn't a squashed instruction
967        // that was broadcasted.
968        branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid);
969    }
970
971    // Check ROB squash signals from commit.
972    if (fromCommit->commitInfo[tid].robSquashing) {
973        DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid);
974
975        // Continue to squash.
976        fetchStatus[tid] = Squashing;
977
978        return true;
979    }
980
981    // Check squash signals from decode.
982    if (fromDecode->decodeInfo[tid].squash) {
983        DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
984                "from decode.\n",tid);
985
986        // Update the branch predictor.
987        if (fromDecode->decodeInfo[tid].branchMispredict) {
988            branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
989                              fromDecode->decodeInfo[tid].nextPC,
990                              fromDecode->decodeInfo[tid].branchTaken,
991                              tid);
992        } else {
993            branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
994                              tid);
995        }
996
997        if (fetchStatus[tid] != Squashing) {
998
999            DPRINTF(Fetch, "Squashing from decode with PC = %s\n",
1000                fromDecode->decodeInfo[tid].nextPC);
1001            // Squash unless we're already squashing
1002            squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
1003                             fromDecode->decodeInfo[tid].squashInst,
1004                             fromDecode->decodeInfo[tid].doneSeqNum,
1005                             tid);
1006
1007            return true;
1008        }
1009    }
1010
1011    if (checkStall(tid) &&
1012        fetchStatus[tid] != IcacheWaitResponse &&
1013        fetchStatus[tid] != IcacheWaitRetry) {
1014        DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid);
1015
1016        fetchStatus[tid] = Blocked;
1017
1018        return true;
1019    }
1020
1021    if (fetchStatus[tid] == Blocked ||
1022        fetchStatus[tid] == Squashing) {
1023        // Switch status to running if fetch isn't being told to block or
1024        // squash this cycle.
1025        DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n",
1026                tid);
1027
1028        fetchStatus[tid] = Running;
1029
1030        return true;
1031    }
1032
1033    // If we've reached this point, we have not gotten any signals that
1034    // cause fetch to change its status.  Fetch remains the same as before.
1035    return false;
1036}
1037
1038template<class Impl>
1039typename Impl::DynInstPtr
1040DefaultFetch<Impl>::buildInst(ThreadID tid, StaticInstPtr staticInst,
1041                              StaticInstPtr curMacroop, TheISA::PCState thisPC,
1042                              TheISA::PCState nextPC, bool trace)
1043{
1044    // Get a sequence number.
1045    InstSeqNum seq = cpu->getAndIncrementInstSeq();
1046
1047    // Create a new DynInst from the instruction fetched.
1048    DynInstPtr instruction =
1049        new DynInst(staticInst, curMacroop, thisPC, nextPC, seq, cpu);
1050    instruction->setTid(tid);
1051
1052    instruction->setASID(tid);
1053
1054    instruction->setThreadState(cpu->thread[tid]);
1055
1056    DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x (%d) created "
1057            "[sn:%lli].\n", tid, thisPC.instAddr(),
1058            thisPC.microPC(), seq);
1059
1060    DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", tid,
1061            instruction->staticInst->
1062            disassemble(thisPC.instAddr()));
1063
1064#if TRACING_ON
1065    if (trace) {
1066        instruction->traceData =
1067            cpu->getTracer()->getInstRecord(curTick(), cpu->tcBase(tid),
1068                    instruction->staticInst, thisPC, curMacroop);
1069    }
1070#else
1071    instruction->traceData = NULL;
1072#endif
1073
1074    // Add instruction to the CPU's list of instructions.
1075    instruction->setInstListIt(cpu->addInst(instruction));
1076
1077    // Write the instruction to the first slot in the queue
1078    // that heads to decode.
1079    assert(numInst < fetchWidth);
1080    toDecode->insts[toDecode->size++] = instruction;
1081
1082    // Keep track of if we can take an interrupt at this boundary
1083    delayedCommit[tid] = instruction->isDelayedCommit();
1084
1085    return instruction;
1086}
1087
1088template<class Impl>
1089void
1090DefaultFetch<Impl>::fetch(bool &status_change)
1091{
1092    //////////////////////////////////////////
1093    // Start actual fetch
1094    //////////////////////////////////////////
1095    ThreadID tid = getFetchingThread(fetchPolicy);
1096
1097    if (tid == InvalidThreadID || drainPending) {
1098        // Breaks looping condition in tick()
1099        threadFetched = numFetchingThreads;
1100
1101        if (numThreads == 1) {  // @todo Per-thread stats
1102            profileStall(0);
1103        }
1104
1105        return;
1106    }
1107
1108    DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
1109
1110    // The current PC.
1111    TheISA::PCState thisPC = pc[tid];
1112
1113    Addr pcOffset = fetchOffset[tid];
1114    Addr fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask;
1115
1116    bool inRom = isRomMicroPC(thisPC.microPC());
1117
1118    // If returning from the delay of a cache miss, then update the status
1119    // to running, otherwise do the cache access.  Possibly move this up
1120    // to tick() function.
1121    if (fetchStatus[tid] == IcacheAccessComplete) {
1122        DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n", tid);
1123
1124        fetchStatus[tid] = Running;
1125        status_change = true;
1126    } else if (fetchStatus[tid] == Running) {
1127        // Align the fetch PC so its at the start of a cache block.
1128        Addr block_PC = icacheBlockAlignPC(fetchAddr);
1129
1130        // If buffer is no longer valid or fetchAddr has moved to point
1131        // to the next cache block, AND we have no remaining ucode
1132        // from a macro-op, then start fetch from icache.
1133        if (!(cacheDataValid[tid] && block_PC == cacheDataPC[tid])
1134            && !inRom && !macroop[tid]) {
1135            DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
1136                    "instruction, starting at PC %s.\n", tid, thisPC);
1137
1138            fetchCacheLine(fetchAddr, tid, thisPC.instAddr());
1139
1140            if (fetchStatus[tid] == IcacheWaitResponse)
1141                ++icacheStallCycles;
1142            else if (fetchStatus[tid] == ItlbWait)
1143                ++fetchTlbCycles;
1144            else
1145                ++fetchMiscStallCycles;
1146            return;
1147        } else if ((checkInterrupt(thisPC.instAddr()) && !delayedCommit[tid])
1148                   || isSwitchedOut()) {
1149            // Stall CPU if an interrupt is posted and we're not issuing
1150            // an delayed commit micro-op currently (delayed commit instructions
1151            // are not interruptable by interrupts, only faults)
1152            ++fetchMiscStallCycles;
1153            DPRINTF(Fetch, "[tid:%i]: Fetch is stalled!\n", tid);
1154            return;
1155        }
1156    } else {
1157        if (fetchStatus[tid] == Idle) {
1158            ++fetchIdleCycles;
1159            DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid);
1160        }
1161
1162        // Status is Idle, so fetch should do nothing.
1163        return;
1164    }
1165
1166    ++fetchCycles;
1167
1168    TheISA::PCState nextPC = thisPC;
1169
1170    StaticInstPtr staticInst = NULL;
1171    StaticInstPtr curMacroop = macroop[tid];
1172
1173    // If the read of the first instruction was successful, then grab the
1174    // instructions from the rest of the cache line and put them into the
1175    // queue heading to decode.
1176
1177    DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
1178            "decode.\n", tid);
1179
1180    // Need to keep track of whether or not a predicted branch
1181    // ended this fetch block.
1182    bool predictedBranch = false;
1183
1184    TheISA::MachInst *cacheInsts =
1185        reinterpret_cast<TheISA::MachInst *>(cacheData[tid]);
1186
1187    const unsigned numInsts = cacheBlkSize / instSize;
1188    unsigned blkOffset = (fetchAddr - cacheDataPC[tid]) / instSize;
1189
1190    // Loop through instruction memory from the cache.
1191    // Keep issuing while fetchWidth is available and branch is not
1192    // predicted taken
1193    while (numInst < fetchWidth && !predictedBranch) {
1194
1195        // We need to process more memory if we aren't going to get a
1196        // StaticInst from the rom, the current macroop, or what's already
1197        // in the decoder.
1198        bool needMem = !inRom && !curMacroop &&
1199            !decoder[tid]->instReady();
1200        fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask;
1201        Addr block_PC = icacheBlockAlignPC(fetchAddr);
1202
1203        if (needMem) {
1204            // If buffer is no longer valid or fetchAddr has moved to point
1205            // to the next cache block then start fetch from icache.
1206            if (!cacheDataValid[tid] || block_PC != cacheDataPC[tid])
1207                break;
1208
1209            if (blkOffset >= numInsts) {
1210                // We need to process more memory, but we've run out of the
1211                // current block.
1212                break;
1213            }
1214
1215            if (ISA_HAS_DELAY_SLOT && pcOffset == 0) {
1216                // Walk past any annulled delay slot instructions.
1217                Addr pcAddr = thisPC.instAddr() & BaseCPU::PCMask;
1218                while (fetchAddr != pcAddr && blkOffset < numInsts) {
1219                    blkOffset++;
1220                    fetchAddr += instSize;
1221                }
1222                if (blkOffset >= numInsts)
1223                    break;
1224            }
1225            MachInst inst = TheISA::gtoh(cacheInsts[blkOffset]);
1226
1227            decoder[tid]->setTC(cpu->thread[tid]->getTC());
1228            decoder[tid]->moreBytes(thisPC, fetchAddr, inst);
1229
1230            if (decoder[tid]->needMoreBytes()) {
1231                blkOffset++;
1232                fetchAddr += instSize;
1233                pcOffset += instSize;
1234            }
1235        }
1236
1237        // Extract as many instructions and/or microops as we can from
1238        // the memory we've processed so far.
1239        do {
1240            if (!(curMacroop || inRom)) {
1241                if (decoder[tid]->instReady()) {
1242                    staticInst = decoder[tid]->decode(thisPC);
1243
1244                    // Increment stat of fetched instructions.
1245                    ++fetchedInsts;
1246
1247                    if (staticInst->isMacroop()) {
1248                        curMacroop = staticInst;
1249                    } else {
1250                        pcOffset = 0;
1251                    }
1252                } else {
1253                    // We need more bytes for this instruction so blkOffset and
1254                    // pcOffset will be updated
1255                    break;
1256                }
1257            }
1258            // Whether we're moving to a new macroop because we're at the
1259            // end of the current one, or the branch predictor incorrectly
1260            // thinks we are...
1261            bool newMacro = false;
1262            if (curMacroop || inRom) {
1263                if (inRom) {
1264                    staticInst = cpu->microcodeRom.fetchMicroop(
1265                            thisPC.microPC(), curMacroop);
1266                } else {
1267                    staticInst = curMacroop->fetchMicroop(thisPC.microPC());
1268                }
1269                newMacro |= staticInst->isLastMicroop();
1270            }
1271
1272            DynInstPtr instruction =
1273                buildInst(tid, staticInst, curMacroop,
1274                          thisPC, nextPC, true);
1275
1276            numInst++;
1277
1278#if TRACING_ON
1279            instruction->fetchTick = curTick();
1280#endif
1281
1282            nextPC = thisPC;
1283
1284            // If we're branching after this instruction, quite fetching
1285            // from the same block then.
1286            predictedBranch |= thisPC.branching();
1287            predictedBranch |=
1288                lookupAndUpdateNextPC(instruction, nextPC);
1289            if (predictedBranch) {
1290                DPRINTF(Fetch, "Branch detected with PC = %s\n", thisPC);
1291            }
1292
1293            newMacro |= thisPC.instAddr() != nextPC.instAddr();
1294
1295            // Move to the next instruction, unless we have a branch.
1296            thisPC = nextPC;
1297            inRom = isRomMicroPC(thisPC.microPC());
1298
1299            if (newMacro) {
1300                fetchAddr = thisPC.instAddr() & BaseCPU::PCMask;
1301                blkOffset = (fetchAddr - cacheDataPC[tid]) / instSize;
1302                pcOffset = 0;
1303                curMacroop = NULL;
1304            }
1305
1306            if (instruction->isQuiesce()) {
1307                DPRINTF(Fetch,
1308                        "Quiesce instruction encountered, halting fetch!");
1309                fetchStatus[tid] = QuiescePending;
1310                status_change = true;
1311                break;
1312            }
1313        } while ((curMacroop || decoder[tid]->instReady()) &&
1314                 numInst < fetchWidth);
1315    }
1316
1317    if (predictedBranch) {
1318        DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch "
1319                "instruction encountered.\n", tid);
1320    } else if (numInst >= fetchWidth) {
1321        DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth "
1322                "for this cycle.\n", tid);
1323    } else if (blkOffset >= cacheBlkSize) {
1324        DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache "
1325                "block.\n", tid);
1326    }
1327
1328    macroop[tid] = curMacroop;
1329    fetchOffset[tid] = pcOffset;
1330
1331    if (numInst > 0) {
1332        wroteToTimeBuffer = true;
1333    }
1334
1335    pc[tid] = thisPC;
1336
1337    // pipeline a fetch if we're crossing a cache boundary and not in
1338    // a state that would preclude fetching
1339    fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask;
1340    Addr block_PC = icacheBlockAlignPC(fetchAddr);
1341    issuePipelinedIfetch[tid] = block_PC != cacheDataPC[tid] &&
1342        fetchStatus[tid] != IcacheWaitResponse &&
1343        fetchStatus[tid] != ItlbWait &&
1344        fetchStatus[tid] != IcacheWaitRetry &&
1345        fetchStatus[tid] != QuiescePending &&
1346        !curMacroop;
1347}
1348
1349template<class Impl>
1350void
1351DefaultFetch<Impl>::recvRetry()
1352{
1353    if (retryPkt != NULL) {
1354        assert(cacheBlocked);
1355        assert(retryTid != InvalidThreadID);
1356        assert(fetchStatus[retryTid] == IcacheWaitRetry);
1357
1358        if (cpu->getInstPort().sendTimingReq(retryPkt)) {
1359            fetchStatus[retryTid] = IcacheWaitResponse;
1360            retryPkt = NULL;
1361            retryTid = InvalidThreadID;
1362            cacheBlocked = false;
1363        }
1364    } else {
1365        assert(retryTid == InvalidThreadID);
1366        // Access has been squashed since it was sent out.  Just clear
1367        // the cache being blocked.
1368        cacheBlocked = false;
1369    }
1370}
1371
1372///////////////////////////////////////
1373//                                   //
1374//  SMT FETCH POLICY MAINTAINED HERE //
1375//                                   //
1376///////////////////////////////////////
1377template<class Impl>
1378ThreadID
1379DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority)
1380{
1381    if (numThreads > 1) {
1382        switch (fetch_priority) {
1383
1384          case SingleThread:
1385            return 0;
1386
1387          case RoundRobin:
1388            return roundRobin();
1389
1390          case IQ:
1391            return iqCount();
1392
1393          case LSQ:
1394            return lsqCount();
1395
1396          case Branch:
1397            return branchCount();
1398
1399          default:
1400            return InvalidThreadID;
1401        }
1402    } else {
1403        list<ThreadID>::iterator thread = activeThreads->begin();
1404        if (thread == activeThreads->end()) {
1405            return InvalidThreadID;
1406        }
1407
1408        ThreadID tid = *thread;
1409
1410        if (fetchStatus[tid] == Running ||
1411            fetchStatus[tid] == IcacheAccessComplete ||
1412            fetchStatus[tid] == Idle) {
1413            return tid;
1414        } else {
1415            return InvalidThreadID;
1416        }
1417    }
1418}
1419
1420
1421template<class Impl>
1422ThreadID
1423DefaultFetch<Impl>::roundRobin()
1424{
1425    list<ThreadID>::iterator pri_iter = priorityList.begin();
1426    list<ThreadID>::iterator end      = priorityList.end();
1427
1428    ThreadID high_pri;
1429
1430    while (pri_iter != end) {
1431        high_pri = *pri_iter;
1432
1433        assert(high_pri <= numThreads);
1434
1435        if (fetchStatus[high_pri] == Running ||
1436            fetchStatus[high_pri] == IcacheAccessComplete ||
1437            fetchStatus[high_pri] == Idle) {
1438
1439            priorityList.erase(pri_iter);
1440            priorityList.push_back(high_pri);
1441
1442            return high_pri;
1443        }
1444
1445        pri_iter++;
1446    }
1447
1448    return InvalidThreadID;
1449}
1450
1451template<class Impl>
1452ThreadID
1453DefaultFetch<Impl>::iqCount()
1454{
1455    std::priority_queue<unsigned> PQ;
1456    std::map<unsigned, ThreadID> threadMap;
1457
1458    list<ThreadID>::iterator threads = activeThreads->begin();
1459    list<ThreadID>::iterator end = activeThreads->end();
1460
1461    while (threads != end) {
1462        ThreadID tid = *threads++;
1463        unsigned iqCount = fromIEW->iewInfo[tid].iqCount;
1464
1465        PQ.push(iqCount);
1466        threadMap[iqCount] = tid;
1467    }
1468
1469    while (!PQ.empty()) {
1470        ThreadID high_pri = threadMap[PQ.top()];
1471
1472        if (fetchStatus[high_pri] == Running ||
1473            fetchStatus[high_pri] == IcacheAccessComplete ||
1474            fetchStatus[high_pri] == Idle)
1475            return high_pri;
1476        else
1477            PQ.pop();
1478
1479    }
1480
1481    return InvalidThreadID;
1482}
1483
1484template<class Impl>
1485ThreadID
1486DefaultFetch<Impl>::lsqCount()
1487{
1488    std::priority_queue<unsigned> PQ;
1489    std::map<unsigned, ThreadID> threadMap;
1490
1491    list<ThreadID>::iterator threads = activeThreads->begin();
1492    list<ThreadID>::iterator end = activeThreads->end();
1493
1494    while (threads != end) {
1495        ThreadID tid = *threads++;
1496        unsigned ldstqCount = fromIEW->iewInfo[tid].ldstqCount;
1497
1498        PQ.push(ldstqCount);
1499        threadMap[ldstqCount] = tid;
1500    }
1501
1502    while (!PQ.empty()) {
1503        ThreadID high_pri = threadMap[PQ.top()];
1504
1505        if (fetchStatus[high_pri] == Running ||
1506            fetchStatus[high_pri] == IcacheAccessComplete ||
1507            fetchStatus[high_pri] == Idle)
1508            return high_pri;
1509        else
1510            PQ.pop();
1511    }
1512
1513    return InvalidThreadID;
1514}
1515
1516template<class Impl>
1517ThreadID
1518DefaultFetch<Impl>::branchCount()
1519{
1520#if 0
1521    list<ThreadID>::iterator thread = activeThreads->begin();
1522    assert(thread != activeThreads->end());
1523    ThreadID tid = *thread;
1524#endif
1525
1526    panic("Branch Count Fetch policy unimplemented\n");
1527    return InvalidThreadID;
1528}
1529
1530template<class Impl>
1531void
1532DefaultFetch<Impl>::pipelineIcacheAccesses(ThreadID tid)
1533{
1534    if (!issuePipelinedIfetch[tid]) {
1535        return;
1536    }
1537
1538    // The next PC to access.
1539    TheISA::PCState thisPC = pc[tid];
1540
1541    if (isRomMicroPC(thisPC.microPC())) {
1542        return;
1543    }
1544
1545    Addr pcOffset = fetchOffset[tid];
1546    Addr fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask;
1547
1548    // Align the fetch PC so its at the start of a cache block.
1549    Addr block_PC = icacheBlockAlignPC(fetchAddr);
1550
1551    // Unless buffer already got the block, fetch it from icache.
1552    if (!(cacheDataValid[tid] && block_PC == cacheDataPC[tid])) {
1553        DPRINTF(Fetch, "[tid:%i]: Issuing a pipelined I-cache access, "
1554                "starting at PC %s.\n", tid, thisPC);
1555
1556        fetchCacheLine(fetchAddr, tid, thisPC.instAddr());
1557    }
1558}
1559
1560template<class Impl>
1561void
1562DefaultFetch<Impl>::profileStall(ThreadID tid) {
1563    DPRINTF(Fetch,"There are no more threads available to fetch from.\n");
1564
1565    // @todo Per-thread stats
1566
1567    if (drainPending) {
1568        ++fetchPendingDrainCycles;
1569        DPRINTF(Fetch, "Fetch is waiting for a drain!\n");
1570    } else if (activeThreads->empty()) {
1571        ++fetchNoActiveThreadStallCycles;
1572        DPRINTF(Fetch, "Fetch has no active thread!\n");
1573    } else if (fetchStatus[tid] == Blocked) {
1574        ++fetchBlockedCycles;
1575        DPRINTF(Fetch, "[tid:%i]: Fetch is blocked!\n", tid);
1576    } else if (fetchStatus[tid] == Squashing) {
1577        ++fetchSquashCycles;
1578        DPRINTF(Fetch, "[tid:%i]: Fetch is squashing!\n", tid);
1579    } else if (fetchStatus[tid] == IcacheWaitResponse) {
1580        ++icacheStallCycles;
1581        DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n",
1582                tid);
1583    } else if (fetchStatus[tid] == ItlbWait) {
1584        ++fetchTlbCycles;
1585        DPRINTF(Fetch, "[tid:%i]: Fetch is waiting ITLB walk to "
1586                "finish!\n", tid);
1587    } else if (fetchStatus[tid] == TrapPending) {
1588        ++fetchPendingTrapStallCycles;
1589        DPRINTF(Fetch, "[tid:%i]: Fetch is waiting for a pending trap!\n",
1590                tid);
1591    } else if (fetchStatus[tid] == QuiescePending) {
1592        ++fetchPendingQuiesceStallCycles;
1593        DPRINTF(Fetch, "[tid:%i]: Fetch is waiting for a pending quiesce "
1594                "instruction!\n", tid);
1595    } else if (fetchStatus[tid] == IcacheWaitRetry) {
1596        ++fetchIcacheWaitRetryStallCycles;
1597        DPRINTF(Fetch, "[tid:%i]: Fetch is waiting for an I-cache retry!\n",
1598                tid);
1599    } else if (fetchStatus[tid] == NoGoodAddr) {
1600            DPRINTF(Fetch, "[tid:%i]: Fetch predicted non-executable address\n",
1601                    tid);
1602    } else {
1603        DPRINTF(Fetch, "[tid:%i]: Unexpected fetch stall reason (Status: %i).\n",
1604             tid, fetchStatus[tid]);
1605    }
1606}
1607