fetch_impl.hh revision 8821:bba1a976c293
112272SGeoffrey.Blake@arm.com/* 212272SGeoffrey.Blake@arm.com * Copyright (c) 2010-2011 ARM Limited 312272SGeoffrey.Blake@arm.com * All rights reserved. 412272SGeoffrey.Blake@arm.com * 512272SGeoffrey.Blake@arm.com * The license below extends only to copyright in the software and shall 612272SGeoffrey.Blake@arm.com * not be construed as granting a license to any other intellectual 712272SGeoffrey.Blake@arm.com * property including but not limited to intellectual property relating 812272SGeoffrey.Blake@arm.com * to a hardware implementation of the functionality of the software 912272SGeoffrey.Blake@arm.com * licensed hereunder. You may use the software subject to the license 1012272SGeoffrey.Blake@arm.com * terms below provided that you ensure that this notice is replicated 1112272SGeoffrey.Blake@arm.com * unmodified and in its entirety in all distributions of the software, 1212272SGeoffrey.Blake@arm.com * modified or unmodified, in source code or in binary form. 134486Sbinkertn@umich.edu * 147897Shestness@cs.utexas.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 154486Sbinkertn@umich.edu * All rights reserved. 164486Sbinkertn@umich.edu * 174486Sbinkertn@umich.edu * Redistribution and use in source and binary forms, with or without 184486Sbinkertn@umich.edu * modification, are permitted provided that the following conditions are 194486Sbinkertn@umich.edu * met: redistributions of source code must retain the above copyright 204486Sbinkertn@umich.edu * notice, this list of conditions and the following disclaimer; 214486Sbinkertn@umich.edu * redistributions in binary form must reproduce the above copyright 224486Sbinkertn@umich.edu * notice, this list of conditions and the following disclaimer in the 234486Sbinkertn@umich.edu * documentation and/or other materials provided with the distribution; 244486Sbinkertn@umich.edu * neither the name of the copyright holders nor the names of its 254486Sbinkertn@umich.edu * contributors may be used to endorse or promote products derived from 264486Sbinkertn@umich.edu * this software without specific prior written permission. 274486Sbinkertn@umich.edu * 284486Sbinkertn@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 294486Sbinkertn@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 304486Sbinkertn@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 314486Sbinkertn@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 324486Sbinkertn@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 334486Sbinkertn@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 344486Sbinkertn@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 354486Sbinkertn@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 364486Sbinkertn@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 374486Sbinkertn@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 384486Sbinkertn@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 394486Sbinkertn@umich.edu * 404486Sbinkertn@umich.edu * Authors: Kevin Lim 417897Shestness@cs.utexas.edu * Korey Sewell 424486Sbinkertn@umich.edu */ 4311988Sandreas.sandberg@arm.com 4411839SCurtis.Dunham@arm.com#include <algorithm> 453102SN/A#include <cstring> 463102SN/A#include <list> 476654Snate@binkert.org#include <map> 4813665Sandreas.sandberg@arm.com#include <queue> 4913665Sandreas.sandberg@arm.com 502212SN/A#include "arch/isa_traits.hh" 519524SAndreas.Sandberg@ARM.com#include "arch/tlb.hh" 529524SAndreas.Sandberg@ARM.com#include "arch/utility.hh" 532902SN/A#include "arch/vtophys.hh" 548703Sandreas.hansson@arm.com#include "base/types.hh" 551783SN/A#include "config/the_isa.hh" 569338SAndreas.Sandberg@arm.com#include "config/use_checker.hh" 578839Sandreas.hansson@arm.com#include "cpu/base.hh" 587673Snate@binkert.org#include "cpu/o3/fetch.hh" 5911988Sandreas.sandberg@arm.com#include "cpu/exetrace.hh" 6011988Sandreas.sandberg@arm.com#include "debug/Activity.hh" 6111988Sandreas.sandberg@arm.com#include "debug/Fetch.hh" 6211988Sandreas.sandberg@arm.com#include "mem/packet.hh" 634859Snate@binkert.org#include "mem/request.hh" 648931Sandreas.hansson@arm.com#include "params/DerivO3CPU.hh" 658931Sandreas.hansson@arm.com#include "sim/byteswap.hh" 662902SN/A#include "sim/core.hh" 679408Sandreas.hansson@arm.com#include "sim/eventq.hh" 6811420Sdavid.guillen@arm.com#include "sim/full_system.hh" 6911420Sdavid.guillen@arm.com#include "sim/system.hh" 7011420Sdavid.guillen@arm.com 7111420Sdavid.guillen@arm.com#if USE_CHECKER 7210700Sandreas.hansson@arm.com#include "cpu/checker/cpu.hh" 7310700Sandreas.hansson@arm.com#endif // USE_CHECKER 7411838SCurtis.Dunham@arm.com 7510700Sandreas.hansson@arm.comusing namespace std; 7610700Sandreas.hansson@arm.com 7710700Sandreas.hansson@arm.comtemplate<class Impl> 7810700Sandreas.hansson@arm.comDefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params) 799408Sandreas.hansson@arm.com : cpu(_cpu), 809408Sandreas.hansson@arm.com branchPred(params), 819408Sandreas.hansson@arm.com predecoder(NULL), 829408Sandreas.hansson@arm.com numInst(0), 839408Sandreas.hansson@arm.com decodeToFetchDelay(params->decodeToFetchDelay), 849814Sandreas.hansson@arm.com renameToFetchDelay(params->renameToFetchDelay), 859814Sandreas.hansson@arm.com iewToFetchDelay(params->iewToFetchDelay), 8613883Sdavid.hashe@amd.com commitToFetchDelay(params->commitToFetchDelay), 8713883Sdavid.hashe@amd.com fetchWidth(params->fetchWidth), 8811273Sandreas.sandberg@arm.com cacheBlocked(false), 8911270Sandreas.sandberg@arm.com retryPkt(NULL), 907914SBrad.Beckmann@amd.com retryTid(InvalidThreadID), 918666SPrakash.Ramrakhyani@arm.com numThreads(params->numThreads), 927914SBrad.Beckmann@amd.com numFetchingThreads(params->smtNumFetchingThreads), 937914SBrad.Beckmann@amd.com interruptPending(false), 947914SBrad.Beckmann@amd.com drainPending(false), 957914SBrad.Beckmann@amd.com switchedOut(false), 967914SBrad.Beckmann@amd.com finishTranslationEvent(this) 977914SBrad.Beckmann@amd.com{ 987914SBrad.Beckmann@amd.com if (numThreads > Impl::MaxThreads) 997914SBrad.Beckmann@amd.com fatal("numThreads (%d) is larger than compiled limit (%d),\n" 1007914SBrad.Beckmann@amd.com "\tincrease MaxThreads in src/cpu/o3/impl.hh\n", 1017914SBrad.Beckmann@amd.com numThreads, static_cast<int>(Impl::MaxThreads)); 1027914SBrad.Beckmann@amd.com 1037914SBrad.Beckmann@amd.com // Set fetch stage's status to inactive. 1047914SBrad.Beckmann@amd.com _status = Inactive; 1058769Sgblack@eecs.umich.edu 1068769Sgblack@eecs.umich.edu std::string policy = params->smtFetchPolicy; 1078769Sgblack@eecs.umich.edu 10810282Sdam.sunwoo@arm.com // Convert string to lowercase 10910282Sdam.sunwoo@arm.com std::transform(policy.begin(), policy.end(), policy.begin(), 11012262Sandreas.sandberg@arm.com (int(*)(int)) tolower); 1118769Sgblack@eecs.umich.edu 1128769Sgblack@eecs.umich.edu // Figure out fetch policy 11312272SGeoffrey.Blake@arm.com if (policy == "singlethread") { 11412272SGeoffrey.Blake@arm.com fetchPolicy = SingleThread; 11512272SGeoffrey.Blake@arm.com if (numThreads > 1) 11612272SGeoffrey.Blake@arm.com panic("Invalid Fetch Policy for a SMT workload."); 11710037SARM gem5 Developers } else if (policy == "roundrobin") { 11810249Sstephan.diestelhorst@arm.com fetchPolicy = RoundRobin; 11911146Smitch.hayenga@arm.com DPRINTF(Fetch, "Fetch policy set to Round Robin\n"); 12011146Smitch.hayenga@arm.com } else if (policy == "branch") { 12111146Smitch.hayenga@arm.com fetchPolicy = Branch; 12210249Sstephan.diestelhorst@arm.com DPRINTF(Fetch, "Fetch policy set to Branch Count\n"); 12310249Sstephan.diestelhorst@arm.com } else if (policy == "iqcount") { 12410249Sstephan.diestelhorst@arm.com fetchPolicy = IQ; 12511839SCurtis.Dunham@arm.com DPRINTF(Fetch, "Fetch policy set to IQ count\n"); 12611839SCurtis.Dunham@arm.com } else if (policy == "lsqcount") { 12711839SCurtis.Dunham@arm.com fetchPolicy = LSQ; 128 DPRINTF(Fetch, "Fetch policy set to LSQ count\n"); 129 } else { 130 fatal("Invalid Fetch Policy. Options Are: {SingleThread," 131 " RoundRobin,LSQcount,IQcount}\n"); 132 } 133 134 // Get the size of an instruction. 135 instSize = sizeof(TheISA::MachInst); 136} 137 138template <class Impl> 139std::string 140DefaultFetch<Impl>::name() const 141{ 142 return cpu->name() + ".fetch"; 143} 144 145template <class Impl> 146void 147DefaultFetch<Impl>::regStats() 148{ 149 icacheStallCycles 150 .name(name() + ".icacheStallCycles") 151 .desc("Number of cycles fetch is stalled on an Icache miss") 152 .prereq(icacheStallCycles); 153 154 fetchedInsts 155 .name(name() + ".Insts") 156 .desc("Number of instructions fetch has processed") 157 .prereq(fetchedInsts); 158 159 fetchedBranches 160 .name(name() + ".Branches") 161 .desc("Number of branches that fetch encountered") 162 .prereq(fetchedBranches); 163 164 predictedBranches 165 .name(name() + ".predictedBranches") 166 .desc("Number of branches that fetch has predicted taken") 167 .prereq(predictedBranches); 168 169 fetchCycles 170 .name(name() + ".Cycles") 171 .desc("Number of cycles fetch has run and was not squashing or" 172 " blocked") 173 .prereq(fetchCycles); 174 175 fetchSquashCycles 176 .name(name() + ".SquashCycles") 177 .desc("Number of cycles fetch has spent squashing") 178 .prereq(fetchSquashCycles); 179 180 fetchTlbCycles 181 .name(name() + ".TlbCycles") 182 .desc("Number of cycles fetch has spent waiting for tlb") 183 .prereq(fetchTlbCycles); 184 185 fetchIdleCycles 186 .name(name() + ".IdleCycles") 187 .desc("Number of cycles fetch was idle") 188 .prereq(fetchIdleCycles); 189 190 fetchBlockedCycles 191 .name(name() + ".BlockedCycles") 192 .desc("Number of cycles fetch has spent blocked") 193 .prereq(fetchBlockedCycles); 194 195 fetchedCacheLines 196 .name(name() + ".CacheLines") 197 .desc("Number of cache lines fetched") 198 .prereq(fetchedCacheLines); 199 200 fetchMiscStallCycles 201 .name(name() + ".MiscStallCycles") 202 .desc("Number of cycles fetch has spent waiting on interrupts, or " 203 "bad addresses, or out of MSHRs") 204 .prereq(fetchMiscStallCycles); 205 206 fetchPendingDrainCycles 207 .name(name() + ".PendingDrainCycles") 208 .desc("Number of cycles fetch has spent waiting on pipes to drain") 209 .prereq(fetchPendingDrainCycles); 210 211 fetchNoActiveThreadStallCycles 212 .name(name() + ".NoActiveThreadStallCycles") 213 .desc("Number of stall cycles due to no active thread to fetch from") 214 .prereq(fetchNoActiveThreadStallCycles); 215 216 fetchPendingTrapStallCycles 217 .name(name() + ".PendingTrapStallCycles") 218 .desc("Number of stall cycles due to pending traps") 219 .prereq(fetchPendingTrapStallCycles); 220 221 fetchPendingQuiesceStallCycles 222 .name(name() + ".PendingQuiesceStallCycles") 223 .desc("Number of stall cycles due to pending quiesce instructions") 224 .prereq(fetchPendingQuiesceStallCycles); 225 226 fetchIcacheWaitRetryStallCycles 227 .name(name() + ".IcacheWaitRetryStallCycles") 228 .desc("Number of stall cycles due to full MSHR") 229 .prereq(fetchIcacheWaitRetryStallCycles); 230 231 fetchIcacheSquashes 232 .name(name() + ".IcacheSquashes") 233 .desc("Number of outstanding Icache misses that were squashed") 234 .prereq(fetchIcacheSquashes); 235 236 fetchTlbSquashes 237 .name(name() + ".ItlbSquashes") 238 .desc("Number of outstanding ITLB misses that were squashed") 239 .prereq(fetchTlbSquashes); 240 241 fetchNisnDist 242 .init(/* base value */ 0, 243 /* last value */ fetchWidth, 244 /* bucket size */ 1) 245 .name(name() + ".rateDist") 246 .desc("Number of instructions fetched each cycle (Total)") 247 .flags(Stats::pdf); 248 249 idleRate 250 .name(name() + ".idleRate") 251 .desc("Percent of cycles fetch was idle") 252 .prereq(idleRate); 253 idleRate = fetchIdleCycles * 100 / cpu->numCycles; 254 255 branchRate 256 .name(name() + ".branchRate") 257 .desc("Number of branch fetches per cycle") 258 .flags(Stats::total); 259 branchRate = fetchedBranches / cpu->numCycles; 260 261 fetchRate 262 .name(name() + ".rate") 263 .desc("Number of inst fetches per cycle") 264 .flags(Stats::total); 265 fetchRate = fetchedInsts / cpu->numCycles; 266 267 branchPred.regStats(); 268} 269 270template<class Impl> 271void 272DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer) 273{ 274 timeBuffer = time_buffer; 275 276 // Create wires to get information from proper places in time buffer. 277 fromDecode = timeBuffer->getWire(-decodeToFetchDelay); 278 fromRename = timeBuffer->getWire(-renameToFetchDelay); 279 fromIEW = timeBuffer->getWire(-iewToFetchDelay); 280 fromCommit = timeBuffer->getWire(-commitToFetchDelay); 281} 282 283template<class Impl> 284void 285DefaultFetch<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr) 286{ 287 activeThreads = at_ptr; 288} 289 290template<class Impl> 291void 292DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 293{ 294 fetchQueue = fq_ptr; 295 296 // Create wire to write information to proper place in fetch queue. 297 toDecode = fetchQueue->getWire(0); 298} 299 300template<class Impl> 301void 302DefaultFetch<Impl>::initStage() 303{ 304 // Setup PC and nextPC with initial state. 305 for (ThreadID tid = 0; tid < numThreads; tid++) { 306 pc[tid] = cpu->pcState(tid); 307 fetchOffset[tid] = 0; 308 macroop[tid] = NULL; 309 delayedCommit[tid] = false; 310 } 311 312 for (ThreadID tid = 0; tid < numThreads; tid++) { 313 314 fetchStatus[tid] = Running; 315 316 priorityList.push_back(tid); 317 318 memReq[tid] = NULL; 319 320 stalls[tid].decode = false; 321 stalls[tid].rename = false; 322 stalls[tid].iew = false; 323 stalls[tid].commit = false; 324 } 325 326 // Schedule fetch to get the correct PC from the CPU 327 // scheduleFetchStartupEvent(1); 328 329 // Fetch needs to start fetching instructions at the very beginning, 330 // so it must start up in active state. 331 switchToActive(); 332} 333 334template<class Impl> 335void 336DefaultFetch<Impl>::setIcache() 337{ 338 assert(cpu->getIcachePort()->isConnected()); 339 340 // Size of cache block. 341 cacheBlkSize = cpu->getIcachePort()->peerBlockSize(); 342 343 // Create mask to get rid of offset bits. 344 cacheBlkMask = (cacheBlkSize - 1); 345 346 for (ThreadID tid = 0; tid < numThreads; tid++) { 347 // Create space to store a cache line. 348 cacheData[tid] = new uint8_t[cacheBlkSize]; 349 cacheDataPC[tid] = 0; 350 cacheDataValid[tid] = false; 351 } 352} 353 354template<class Impl> 355void 356DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt) 357{ 358 ThreadID tid = pkt->req->threadId(); 359 360 DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n", tid); 361 362 assert(!pkt->wasNacked()); 363 364 // Only change the status if it's still waiting on the icache access 365 // to return. 366 if (fetchStatus[tid] != IcacheWaitResponse || 367 pkt->req != memReq[tid] || 368 isSwitchedOut()) { 369 ++fetchIcacheSquashes; 370 delete pkt->req; 371 delete pkt; 372 return; 373 } 374 375 memcpy(cacheData[tid], pkt->getPtr<uint8_t>(), cacheBlkSize); 376 cacheDataValid[tid] = true; 377 378 if (!drainPending) { 379 // Wake up the CPU (if it went to sleep and was waiting on 380 // this completion event). 381 cpu->wakeCPU(); 382 383 DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n", 384 tid); 385 386 switchToActive(); 387 } 388 389 // Only switch to IcacheAccessComplete if we're not stalled as well. 390 if (checkStall(tid)) { 391 fetchStatus[tid] = Blocked; 392 } else { 393 fetchStatus[tid] = IcacheAccessComplete; 394 } 395 396 // Reset the mem req to NULL. 397 delete pkt->req; 398 delete pkt; 399 memReq[tid] = NULL; 400} 401 402template <class Impl> 403bool 404DefaultFetch<Impl>::drain() 405{ 406 // Fetch is ready to drain at any time. 407 cpu->signalDrained(); 408 drainPending = true; 409 return true; 410} 411 412template <class Impl> 413void 414DefaultFetch<Impl>::resume() 415{ 416 drainPending = false; 417} 418 419template <class Impl> 420void 421DefaultFetch<Impl>::switchOut() 422{ 423 switchedOut = true; 424 // Branch predictor needs to have its state cleared. 425 branchPred.switchOut(); 426} 427 428template <class Impl> 429void 430DefaultFetch<Impl>::takeOverFrom() 431{ 432 // the instruction port is now connected so we can get the block 433 // size 434 setIcache(); 435 436 // Reset all state 437 for (ThreadID i = 0; i < Impl::MaxThreads; ++i) { 438 stalls[i].decode = 0; 439 stalls[i].rename = 0; 440 stalls[i].iew = 0; 441 stalls[i].commit = 0; 442 pc[i] = cpu->pcState(i); 443 fetchStatus[i] = Running; 444 } 445 numInst = 0; 446 wroteToTimeBuffer = false; 447 _status = Inactive; 448 switchedOut = false; 449 interruptPending = false; 450 branchPred.takeOverFrom(); 451} 452 453template <class Impl> 454void 455DefaultFetch<Impl>::wakeFromQuiesce() 456{ 457 DPRINTF(Fetch, "Waking up from quiesce\n"); 458 // Hopefully this is safe 459 // @todo: Allow other threads to wake from quiesce. 460 fetchStatus[0] = Running; 461} 462 463template <class Impl> 464inline void 465DefaultFetch<Impl>::switchToActive() 466{ 467 if (_status == Inactive) { 468 DPRINTF(Activity, "Activating stage.\n"); 469 470 cpu->activateStage(O3CPU::FetchIdx); 471 472 _status = Active; 473 } 474} 475 476template <class Impl> 477inline void 478DefaultFetch<Impl>::switchToInactive() 479{ 480 if (_status == Active) { 481 DPRINTF(Activity, "Deactivating stage.\n"); 482 483 cpu->deactivateStage(O3CPU::FetchIdx); 484 485 _status = Inactive; 486 } 487} 488 489template <class Impl> 490bool 491DefaultFetch<Impl>::lookupAndUpdateNextPC( 492 DynInstPtr &inst, TheISA::PCState &nextPC) 493{ 494 // Do branch prediction check here. 495 // A bit of a misnomer...next_PC is actually the current PC until 496 // this function updates it. 497 bool predict_taken; 498 499 if (!inst->isControl()) { 500 TheISA::advancePC(nextPC, inst->staticInst); 501 inst->setPredTarg(nextPC); 502 inst->setPredTaken(false); 503 return false; 504 } 505 506 ThreadID tid = inst->threadNumber; 507 predict_taken = branchPred.predict(inst, nextPC, tid); 508 509 if (predict_taken) { 510 DPRINTF(Fetch, "[tid:%i]: [sn:%i]: Branch predicted to be taken to %s.\n", 511 tid, inst->seqNum, nextPC); 512 } else { 513 DPRINTF(Fetch, "[tid:%i]: [sn:%i]:Branch predicted to be not taken.\n", 514 tid, inst->seqNum); 515 } 516 517 DPRINTF(Fetch, "[tid:%i]: [sn:%i] Branch predicted to go to %s.\n", 518 tid, inst->seqNum, nextPC); 519 inst->setPredTarg(nextPC); 520 inst->setPredTaken(predict_taken); 521 522 ++fetchedBranches; 523 524 if (predict_taken) { 525 ++predictedBranches; 526 } 527 528 return predict_taken; 529} 530 531template <class Impl> 532bool 533DefaultFetch<Impl>::fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc) 534{ 535 Fault fault = NoFault; 536 537 // @todo: not sure if these should block translation. 538 //AlphaDep 539 if (cacheBlocked) { 540 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n", 541 tid); 542 return false; 543 } else if (isSwitchedOut()) { 544 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, switched out\n", 545 tid); 546 return false; 547 } else if (checkInterrupt(pc)) { 548 // Hold off fetch from getting new instructions when: 549 // Cache is blocked, or 550 // while an interrupt is pending and we're not in PAL mode, or 551 // fetch is switched out. 552 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n", 553 tid); 554 return false; 555 } 556 557 // Align the fetch address so it's at the start of a cache block. 558 Addr block_PC = icacheBlockAlignPC(vaddr); 559 560 DPRINTF(Fetch, "[tid:%i] Fetching cache line %#x for addr %#x\n", 561 tid, block_PC, vaddr); 562 563 // Setup the memReq to do a read of the first instruction's address. 564 // Set the appropriate read size and flags as well. 565 // Build request here. 566 RequestPtr mem_req = 567 new Request(tid, block_PC, cacheBlkSize, Request::INST_FETCH, 568 pc, cpu->thread[tid]->contextId(), tid); 569 570 memReq[tid] = mem_req; 571 572 // Initiate translation of the icache block 573 fetchStatus[tid] = ItlbWait; 574 FetchTranslation *trans = new FetchTranslation(this); 575 cpu->itb->translateTiming(mem_req, cpu->thread[tid]->getTC(), 576 trans, BaseTLB::Execute); 577 return true; 578} 579 580template <class Impl> 581void 582DefaultFetch<Impl>::finishTranslation(Fault fault, RequestPtr mem_req) 583{ 584 ThreadID tid = mem_req->threadId(); 585 Addr block_PC = mem_req->getVaddr(); 586 587 // Wake up CPU if it was idle 588 cpu->wakeCPU(); 589 590 if (fetchStatus[tid] != ItlbWait || mem_req != memReq[tid] || 591 mem_req->getVaddr() != memReq[tid]->getVaddr() || isSwitchedOut()) { 592 DPRINTF(Fetch, "[tid:%i] Ignoring itlb completed after squash\n", 593 tid); 594 ++fetchTlbSquashes; 595 delete mem_req; 596 return; 597 } 598 599 600 // If translation was successful, attempt to read the icache block. 601 if (fault == NoFault) { 602 // Check that we're not going off into random memory 603 // If we have, just wait around for commit to squash something and put 604 // us on the right track 605 if (!cpu->system->isMemory(mem_req->getPaddr())) { 606 warn("Address %#x is outside of physical memory, stopping fetch\n", 607 mem_req->getPaddr()); 608 fetchStatus[tid] = NoGoodAddr; 609 delete mem_req; 610 memReq[tid] = NULL; 611 return; 612 } 613 614 // Build packet here. 615 PacketPtr data_pkt = new Packet(mem_req, 616 MemCmd::ReadReq, Packet::Broadcast); 617 data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]); 618 619 cacheDataPC[tid] = block_PC; 620 cacheDataValid[tid] = false; 621 DPRINTF(Fetch, "Fetch: Doing instruction read.\n"); 622 623 fetchedCacheLines++; 624 625 // Access the cache. 626 if (!cpu->getIcachePort()->sendTiming(data_pkt)) { 627 assert(retryPkt == NULL); 628 assert(retryTid == InvalidThreadID); 629 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid); 630 631 fetchStatus[tid] = IcacheWaitRetry; 632 retryPkt = data_pkt; 633 retryTid = tid; 634 cacheBlocked = true; 635 } else { 636 DPRINTF(Fetch, "[tid:%i]: Doing Icache access.\n", tid); 637 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache " 638 "response.\n", tid); 639 640 lastIcacheStall[tid] = curTick(); 641 fetchStatus[tid] = IcacheWaitResponse; 642 } 643 } else { 644 if (!(numInst < fetchWidth)) { 645 assert(!finishTranslationEvent.scheduled()); 646 finishTranslationEvent.setFault(fault); 647 finishTranslationEvent.setReq(mem_req); 648 cpu->schedule(finishTranslationEvent, cpu->nextCycle(curTick() + cpu->ticks(1))); 649 return; 650 } 651 DPRINTF(Fetch, "[tid:%i] Got back req with addr %#x but expected %#x\n", 652 tid, mem_req->getVaddr(), memReq[tid]->getVaddr()); 653 // Translation faulted, icache request won't be sent. 654 delete mem_req; 655 memReq[tid] = NULL; 656 657 // Send the fault to commit. This thread will not do anything 658 // until commit handles the fault. The only other way it can 659 // wake up is if a squash comes along and changes the PC. 660 TheISA::PCState fetchPC = pc[tid]; 661 662 DPRINTF(Fetch, "[tid:%i]: Translation faulted, building noop.\n", tid); 663 // We will use a nop in ordier to carry the fault. 664 DynInstPtr instruction = buildInst(tid, 665 decoder.decode(TheISA::NoopMachInst, fetchPC.instAddr()), 666 NULL, fetchPC, fetchPC, false); 667 668 instruction->setPredTarg(fetchPC); 669 instruction->fault = fault; 670 wroteToTimeBuffer = true; 671 672 DPRINTF(Activity, "Activity this cycle.\n"); 673 cpu->activityThisCycle(); 674 675 fetchStatus[tid] = TrapPending; 676 677 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n", tid); 678 DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %s.\n", 679 tid, fault->name(), pc[tid]); 680 } 681 _status = updateFetchStatus(); 682} 683 684template <class Impl> 685inline void 686DefaultFetch<Impl>::doSquash(const TheISA::PCState &newPC, 687 const DynInstPtr squashInst, ThreadID tid) 688{ 689 DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %s.\n", 690 tid, newPC); 691 692 pc[tid] = newPC; 693 fetchOffset[tid] = 0; 694 if (squashInst && squashInst->pcState().instAddr() == newPC.instAddr()) 695 macroop[tid] = squashInst->macroop; 696 else 697 macroop[tid] = NULL; 698 predecoder.reset(); 699 700 // Clear the icache miss if it's outstanding. 701 if (fetchStatus[tid] == IcacheWaitResponse) { 702 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n", 703 tid); 704 memReq[tid] = NULL; 705 } else if (fetchStatus[tid] == ItlbWait) { 706 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding ITLB miss.\n", 707 tid); 708 memReq[tid] = NULL; 709 } 710 711 // Get rid of the retrying packet if it was from this thread. 712 if (retryTid == tid) { 713 assert(cacheBlocked); 714 if (retryPkt) { 715 delete retryPkt->req; 716 delete retryPkt; 717 } 718 retryPkt = NULL; 719 retryTid = InvalidThreadID; 720 } 721 722 fetchStatus[tid] = Squashing; 723 724 ++fetchSquashCycles; 725} 726 727template<class Impl> 728void 729DefaultFetch<Impl>::squashFromDecode(const TheISA::PCState &newPC, 730 const DynInstPtr squashInst, 731 const InstSeqNum seq_num, ThreadID tid) 732{ 733 DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n", tid); 734 735 doSquash(newPC, squashInst, tid); 736 737 // Tell the CPU to remove any instructions that are in flight between 738 // fetch and decode. 739 cpu->removeInstsUntil(seq_num, tid); 740} 741 742template<class Impl> 743bool 744DefaultFetch<Impl>::checkStall(ThreadID tid) const 745{ 746 bool ret_val = false; 747 748 if (cpu->contextSwitch) { 749 DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid); 750 ret_val = true; 751 } else if (stalls[tid].decode) { 752 DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid); 753 ret_val = true; 754 } else if (stalls[tid].rename) { 755 DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid); 756 ret_val = true; 757 } else if (stalls[tid].iew) { 758 DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid); 759 ret_val = true; 760 } else if (stalls[tid].commit) { 761 DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid); 762 ret_val = true; 763 } 764 765 return ret_val; 766} 767 768template<class Impl> 769typename DefaultFetch<Impl>::FetchStatus 770DefaultFetch<Impl>::updateFetchStatus() 771{ 772 //Check Running 773 list<ThreadID>::iterator threads = activeThreads->begin(); 774 list<ThreadID>::iterator end = activeThreads->end(); 775 776 while (threads != end) { 777 ThreadID tid = *threads++; 778 779 if (fetchStatus[tid] == Running || 780 fetchStatus[tid] == Squashing || 781 fetchStatus[tid] == IcacheAccessComplete) { 782 783 if (_status == Inactive) { 784 DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid); 785 786 if (fetchStatus[tid] == IcacheAccessComplete) { 787 DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache" 788 "completion\n",tid); 789 } 790 791 cpu->activateStage(O3CPU::FetchIdx); 792 } 793 794 return Active; 795 } 796 } 797 798 // Stage is switching from active to inactive, notify CPU of it. 799 if (_status == Active) { 800 DPRINTF(Activity, "Deactivating stage.\n"); 801 802 cpu->deactivateStage(O3CPU::FetchIdx); 803 } 804 805 return Inactive; 806} 807 808template <class Impl> 809void 810DefaultFetch<Impl>::squash(const TheISA::PCState &newPC, 811 const InstSeqNum seq_num, DynInstPtr squashInst, 812 ThreadID tid) 813{ 814 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n", tid); 815 816 doSquash(newPC, squashInst, tid); 817 818 // Tell the CPU to remove any instructions that are not in the ROB. 819 cpu->removeInstsNotInROB(tid); 820} 821 822template <class Impl> 823void 824DefaultFetch<Impl>::tick() 825{ 826 list<ThreadID>::iterator threads = activeThreads->begin(); 827 list<ThreadID>::iterator end = activeThreads->end(); 828 bool status_change = false; 829 830 wroteToTimeBuffer = false; 831 832 for (ThreadID i = 0; i < Impl::MaxThreads; ++i) { 833 issuePipelinedIfetch[i] = false; 834 } 835 836 while (threads != end) { 837 ThreadID tid = *threads++; 838 839 // Check the signals for each thread to determine the proper status 840 // for each thread. 841 bool updated_status = checkSignalsAndUpdate(tid); 842 status_change = status_change || updated_status; 843 } 844 845 DPRINTF(Fetch, "Running stage.\n"); 846 847 if (FullSystem) { 848 if (fromCommit->commitInfo[0].interruptPending) { 849 interruptPending = true; 850 } 851 852 if (fromCommit->commitInfo[0].clearInterrupt) { 853 interruptPending = false; 854 } 855 } 856 857 for (threadFetched = 0; threadFetched < numFetchingThreads; 858 threadFetched++) { 859 // Fetch each of the actively fetching threads. 860 fetch(status_change); 861 } 862 863 // Record number of instructions fetched this cycle for distribution. 864 fetchNisnDist.sample(numInst); 865 866 if (status_change) { 867 // Change the fetch stage status if there was a status change. 868 _status = updateFetchStatus(); 869 } 870 871 // If there was activity this cycle, inform the CPU of it. 872 if (wroteToTimeBuffer || cpu->contextSwitch) { 873 DPRINTF(Activity, "Activity this cycle.\n"); 874 875 cpu->activityThisCycle(); 876 } 877 878 // Issue the next I-cache request if possible. 879 for (ThreadID i = 0; i < Impl::MaxThreads; ++i) { 880 if (issuePipelinedIfetch[i]) { 881 pipelineIcacheAccesses(i); 882 } 883 } 884 885 // Reset the number of the instruction we've fetched. 886 numInst = 0; 887} 888 889template <class Impl> 890bool 891DefaultFetch<Impl>::checkSignalsAndUpdate(ThreadID tid) 892{ 893 // Update the per thread stall statuses. 894 if (fromDecode->decodeBlock[tid]) { 895 stalls[tid].decode = true; 896 } 897 898 if (fromDecode->decodeUnblock[tid]) { 899 assert(stalls[tid].decode); 900 assert(!fromDecode->decodeBlock[tid]); 901 stalls[tid].decode = false; 902 } 903 904 if (fromRename->renameBlock[tid]) { 905 stalls[tid].rename = true; 906 } 907 908 if (fromRename->renameUnblock[tid]) { 909 assert(stalls[tid].rename); 910 assert(!fromRename->renameBlock[tid]); 911 stalls[tid].rename = false; 912 } 913 914 if (fromIEW->iewBlock[tid]) { 915 stalls[tid].iew = true; 916 } 917 918 if (fromIEW->iewUnblock[tid]) { 919 assert(stalls[tid].iew); 920 assert(!fromIEW->iewBlock[tid]); 921 stalls[tid].iew = false; 922 } 923 924 if (fromCommit->commitBlock[tid]) { 925 stalls[tid].commit = true; 926 } 927 928 if (fromCommit->commitUnblock[tid]) { 929 assert(stalls[tid].commit); 930 assert(!fromCommit->commitBlock[tid]); 931 stalls[tid].commit = false; 932 } 933 934 // Check squash signals from commit. 935 if (fromCommit->commitInfo[tid].squash) { 936 937 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash " 938 "from commit.\n",tid); 939 // In any case, squash. 940 squash(fromCommit->commitInfo[tid].pc, 941 fromCommit->commitInfo[tid].doneSeqNum, 942 fromCommit->commitInfo[tid].squashInst, tid); 943 944 // If it was a branch mispredict on a control instruction, update the 945 // branch predictor with that instruction, otherwise just kill the 946 // invalid state we generated in after sequence number 947 if (fromCommit->commitInfo[tid].mispredictInst && 948 fromCommit->commitInfo[tid].mispredictInst->isControl()) { 949 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum, 950 fromCommit->commitInfo[tid].pc, 951 fromCommit->commitInfo[tid].branchTaken, 952 tid); 953 } else { 954 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum, 955 tid); 956 } 957 958 return true; 959 } else if (fromCommit->commitInfo[tid].doneSeqNum) { 960 // Update the branch predictor if it wasn't a squashed instruction 961 // that was broadcasted. 962 branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid); 963 } 964 965 // Check ROB squash signals from commit. 966 if (fromCommit->commitInfo[tid].robSquashing) { 967 DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid); 968 969 // Continue to squash. 970 fetchStatus[tid] = Squashing; 971 972 return true; 973 } 974 975 // Check squash signals from decode. 976 if (fromDecode->decodeInfo[tid].squash) { 977 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash " 978 "from decode.\n",tid); 979 980 // Update the branch predictor. 981 if (fromDecode->decodeInfo[tid].branchMispredict) { 982 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum, 983 fromDecode->decodeInfo[tid].nextPC, 984 fromDecode->decodeInfo[tid].branchTaken, 985 tid); 986 } else { 987 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum, 988 tid); 989 } 990 991 if (fetchStatus[tid] != Squashing) { 992 993 DPRINTF(Fetch, "Squashing from decode with PC = %s\n", 994 fromDecode->decodeInfo[tid].nextPC); 995 // Squash unless we're already squashing 996 squashFromDecode(fromDecode->decodeInfo[tid].nextPC, 997 fromDecode->decodeInfo[tid].squashInst, 998 fromDecode->decodeInfo[tid].doneSeqNum, 999 tid); 1000 1001 return true; 1002 } 1003 } 1004 1005 if (checkStall(tid) && 1006 fetchStatus[tid] != IcacheWaitResponse && 1007 fetchStatus[tid] != IcacheWaitRetry) { 1008 DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid); 1009 1010 fetchStatus[tid] = Blocked; 1011 1012 return true; 1013 } 1014 1015 if (fetchStatus[tid] == Blocked || 1016 fetchStatus[tid] == Squashing) { 1017 // Switch status to running if fetch isn't being told to block or 1018 // squash this cycle. 1019 DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n", 1020 tid); 1021 1022 fetchStatus[tid] = Running; 1023 1024 return true; 1025 } 1026 1027 // If we've reached this point, we have not gotten any signals that 1028 // cause fetch to change its status. Fetch remains the same as before. 1029 return false; 1030} 1031 1032template<class Impl> 1033typename Impl::DynInstPtr 1034DefaultFetch<Impl>::buildInst(ThreadID tid, StaticInstPtr staticInst, 1035 StaticInstPtr curMacroop, TheISA::PCState thisPC, 1036 TheISA::PCState nextPC, bool trace) 1037{ 1038 // Get a sequence number. 1039 InstSeqNum seq = cpu->getAndIncrementInstSeq(); 1040 1041 // Create a new DynInst from the instruction fetched. 1042 DynInstPtr instruction = 1043 new DynInst(staticInst, curMacroop, thisPC, nextPC, seq, cpu); 1044 instruction->setTid(tid); 1045 1046 instruction->setASID(tid); 1047 1048 instruction->setThreadState(cpu->thread[tid]); 1049 1050 DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x (%d) created " 1051 "[sn:%lli].\n", tid, thisPC.instAddr(), 1052 thisPC.microPC(), seq); 1053 1054 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", tid, 1055 instruction->staticInst-> 1056 disassemble(thisPC.instAddr())); 1057 1058#if TRACING_ON 1059 if (trace) { 1060 instruction->traceData = 1061 cpu->getTracer()->getInstRecord(curTick(), cpu->tcBase(tid), 1062 instruction->staticInst, thisPC, curMacroop); 1063 } 1064#else 1065 instruction->traceData = NULL; 1066#endif 1067 1068 // Add instruction to the CPU's list of instructions. 1069 instruction->setInstListIt(cpu->addInst(instruction)); 1070 1071 // Write the instruction to the first slot in the queue 1072 // that heads to decode. 1073 assert(numInst < fetchWidth); 1074 toDecode->insts[toDecode->size++] = instruction; 1075 1076 // Keep track of if we can take an interrupt at this boundary 1077 delayedCommit[tid] = instruction->isDelayedCommit(); 1078 1079 return instruction; 1080} 1081 1082template<class Impl> 1083void 1084DefaultFetch<Impl>::fetch(bool &status_change) 1085{ 1086 ////////////////////////////////////////// 1087 // Start actual fetch 1088 ////////////////////////////////////////// 1089 ThreadID tid = getFetchingThread(fetchPolicy); 1090 1091 if (tid == InvalidThreadID || drainPending) { 1092 // Breaks looping condition in tick() 1093 threadFetched = numFetchingThreads; 1094 1095 if (numThreads == 1) { // @todo Per-thread stats 1096 profileStall(0); 1097 } 1098 1099 return; 1100 } 1101 1102 DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid); 1103 1104 // The current PC. 1105 TheISA::PCState thisPC = pc[tid]; 1106 1107 Addr pcOffset = fetchOffset[tid]; 1108 Addr fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask; 1109 1110 bool inRom = isRomMicroPC(thisPC.microPC()); 1111 1112 // If returning from the delay of a cache miss, then update the status 1113 // to running, otherwise do the cache access. Possibly move this up 1114 // to tick() function. 1115 if (fetchStatus[tid] == IcacheAccessComplete) { 1116 DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n", tid); 1117 1118 fetchStatus[tid] = Running; 1119 status_change = true; 1120 } else if (fetchStatus[tid] == Running) { 1121 // Align the fetch PC so its at the start of a cache block. 1122 Addr block_PC = icacheBlockAlignPC(fetchAddr); 1123 1124 // If buffer is no longer valid or fetchAddr has moved to point 1125 // to the next cache block, AND we have no remaining ucode 1126 // from a macro-op, then start fetch from icache. 1127 if (!(cacheDataValid[tid] && block_PC == cacheDataPC[tid]) 1128 && !inRom && !macroop[tid]) { 1129 DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read " 1130 "instruction, starting at PC %s.\n", tid, thisPC); 1131 1132 fetchCacheLine(fetchAddr, tid, thisPC.instAddr()); 1133 1134 if (fetchStatus[tid] == IcacheWaitResponse) 1135 ++icacheStallCycles; 1136 else if (fetchStatus[tid] == ItlbWait) 1137 ++fetchTlbCycles; 1138 else 1139 ++fetchMiscStallCycles; 1140 return; 1141 } else if ((checkInterrupt(thisPC.instAddr()) && !delayedCommit[tid]) 1142 || isSwitchedOut()) { 1143 // Stall CPU if an interrupt is posted and we're not issuing 1144 // an delayed commit micro-op currently (delayed commit instructions 1145 // are not interruptable by interrupts, only faults) 1146 ++fetchMiscStallCycles; 1147 return; 1148 } 1149 } else { 1150 if (fetchStatus[tid] == Idle) { 1151 ++fetchIdleCycles; 1152 DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid); 1153 } 1154 1155 // Status is Idle, so fetch should do nothing. 1156 return; 1157 } 1158 1159 ++fetchCycles; 1160 1161 TheISA::PCState nextPC = thisPC; 1162 1163 StaticInstPtr staticInst = NULL; 1164 StaticInstPtr curMacroop = macroop[tid]; 1165 1166 // If the read of the first instruction was successful, then grab the 1167 // instructions from the rest of the cache line and put them into the 1168 // queue heading to decode. 1169 1170 DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to " 1171 "decode.\n", tid); 1172 1173 // Need to keep track of whether or not a predicted branch 1174 // ended this fetch block. 1175 bool predictedBranch = false; 1176 1177 TheISA::MachInst *cacheInsts = 1178 reinterpret_cast<TheISA::MachInst *>(cacheData[tid]); 1179 1180 const unsigned numInsts = cacheBlkSize / instSize; 1181 unsigned blkOffset = (fetchAddr - cacheDataPC[tid]) / instSize; 1182 1183 // Loop through instruction memory from the cache. 1184 // Keep issuing while fetchWidth is available and branch is not 1185 // predicted taken 1186 while (numInst < fetchWidth && !predictedBranch) { 1187 1188 // We need to process more memory if we aren't going to get a 1189 // StaticInst from the rom, the current macroop, or what's already 1190 // in the predecoder. 1191 bool needMem = !inRom && !curMacroop && !predecoder.extMachInstReady(); 1192 1193 if (needMem) { 1194 if (blkOffset >= numInsts) { 1195 // We need to process more memory, but we've run out of the 1196 // current block. 1197 break; 1198 } 1199 1200 if (ISA_HAS_DELAY_SLOT && pcOffset == 0) { 1201 // Walk past any annulled delay slot instructions. 1202 Addr pcAddr = thisPC.instAddr() & BaseCPU::PCMask; 1203 while (fetchAddr != pcAddr && blkOffset < numInsts) { 1204 blkOffset++; 1205 fetchAddr += instSize; 1206 } 1207 if (blkOffset >= numInsts) 1208 break; 1209 } 1210 MachInst inst = TheISA::gtoh(cacheInsts[blkOffset]); 1211 1212 predecoder.setTC(cpu->thread[tid]->getTC()); 1213 predecoder.moreBytes(thisPC, fetchAddr, inst); 1214 1215 if (predecoder.needMoreBytes()) { 1216 blkOffset++; 1217 fetchAddr += instSize; 1218 pcOffset += instSize; 1219 } 1220 } 1221 1222 // Extract as many instructions and/or microops as we can from 1223 // the memory we've processed so far. 1224 do { 1225 if (!(curMacroop || inRom)) { 1226 if (predecoder.extMachInstReady()) { 1227 ExtMachInst extMachInst = 1228 predecoder.getExtMachInst(thisPC); 1229 staticInst = 1230 decoder.decode(extMachInst, thisPC.instAddr()); 1231 1232 // Increment stat of fetched instructions. 1233 ++fetchedInsts; 1234 1235 if (staticInst->isMacroop()) { 1236 curMacroop = staticInst; 1237 } else { 1238 pcOffset = 0; 1239 } 1240 } else { 1241 // We need more bytes for this instruction so blkOffset and 1242 // pcOffset will be updated 1243 break; 1244 } 1245 } 1246 // Whether we're moving to a new macroop because we're at the 1247 // end of the current one, or the branch predictor incorrectly 1248 // thinks we are... 1249 bool newMacro = false; 1250 if (curMacroop || inRom) { 1251 if (inRom) { 1252 staticInst = cpu->microcodeRom.fetchMicroop( 1253 thisPC.microPC(), curMacroop); 1254 } else { 1255 staticInst = curMacroop->fetchMicroop(thisPC.microPC()); 1256 } 1257 newMacro |= staticInst->isLastMicroop(); 1258 } 1259 1260 DynInstPtr instruction = 1261 buildInst(tid, staticInst, curMacroop, 1262 thisPC, nextPC, true); 1263 1264 numInst++; 1265 1266#if TRACING_ON 1267 instruction->fetchTick = curTick(); 1268#endif 1269 1270 nextPC = thisPC; 1271 1272 // If we're branching after this instruction, quite fetching 1273 // from the same block then. 1274 predictedBranch |= thisPC.branching(); 1275 predictedBranch |= 1276 lookupAndUpdateNextPC(instruction, nextPC); 1277 if (predictedBranch) { 1278 DPRINTF(Fetch, "Branch detected with PC = %s\n", thisPC); 1279 } 1280 1281 newMacro |= thisPC.instAddr() != nextPC.instAddr(); 1282 1283 // Move to the next instruction, unless we have a branch. 1284 thisPC = nextPC; 1285 inRom = isRomMicroPC(thisPC.microPC()); 1286 1287 if (newMacro) { 1288 fetchAddr = thisPC.instAddr() & BaseCPU::PCMask; 1289 blkOffset = (fetchAddr - cacheDataPC[tid]) / instSize; 1290 pcOffset = 0; 1291 curMacroop = NULL; 1292 } 1293 1294 if (instruction->isQuiesce()) { 1295 DPRINTF(Fetch, 1296 "Quiesce instruction encountered, halting fetch!"); 1297 fetchStatus[tid] = QuiescePending; 1298 status_change = true; 1299 break; 1300 } 1301 } while ((curMacroop || predecoder.extMachInstReady()) && 1302 numInst < fetchWidth); 1303 } 1304 1305 if (predictedBranch) { 1306 DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch " 1307 "instruction encountered.\n", tid); 1308 } else if (numInst >= fetchWidth) { 1309 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth " 1310 "for this cycle.\n", tid); 1311 } else if (blkOffset >= cacheBlkSize) { 1312 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache " 1313 "block.\n", tid); 1314 } 1315 1316 macroop[tid] = curMacroop; 1317 fetchOffset[tid] = pcOffset; 1318 1319 if (numInst > 0) { 1320 wroteToTimeBuffer = true; 1321 } 1322 1323 pc[tid] = thisPC; 1324 1325 // pipeline a fetch if we're crossing a cache boundary and not in 1326 // a state that would preclude fetching 1327 fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask; 1328 Addr block_PC = icacheBlockAlignPC(fetchAddr); 1329 issuePipelinedIfetch[tid] = block_PC != cacheDataPC[tid] && 1330 fetchStatus[tid] != IcacheWaitResponse && 1331 fetchStatus[tid] != ItlbWait && 1332 fetchStatus[tid] != IcacheWaitRetry && 1333 fetchStatus[tid] != QuiescePending && 1334 !curMacroop; 1335} 1336 1337template<class Impl> 1338void 1339DefaultFetch<Impl>::recvRetry() 1340{ 1341 if (retryPkt != NULL) { 1342 assert(cacheBlocked); 1343 assert(retryTid != InvalidThreadID); 1344 assert(fetchStatus[retryTid] == IcacheWaitRetry); 1345 1346 if (cpu->getIcachePort()->sendTiming(retryPkt)) { 1347 fetchStatus[retryTid] = IcacheWaitResponse; 1348 retryPkt = NULL; 1349 retryTid = InvalidThreadID; 1350 cacheBlocked = false; 1351 } 1352 } else { 1353 assert(retryTid == InvalidThreadID); 1354 // Access has been squashed since it was sent out. Just clear 1355 // the cache being blocked. 1356 cacheBlocked = false; 1357 } 1358} 1359 1360/////////////////////////////////////// 1361// // 1362// SMT FETCH POLICY MAINTAINED HERE // 1363// // 1364/////////////////////////////////////// 1365template<class Impl> 1366ThreadID 1367DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority) 1368{ 1369 if (numThreads > 1) { 1370 switch (fetch_priority) { 1371 1372 case SingleThread: 1373 return 0; 1374 1375 case RoundRobin: 1376 return roundRobin(); 1377 1378 case IQ: 1379 return iqCount(); 1380 1381 case LSQ: 1382 return lsqCount(); 1383 1384 case Branch: 1385 return branchCount(); 1386 1387 default: 1388 return InvalidThreadID; 1389 } 1390 } else { 1391 list<ThreadID>::iterator thread = activeThreads->begin(); 1392 if (thread == activeThreads->end()) { 1393 return InvalidThreadID; 1394 } 1395 1396 ThreadID tid = *thread; 1397 1398 if (fetchStatus[tid] == Running || 1399 fetchStatus[tid] == IcacheAccessComplete || 1400 fetchStatus[tid] == Idle) { 1401 return tid; 1402 } else { 1403 return InvalidThreadID; 1404 } 1405 } 1406} 1407 1408 1409template<class Impl> 1410ThreadID 1411DefaultFetch<Impl>::roundRobin() 1412{ 1413 list<ThreadID>::iterator pri_iter = priorityList.begin(); 1414 list<ThreadID>::iterator end = priorityList.end(); 1415 1416 ThreadID high_pri; 1417 1418 while (pri_iter != end) { 1419 high_pri = *pri_iter; 1420 1421 assert(high_pri <= numThreads); 1422 1423 if (fetchStatus[high_pri] == Running || 1424 fetchStatus[high_pri] == IcacheAccessComplete || 1425 fetchStatus[high_pri] == Idle) { 1426 1427 priorityList.erase(pri_iter); 1428 priorityList.push_back(high_pri); 1429 1430 return high_pri; 1431 } 1432 1433 pri_iter++; 1434 } 1435 1436 return InvalidThreadID; 1437} 1438 1439template<class Impl> 1440ThreadID 1441DefaultFetch<Impl>::iqCount() 1442{ 1443 std::priority_queue<unsigned> PQ; 1444 std::map<unsigned, ThreadID> threadMap; 1445 1446 list<ThreadID>::iterator threads = activeThreads->begin(); 1447 list<ThreadID>::iterator end = activeThreads->end(); 1448 1449 while (threads != end) { 1450 ThreadID tid = *threads++; 1451 unsigned iqCount = fromIEW->iewInfo[tid].iqCount; 1452 1453 PQ.push(iqCount); 1454 threadMap[iqCount] = tid; 1455 } 1456 1457 while (!PQ.empty()) { 1458 ThreadID high_pri = threadMap[PQ.top()]; 1459 1460 if (fetchStatus[high_pri] == Running || 1461 fetchStatus[high_pri] == IcacheAccessComplete || 1462 fetchStatus[high_pri] == Idle) 1463 return high_pri; 1464 else 1465 PQ.pop(); 1466 1467 } 1468 1469 return InvalidThreadID; 1470} 1471 1472template<class Impl> 1473ThreadID 1474DefaultFetch<Impl>::lsqCount() 1475{ 1476 std::priority_queue<unsigned> PQ; 1477 std::map<unsigned, ThreadID> threadMap; 1478 1479 list<ThreadID>::iterator threads = activeThreads->begin(); 1480 list<ThreadID>::iterator end = activeThreads->end(); 1481 1482 while (threads != end) { 1483 ThreadID tid = *threads++; 1484 unsigned ldstqCount = fromIEW->iewInfo[tid].ldstqCount; 1485 1486 PQ.push(ldstqCount); 1487 threadMap[ldstqCount] = tid; 1488 } 1489 1490 while (!PQ.empty()) { 1491 ThreadID high_pri = threadMap[PQ.top()]; 1492 1493 if (fetchStatus[high_pri] == Running || 1494 fetchStatus[high_pri] == IcacheAccessComplete || 1495 fetchStatus[high_pri] == Idle) 1496 return high_pri; 1497 else 1498 PQ.pop(); 1499 } 1500 1501 return InvalidThreadID; 1502} 1503 1504template<class Impl> 1505ThreadID 1506DefaultFetch<Impl>::branchCount() 1507{ 1508#if 0 1509 list<ThreadID>::iterator thread = activeThreads->begin(); 1510 assert(thread != activeThreads->end()); 1511 ThreadID tid = *thread; 1512#endif 1513 1514 panic("Branch Count Fetch policy unimplemented\n"); 1515 return InvalidThreadID; 1516} 1517 1518template<class Impl> 1519void 1520DefaultFetch<Impl>::pipelineIcacheAccesses(ThreadID tid) 1521{ 1522 if (!issuePipelinedIfetch[tid]) { 1523 return; 1524 } 1525 1526 // The next PC to access. 1527 TheISA::PCState thisPC = pc[tid]; 1528 1529 if (isRomMicroPC(thisPC.microPC())) { 1530 return; 1531 } 1532 1533 Addr pcOffset = fetchOffset[tid]; 1534 Addr fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask; 1535 1536 // Align the fetch PC so its at the start of a cache block. 1537 Addr block_PC = icacheBlockAlignPC(fetchAddr); 1538 1539 // Unless buffer already got the block, fetch it from icache. 1540 if (!(cacheDataValid[tid] && block_PC == cacheDataPC[tid])) { 1541 DPRINTF(Fetch, "[tid:%i]: Issuing a pipelined I-cache access, " 1542 "starting at PC %s.\n", tid, thisPC); 1543 1544 fetchCacheLine(fetchAddr, tid, thisPC.instAddr()); 1545 } 1546} 1547 1548template<class Impl> 1549void 1550DefaultFetch<Impl>::profileStall(ThreadID tid) { 1551 DPRINTF(Fetch,"There are no more threads available to fetch from.\n"); 1552 1553 // @todo Per-thread stats 1554 1555 if (drainPending) { 1556 ++fetchPendingDrainCycles; 1557 DPRINTF(Fetch, "Fetch is waiting for a drain!\n"); 1558 } else if (activeThreads->empty()) { 1559 ++fetchNoActiveThreadStallCycles; 1560 DPRINTF(Fetch, "Fetch has no active thread!\n"); 1561 } else if (fetchStatus[tid] == Blocked) { 1562 ++fetchBlockedCycles; 1563 DPRINTF(Fetch, "[tid:%i]: Fetch is blocked!\n", tid); 1564 } else if (fetchStatus[tid] == Squashing) { 1565 ++fetchSquashCycles; 1566 DPRINTF(Fetch, "[tid:%i]: Fetch is squashing!\n", tid); 1567 } else if (fetchStatus[tid] == IcacheWaitResponse) { 1568 ++icacheStallCycles; 1569 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n", 1570 tid); 1571 } else if (fetchStatus[tid] == ItlbWait) { 1572 ++fetchTlbCycles; 1573 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting ITLB walk to " 1574 "finish!\n", tid); 1575 } else if (fetchStatus[tid] == TrapPending) { 1576 ++fetchPendingTrapStallCycles; 1577 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting for a pending trap!\n", 1578 tid); 1579 } else if (fetchStatus[tid] == QuiescePending) { 1580 ++fetchPendingQuiesceStallCycles; 1581 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting for a pending quiesce " 1582 "instruction!\n", tid); 1583 } else if (fetchStatus[tid] == IcacheWaitRetry) { 1584 ++fetchIcacheWaitRetryStallCycles; 1585 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting for an I-cache retry!\n", 1586 tid); 1587 } else if (fetchStatus[tid] == NoGoodAddr) { 1588 DPRINTF(Fetch, "[tid:%i]: Fetch predicted non-executable address\n", 1589 tid); 1590 } else { 1591 DPRINTF(Fetch, "[tid:%i]: Unexpected fetch stall reason (Status: %i).\n", 1592 tid, fetchStatus[tid]); 1593 } 1594} 1595