fetch_impl.hh revision 8707:489489c67fd9 
1/*
2 * Copyright (c) 2010-2011 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 *          Korey Sewell
42 */
43
44#include <algorithm>
45#include <cstring>
46
47#include "arch/isa_traits.hh"
48#include "arch/utility.hh"
49#include "base/types.hh"
50#include "config/the_isa.hh"
51#include "config/use_checker.hh"
52#include "cpu/base.hh"
53#include "cpu/checker/cpu.hh"
54#include "cpu/o3/fetch.hh"
55#include "cpu/exetrace.hh"
56#include "debug/Activity.hh"
57#include "debug/Fetch.hh"
58#include "mem/packet.hh"
59#include "mem/request.hh"
60#include "params/DerivO3CPU.hh"
61#include "sim/byteswap.hh"
62#include "sim/core.hh"
63#include "sim/eventq.hh"
64
65#if FULL_SYSTEM
66#include "arch/tlb.hh"
67#include "arch/vtophys.hh"
68#include "sim/system.hh"
69#endif // FULL_SYSTEM
70
71using namespace std;
72
73template<class Impl>
74DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params)
75    : cpu(_cpu),
76      branchPred(params),
77      predecoder(NULL),
78      numInst(0),
79      decodeToFetchDelay(params->decodeToFetchDelay),
80      renameToFetchDelay(params->renameToFetchDelay),
81      iewToFetchDelay(params->iewToFetchDelay),
82      commitToFetchDelay(params->commitToFetchDelay),
83      fetchWidth(params->fetchWidth),
84      cacheBlocked(false),
85      retryPkt(NULL),
86      retryTid(InvalidThreadID),
87      numThreads(params->numThreads),
88      numFetchingThreads(params->smtNumFetchingThreads),
89      interruptPending(false),
90      drainPending(false),
91      switchedOut(false),
92      finishTranslationEvent(this)
93{
94    if (numThreads > Impl::MaxThreads)
95        fatal("numThreads (%d) is larger than compiled limit (%d),\n"
96              "\tincrease MaxThreads in src/cpu/o3/impl.hh\n",
97              numThreads, static_cast<int>(Impl::MaxThreads));
98
99    // Set fetch stage's status to inactive.
100    _status = Inactive;
101
102    std::string policy = params->smtFetchPolicy;
103
104    // Convert string to lowercase
105    std::transform(policy.begin(), policy.end(), policy.begin(),
106                   (int(*)(int)) tolower);
107
108    // Figure out fetch policy
109    if (policy == "singlethread") {
110        fetchPolicy = SingleThread;
111        if (numThreads > 1)
112            panic("Invalid Fetch Policy for a SMT workload.");
113    } else if (policy == "roundrobin") {
114        fetchPolicy = RoundRobin;
115        DPRINTF(Fetch, "Fetch policy set to Round Robin\n");
116    } else if (policy == "branch") {
117        fetchPolicy = Branch;
118        DPRINTF(Fetch, "Fetch policy set to Branch Count\n");
119    } else if (policy == "iqcount") {
120        fetchPolicy = IQ;
121        DPRINTF(Fetch, "Fetch policy set to IQ count\n");
122    } else if (policy == "lsqcount") {
123        fetchPolicy = LSQ;
124        DPRINTF(Fetch, "Fetch policy set to LSQ count\n");
125    } else {
126        fatal("Invalid Fetch Policy. Options Are: {SingleThread,"
127              " RoundRobin,LSQcount,IQcount}\n");
128    }
129
130    // Get the size of an instruction.
131    instSize = sizeof(TheISA::MachInst);
132}
133
134template <class Impl>
135std::string
136DefaultFetch<Impl>::name() const
137{
138    return cpu->name() + ".fetch";
139}
140
141template <class Impl>
142void
143DefaultFetch<Impl>::regStats()
144{
145    icacheStallCycles
146        .name(name() + ".icacheStallCycles")
147        .desc("Number of cycles fetch is stalled on an Icache miss")
148        .prereq(icacheStallCycles);
149
150    fetchedInsts
151        .name(name() + ".Insts")
152        .desc("Number of instructions fetch has processed")
153        .prereq(fetchedInsts);
154
155    fetchedBranches
156        .name(name() + ".Branches")
157        .desc("Number of branches that fetch encountered")
158        .prereq(fetchedBranches);
159
160    predictedBranches
161        .name(name() + ".predictedBranches")
162        .desc("Number of branches that fetch has predicted taken")
163        .prereq(predictedBranches);
164
165    fetchCycles
166        .name(name() + ".Cycles")
167        .desc("Number of cycles fetch has run and was not squashing or"
168              " blocked")
169        .prereq(fetchCycles);
170
171    fetchSquashCycles
172        .name(name() + ".SquashCycles")
173        .desc("Number of cycles fetch has spent squashing")
174        .prereq(fetchSquashCycles);
175
176    fetchTlbCycles
177        .name(name() + ".TlbCycles")
178        .desc("Number of cycles fetch has spent waiting for tlb")
179        .prereq(fetchTlbCycles);
180
181    fetchIdleCycles
182        .name(name() + ".IdleCycles")
183        .desc("Number of cycles fetch was idle")
184        .prereq(fetchIdleCycles);
185
186    fetchBlockedCycles
187        .name(name() + ".BlockedCycles")
188        .desc("Number of cycles fetch has spent blocked")
189        .prereq(fetchBlockedCycles);
190
191    fetchedCacheLines
192        .name(name() + ".CacheLines")
193        .desc("Number of cache lines fetched")
194        .prereq(fetchedCacheLines);
195
196    fetchMiscStallCycles
197        .name(name() + ".MiscStallCycles")
198        .desc("Number of cycles fetch has spent waiting on interrupts, or "
199              "bad addresses, or out of MSHRs")
200        .prereq(fetchMiscStallCycles);
201
202    fetchPendingDrainCycles
203        .name(name() + ".PendingDrainCycles")
204        .desc("Number of cycles fetch has spent waiting on pipes to drain")
205        .prereq(fetchPendingDrainCycles);
206
207    fetchNoActiveThreadStallCycles
208        .name(name() + ".NoActiveThreadStallCycles")
209        .desc("Number of stall cycles due to no active thread to fetch from")
210        .prereq(fetchNoActiveThreadStallCycles);
211
212    fetchPendingTrapStallCycles
213        .name(name() + ".PendingTrapStallCycles")
214        .desc("Number of stall cycles due to pending traps")
215        .prereq(fetchPendingTrapStallCycles);
216
217    fetchPendingQuiesceStallCycles
218        .name(name() + ".PendingQuiesceStallCycles")
219        .desc("Number of stall cycles due to pending quiesce instructions")
220        .prereq(fetchPendingQuiesceStallCycles);
221
222    fetchIcacheWaitRetryStallCycles
223        .name(name() + ".IcacheWaitRetryStallCycles")
224        .desc("Number of stall cycles due to full MSHR")
225        .prereq(fetchIcacheWaitRetryStallCycles);
226
227    fetchIcacheSquashes
228        .name(name() + ".IcacheSquashes")
229        .desc("Number of outstanding Icache misses that were squashed")
230        .prereq(fetchIcacheSquashes);
231
232    fetchTlbSquashes
233        .name(name() + ".ItlbSquashes")
234        .desc("Number of outstanding ITLB misses that were squashed")
235        .prereq(fetchTlbSquashes);
236
237    fetchNisnDist
238        .init(/* base value */ 0,
239              /* last value */ fetchWidth,
240              /* bucket size */ 1)
241        .name(name() + ".rateDist")
242        .desc("Number of instructions fetched each cycle (Total)")
243        .flags(Stats::pdf);
244
245    idleRate
246        .name(name() + ".idleRate")
247        .desc("Percent of cycles fetch was idle")
248        .prereq(idleRate);
249    idleRate = fetchIdleCycles * 100 / cpu->numCycles;
250
251    branchRate
252        .name(name() + ".branchRate")
253        .desc("Number of branch fetches per cycle")
254        .flags(Stats::total);
255    branchRate = fetchedBranches / cpu->numCycles;
256
257    fetchRate
258        .name(name() + ".rate")
259        .desc("Number of inst fetches per cycle")
260        .flags(Stats::total);
261    fetchRate = fetchedInsts / cpu->numCycles;
262
263    branchPred.regStats();
264}
265
266template<class Impl>
267void
268DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
269{
270    timeBuffer = time_buffer;
271
272    // Create wires to get information from proper places in time buffer.
273    fromDecode = timeBuffer->getWire(-decodeToFetchDelay);
274    fromRename = timeBuffer->getWire(-renameToFetchDelay);
275    fromIEW = timeBuffer->getWire(-iewToFetchDelay);
276    fromCommit = timeBuffer->getWire(-commitToFetchDelay);
277}
278
279template<class Impl>
280void
281DefaultFetch<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr)
282{
283    activeThreads = at_ptr;
284}
285
286template<class Impl>
287void
288DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
289{
290    fetchQueue = fq_ptr;
291
292    // Create wire to write information to proper place in fetch queue.
293    toDecode = fetchQueue->getWire(0);
294}
295
296template<class Impl>
297void
298DefaultFetch<Impl>::initStage()
299{
300    // Setup PC and nextPC with initial state.
301    for (ThreadID tid = 0; tid < numThreads; tid++) {
302        pc[tid] = cpu->pcState(tid);
303        fetchOffset[tid] = 0;
304        macroop[tid] = NULL;
305        delayedCommit[tid] = false;
306    }
307
308    for (ThreadID tid = 0; tid < numThreads; tid++) {
309
310        fetchStatus[tid] = Running;
311
312        priorityList.push_back(tid);
313
314        memReq[tid] = NULL;
315
316        stalls[tid].decode = false;
317        stalls[tid].rename = false;
318        stalls[tid].iew = false;
319        stalls[tid].commit = false;
320    }
321
322    // Schedule fetch to get the correct PC from the CPU
323    // scheduleFetchStartupEvent(1);
324
325    // Fetch needs to start fetching instructions at the very beginning,
326    // so it must start up in active state.
327    switchToActive();
328}
329
330template<class Impl>
331void
332DefaultFetch<Impl>::setIcache()
333{
334    assert(cpu->getIcachePort()->isConnected());
335
336    // Size of cache block.
337    cacheBlkSize = cpu->getIcachePort()->peerBlockSize();
338
339    // Create mask to get rid of offset bits.
340    cacheBlkMask = (cacheBlkSize - 1);
341
342    for (ThreadID tid = 0; tid < numThreads; tid++) {
343        // Create space to store a cache line.
344        cacheData[tid] = new uint8_t[cacheBlkSize];
345        cacheDataPC[tid] = 0;
346        cacheDataValid[tid] = false;
347    }
348}
349
350template<class Impl>
351void
352DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
353{
354    ThreadID tid = pkt->req->threadId();
355
356    DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n", tid);
357
358    assert(!pkt->wasNacked());
359
360    // Only change the status if it's still waiting on the icache access
361    // to return.
362    if (fetchStatus[tid] != IcacheWaitResponse ||
363        pkt->req != memReq[tid] ||
364        isSwitchedOut()) {
365        ++fetchIcacheSquashes;
366        delete pkt->req;
367        delete pkt;
368        return;
369    }
370
371    memcpy(cacheData[tid], pkt->getPtr<uint8_t>(), cacheBlkSize);
372    cacheDataValid[tid] = true;
373
374    if (!drainPending) {
375        // Wake up the CPU (if it went to sleep and was waiting on
376        // this completion event).
377        cpu->wakeCPU();
378
379        DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",
380                tid);
381
382        switchToActive();
383    }
384
385    // Only switch to IcacheAccessComplete if we're not stalled as well.
386    if (checkStall(tid)) {
387        fetchStatus[tid] = Blocked;
388    } else {
389        fetchStatus[tid] = IcacheAccessComplete;
390    }
391
392    // Reset the mem req to NULL.
393    delete pkt->req;
394    delete pkt;
395    memReq[tid] = NULL;
396}
397
398template <class Impl>
399bool
400DefaultFetch<Impl>::drain()
401{
402    // Fetch is ready to drain at any time.
403    cpu->signalDrained();
404    drainPending = true;
405    return true;
406}
407
408template <class Impl>
409void
410DefaultFetch<Impl>::resume()
411{
412    drainPending = false;
413}
414
415template <class Impl>
416void
417DefaultFetch<Impl>::switchOut()
418{
419    switchedOut = true;
420    // Branch predictor needs to have its state cleared.
421    branchPred.switchOut();
422}
423
424template <class Impl>
425void
426DefaultFetch<Impl>::takeOverFrom()
427{
428    // the instruction port is now connected so we can get the block
429    // size
430    setIcache();
431
432    // Reset all state
433    for (ThreadID i = 0; i < Impl::MaxThreads; ++i) {
434        stalls[i].decode = 0;
435        stalls[i].rename = 0;
436        stalls[i].iew = 0;
437        stalls[i].commit = 0;
438        pc[i] = cpu->pcState(i);
439        fetchStatus[i] = Running;
440    }
441    numInst = 0;
442    wroteToTimeBuffer = false;
443    _status = Inactive;
444    switchedOut = false;
445    interruptPending = false;
446    branchPred.takeOverFrom();
447}
448
449template <class Impl>
450void
451DefaultFetch<Impl>::wakeFromQuiesce()
452{
453    DPRINTF(Fetch, "Waking up from quiesce\n");
454    // Hopefully this is safe
455    // @todo: Allow other threads to wake from quiesce.
456    fetchStatus[0] = Running;
457}
458
459template <class Impl>
460inline void
461DefaultFetch<Impl>::switchToActive()
462{
463    if (_status == Inactive) {
464        DPRINTF(Activity, "Activating stage.\n");
465
466        cpu->activateStage(O3CPU::FetchIdx);
467
468        _status = Active;
469    }
470}
471
472template <class Impl>
473inline void
474DefaultFetch<Impl>::switchToInactive()
475{
476    if (_status == Active) {
477        DPRINTF(Activity, "Deactivating stage.\n");
478
479        cpu->deactivateStage(O3CPU::FetchIdx);
480
481        _status = Inactive;
482    }
483}
484
485template <class Impl>
486bool
487DefaultFetch<Impl>::lookupAndUpdateNextPC(
488        DynInstPtr &inst, TheISA::PCState &nextPC)
489{
490    // Do branch prediction check here.
491    // A bit of a misnomer...next_PC is actually the current PC until
492    // this function updates it.
493    bool predict_taken;
494
495    if (!inst->isControl()) {
496        TheISA::advancePC(nextPC, inst->staticInst);
497        inst->setPredTarg(nextPC);
498        inst->setPredTaken(false);
499        return false;
500    }
501
502    ThreadID tid = inst->threadNumber;
503    predict_taken = branchPred.predict(inst, nextPC, tid);
504
505    if (predict_taken) {
506        DPRINTF(Fetch, "[tid:%i]: [sn:%i]:  Branch predicted to be taken to %s.\n",
507                tid, inst->seqNum, nextPC);
508    } else {
509        DPRINTF(Fetch, "[tid:%i]: [sn:%i]:Branch predicted to be not taken.\n",
510                tid, inst->seqNum);
511    }
512
513    DPRINTF(Fetch, "[tid:%i]: [sn:%i] Branch predicted to go to %s.\n",
514            tid, inst->seqNum, nextPC);
515    inst->setPredTarg(nextPC);
516    inst->setPredTaken(predict_taken);
517
518    ++fetchedBranches;
519
520    if (predict_taken) {
521        ++predictedBranches;
522    }
523
524    return predict_taken;
525}
526
527template <class Impl>
528bool
529DefaultFetch<Impl>::fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc)
530{
531    Fault fault = NoFault;
532
533    // @todo: not sure if these should block translation.
534    //AlphaDep
535    if (cacheBlocked) {
536        DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n",
537                tid);
538        return false;
539    } else if (isSwitchedOut()) {
540        DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, switched out\n",
541                tid);
542        return false;
543    } else if (checkInterrupt(pc)) {
544        // Hold off fetch from getting new instructions when:
545        // Cache is blocked, or
546        // while an interrupt is pending and we're not in PAL mode, or
547        // fetch is switched out.
548        DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n",
549                tid);
550        return false;
551    }
552
553    // Align the fetch address so it's at the start of a cache block.
554    Addr block_PC = icacheBlockAlignPC(vaddr);
555
556    DPRINTF(Fetch, "[tid:%i] Fetching cache line %#x for addr %#x\n",
557            tid, block_PC, vaddr);
558
559    // Setup the memReq to do a read of the first instruction's address.
560    // Set the appropriate read size and flags as well.
561    // Build request here.
562    RequestPtr mem_req =
563        new Request(tid, block_PC, cacheBlkSize, Request::INST_FETCH,
564                    pc, cpu->thread[tid]->contextId(), tid);
565
566    memReq[tid] = mem_req;
567
568    // Initiate translation of the icache block
569    fetchStatus[tid] = ItlbWait;
570    FetchTranslation *trans = new FetchTranslation(this);
571    cpu->itb->translateTiming(mem_req, cpu->thread[tid]->getTC(),
572                              trans, BaseTLB::Execute);
573    return true;
574}
575
576template <class Impl>
577void
578DefaultFetch<Impl>::finishTranslation(Fault fault, RequestPtr mem_req)
579{
580    ThreadID tid = mem_req->threadId();
581    Addr block_PC = mem_req->getVaddr();
582
583    // Wake up CPU if it was idle
584    cpu->wakeCPU();
585
586    if (fetchStatus[tid] != ItlbWait || mem_req != memReq[tid] ||
587        mem_req->getVaddr() != memReq[tid]->getVaddr() || isSwitchedOut()) {
588        DPRINTF(Fetch, "[tid:%i] Ignoring itlb completed after squash\n",
589                tid);
590        ++fetchTlbSquashes;
591        delete mem_req;
592        return;
593    }
594
595
596    // If translation was successful, attempt to read the icache block.
597    if (fault == NoFault) {
598        // Check that we're not going off into random memory
599        // If we have, just wait around for commit to squash something and put
600        // us on the right track
601        if (!cpu->system->isMemory(mem_req->getPaddr())) {
602            warn("Address %#x is outside of physical memory, stopping fetch\n",
603                    mem_req->getPaddr());
604            fetchStatus[tid] = NoGoodAddr;
605            delete mem_req;
606            memReq[tid] = NULL;
607            return;
608        }
609
610        // Build packet here.
611        PacketPtr data_pkt = new Packet(mem_req,
612                                        MemCmd::ReadReq, Packet::Broadcast);
613        data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]);
614
615        cacheDataPC[tid] = block_PC;
616        cacheDataValid[tid] = false;
617        DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
618
619        fetchedCacheLines++;
620
621        // Access the cache.
622        if (!cpu->getIcachePort()->sendTiming(data_pkt)) {
623            assert(retryPkt == NULL);
624            assert(retryTid == InvalidThreadID);
625            DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
626
627            fetchStatus[tid] = IcacheWaitRetry;
628            retryPkt = data_pkt;
629            retryTid = tid;
630            cacheBlocked = true;
631        } else {
632            DPRINTF(Fetch, "[tid:%i]: Doing Icache access.\n", tid);
633            DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
634                    "response.\n", tid);
635
636            lastIcacheStall[tid] = curTick();
637            fetchStatus[tid] = IcacheWaitResponse;
638        }
639    } else {
640        if (!(numInst < fetchWidth)) {
641            assert(!finishTranslationEvent.scheduled());
642            finishTranslationEvent.setFault(fault);
643            finishTranslationEvent.setReq(mem_req);
644            cpu->schedule(finishTranslationEvent, cpu->nextCycle(curTick() + cpu->ticks(1)));
645            return;
646        }
647        DPRINTF(Fetch, "[tid:%i] Got back req with addr %#x but expected %#x\n",
648                tid, mem_req->getVaddr(), memReq[tid]->getVaddr());
649        // Translation faulted, icache request won't be sent.
650        delete mem_req;
651        memReq[tid] = NULL;
652
653        // Send the fault to commit.  This thread will not do anything
654        // until commit handles the fault.  The only other way it can
655        // wake up is if a squash comes along and changes the PC.
656        TheISA::PCState fetchPC = pc[tid];
657
658        DPRINTF(Fetch, "[tid:%i]: Translation faulted, building noop.\n", tid);
659        // We will use a nop in ordier to carry the fault.
660        DynInstPtr instruction = buildInst(tid,
661                decoder.decode(TheISA::NoopMachInst, fetchPC.instAddr()),
662                NULL, fetchPC, fetchPC, false);
663
664        instruction->setPredTarg(fetchPC);
665        instruction->fault = fault;
666        wroteToTimeBuffer = true;
667
668        DPRINTF(Activity, "Activity this cycle.\n");
669        cpu->activityThisCycle();
670
671        fetchStatus[tid] = TrapPending;
672
673        DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n", tid);
674        DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %s.\n",
675                tid, fault->name(), pc[tid]);
676    }
677    _status = updateFetchStatus();
678}
679
680template <class Impl>
681inline void
682DefaultFetch<Impl>::doSquash(const TheISA::PCState &newPC,
683                             const DynInstPtr squashInst, ThreadID tid)
684{
685    DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %s.\n",
686            tid, newPC);
687
688    pc[tid] = newPC;
689    fetchOffset[tid] = 0;
690    if (squashInst && squashInst->pcState().instAddr() == newPC.instAddr())
691        macroop[tid] = squashInst->macroop;
692    else
693        macroop[tid] = NULL;
694    predecoder.reset();
695
696    // Clear the icache miss if it's outstanding.
697    if (fetchStatus[tid] == IcacheWaitResponse) {
698        DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
699                tid);
700        memReq[tid] = NULL;
701    } else if (fetchStatus[tid] == ItlbWait) {
702        DPRINTF(Fetch, "[tid:%i]: Squashing outstanding ITLB miss.\n",
703                tid);
704        memReq[tid] = NULL;
705    }
706
707    // Get rid of the retrying packet if it was from this thread.
708    if (retryTid == tid) {
709        assert(cacheBlocked);
710        if (retryPkt) {
711            delete retryPkt->req;
712            delete retryPkt;
713        }
714        retryPkt = NULL;
715        retryTid = InvalidThreadID;
716    }
717
718    fetchStatus[tid] = Squashing;
719
720    ++fetchSquashCycles;
721}
722
723template<class Impl>
724void
725DefaultFetch<Impl>::squashFromDecode(const TheISA::PCState &newPC,
726                                     const DynInstPtr squashInst,
727                                     const InstSeqNum seq_num, ThreadID tid)
728{
729    DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n", tid);
730
731    doSquash(newPC, squashInst, tid);
732
733    // Tell the CPU to remove any instructions that are in flight between
734    // fetch and decode.
735    cpu->removeInstsUntil(seq_num, tid);
736}
737
738template<class Impl>
739bool
740DefaultFetch<Impl>::checkStall(ThreadID tid) const
741{
742    bool ret_val = false;
743
744    if (cpu->contextSwitch) {
745        DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid);
746        ret_val = true;
747    } else if (stalls[tid].decode) {
748        DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid);
749        ret_val = true;
750    } else if (stalls[tid].rename) {
751        DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid);
752        ret_val = true;
753    } else if (stalls[tid].iew) {
754        DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid);
755        ret_val = true;
756    } else if (stalls[tid].commit) {
757        DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid);
758        ret_val = true;
759    }
760
761    return ret_val;
762}
763
764template<class Impl>
765typename DefaultFetch<Impl>::FetchStatus
766DefaultFetch<Impl>::updateFetchStatus()
767{
768    //Check Running
769    list<ThreadID>::iterator threads = activeThreads->begin();
770    list<ThreadID>::iterator end = activeThreads->end();
771
772    while (threads != end) {
773        ThreadID tid = *threads++;
774
775        if (fetchStatus[tid] == Running ||
776            fetchStatus[tid] == Squashing ||
777            fetchStatus[tid] == IcacheAccessComplete) {
778
779            if (_status == Inactive) {
780                DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid);
781
782                if (fetchStatus[tid] == IcacheAccessComplete) {
783                    DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache"
784                            "completion\n",tid);
785                }
786
787                cpu->activateStage(O3CPU::FetchIdx);
788            }
789
790            return Active;
791        }
792    }
793
794    // Stage is switching from active to inactive, notify CPU of it.
795    if (_status == Active) {
796        DPRINTF(Activity, "Deactivating stage.\n");
797
798        cpu->deactivateStage(O3CPU::FetchIdx);
799    }
800
801    return Inactive;
802}
803
804template <class Impl>
805void
806DefaultFetch<Impl>::squash(const TheISA::PCState &newPC,
807                           const InstSeqNum seq_num, DynInstPtr squashInst,
808                           ThreadID tid)
809{
810    DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n", tid);
811
812    doSquash(newPC, squashInst, tid);
813
814    // Tell the CPU to remove any instructions that are not in the ROB.
815    cpu->removeInstsNotInROB(tid);
816}
817
818template <class Impl>
819void
820DefaultFetch<Impl>::tick()
821{
822    list<ThreadID>::iterator threads = activeThreads->begin();
823    list<ThreadID>::iterator end = activeThreads->end();
824    bool status_change = false;
825
826    wroteToTimeBuffer = false;
827
828    for (ThreadID i = 0; i < Impl::MaxThreads; ++i) {
829        issuePipelinedIfetch[i] = false;
830    }
831
832    while (threads != end) {
833        ThreadID tid = *threads++;
834
835        // Check the signals for each thread to determine the proper status
836        // for each thread.
837        bool updated_status = checkSignalsAndUpdate(tid);
838        status_change =  status_change || updated_status;
839    }
840
841    DPRINTF(Fetch, "Running stage.\n");
842
843    #if FULL_SYSTEM
844    if (fromCommit->commitInfo[0].interruptPending) {
845        interruptPending = true;
846    }
847
848    if (fromCommit->commitInfo[0].clearInterrupt) {
849        interruptPending = false;
850    }
851#endif
852
853    for (threadFetched = 0; threadFetched < numFetchingThreads;
854         threadFetched++) {
855        // Fetch each of the actively fetching threads.
856        fetch(status_change);
857    }
858
859    // Record number of instructions fetched this cycle for distribution.
860    fetchNisnDist.sample(numInst);
861
862    if (status_change) {
863        // Change the fetch stage status if there was a status change.
864        _status = updateFetchStatus();
865    }
866
867    // If there was activity this cycle, inform the CPU of it.
868    if (wroteToTimeBuffer || cpu->contextSwitch) {
869        DPRINTF(Activity, "Activity this cycle.\n");
870
871        cpu->activityThisCycle();
872    }
873
874    // Issue the next I-cache request if possible.
875    for (ThreadID i = 0; i < Impl::MaxThreads; ++i) {
876        if (issuePipelinedIfetch[i]) {
877            pipelineIcacheAccesses(i);
878        }
879    }
880
881    // Reset the number of the instruction we've fetched.
882    numInst = 0;
883}
884
885template <class Impl>
886bool
887DefaultFetch<Impl>::checkSignalsAndUpdate(ThreadID tid)
888{
889    // Update the per thread stall statuses.
890    if (fromDecode->decodeBlock[tid]) {
891        stalls[tid].decode = true;
892    }
893
894    if (fromDecode->decodeUnblock[tid]) {
895        assert(stalls[tid].decode);
896        assert(!fromDecode->decodeBlock[tid]);
897        stalls[tid].decode = false;
898    }
899
900    if (fromRename->renameBlock[tid]) {
901        stalls[tid].rename = true;
902    }
903
904    if (fromRename->renameUnblock[tid]) {
905        assert(stalls[tid].rename);
906        assert(!fromRename->renameBlock[tid]);
907        stalls[tid].rename = false;
908    }
909
910    if (fromIEW->iewBlock[tid]) {
911        stalls[tid].iew = true;
912    }
913
914    if (fromIEW->iewUnblock[tid]) {
915        assert(stalls[tid].iew);
916        assert(!fromIEW->iewBlock[tid]);
917        stalls[tid].iew = false;
918    }
919
920    if (fromCommit->commitBlock[tid]) {
921        stalls[tid].commit = true;
922    }
923
924    if (fromCommit->commitUnblock[tid]) {
925        assert(stalls[tid].commit);
926        assert(!fromCommit->commitBlock[tid]);
927        stalls[tid].commit = false;
928    }
929
930    // Check squash signals from commit.
931    if (fromCommit->commitInfo[tid].squash) {
932
933        DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
934                "from commit.\n",tid);
935        // In any case, squash.
936        squash(fromCommit->commitInfo[tid].pc,
937               fromCommit->commitInfo[tid].doneSeqNum,
938               fromCommit->commitInfo[tid].squashInst, tid);
939
940        // If it was a branch mispredict on a control instruction, update the
941        // branch predictor with that instruction, otherwise just kill the
942        // invalid state we generated in after sequence number
943        if (fromCommit->commitInfo[tid].mispredictInst &&
944            fromCommit->commitInfo[tid].mispredictInst->isControl()) {
945            branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
946                              fromCommit->commitInfo[tid].pc,
947                              fromCommit->commitInfo[tid].branchTaken,
948                              tid);
949        } else {
950            branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
951                              tid);
952        }
953
954        return true;
955    } else if (fromCommit->commitInfo[tid].doneSeqNum) {
956        // Update the branch predictor if it wasn't a squashed instruction
957        // that was broadcasted.
958        branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid);
959    }
960
961    // Check ROB squash signals from commit.
962    if (fromCommit->commitInfo[tid].robSquashing) {
963        DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid);
964
965        // Continue to squash.
966        fetchStatus[tid] = Squashing;
967
968        return true;
969    }
970
971    // Check squash signals from decode.
972    if (fromDecode->decodeInfo[tid].squash) {
973        DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
974                "from decode.\n",tid);
975
976        // Update the branch predictor.
977        if (fromDecode->decodeInfo[tid].branchMispredict) {
978            branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
979                              fromDecode->decodeInfo[tid].nextPC,
980                              fromDecode->decodeInfo[tid].branchTaken,
981                              tid);
982        } else {
983            branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
984                              tid);
985        }
986
987        if (fetchStatus[tid] != Squashing) {
988
989            DPRINTF(Fetch, "Squashing from decode with PC = %s\n",
990                fromDecode->decodeInfo[tid].nextPC);
991            // Squash unless we're already squashing
992            squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
993                             fromDecode->decodeInfo[tid].squashInst,
994                             fromDecode->decodeInfo[tid].doneSeqNum,
995                             tid);
996
997            return true;
998        }
999    }
1000
1001    if (checkStall(tid) &&
1002        fetchStatus[tid] != IcacheWaitResponse &&
1003        fetchStatus[tid] != IcacheWaitRetry) {
1004        DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid);
1005
1006        fetchStatus[tid] = Blocked;
1007
1008        return true;
1009    }
1010
1011    if (fetchStatus[tid] == Blocked ||
1012        fetchStatus[tid] == Squashing) {
1013        // Switch status to running if fetch isn't being told to block or
1014        // squash this cycle.
1015        DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n",
1016                tid);
1017
1018        fetchStatus[tid] = Running;
1019
1020        return true;
1021    }
1022
1023    // If we've reached this point, we have not gotten any signals that
1024    // cause fetch to change its status.  Fetch remains the same as before.
1025    return false;
1026}
1027
1028template<class Impl>
1029typename Impl::DynInstPtr
1030DefaultFetch<Impl>::buildInst(ThreadID tid, StaticInstPtr staticInst,
1031                              StaticInstPtr curMacroop, TheISA::PCState thisPC,
1032                              TheISA::PCState nextPC, bool trace)
1033{
1034    // Get a sequence number.
1035    InstSeqNum seq = cpu->getAndIncrementInstSeq();
1036
1037    // Create a new DynInst from the instruction fetched.
1038    DynInstPtr instruction =
1039        new DynInst(staticInst, curMacroop, thisPC, nextPC, seq, cpu);
1040    instruction->setTid(tid);
1041
1042    instruction->setASID(tid);
1043
1044    instruction->setThreadState(cpu->thread[tid]);
1045
1046    DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x (%d) created "
1047            "[sn:%lli].\n", tid, thisPC.instAddr(),
1048            thisPC.microPC(), seq);
1049
1050    DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", tid,
1051            instruction->staticInst->
1052            disassemble(thisPC.instAddr()));
1053
1054#if TRACING_ON
1055    if (trace) {
1056        instruction->traceData =
1057            cpu->getTracer()->getInstRecord(curTick(), cpu->tcBase(tid),
1058                    instruction->staticInst, thisPC, curMacroop);
1059    }
1060#else
1061    instruction->traceData = NULL;
1062#endif
1063
1064    // Add instruction to the CPU's list of instructions.
1065    instruction->setInstListIt(cpu->addInst(instruction));
1066
1067    // Write the instruction to the first slot in the queue
1068    // that heads to decode.
1069    assert(numInst < fetchWidth);
1070    toDecode->insts[toDecode->size++] = instruction;
1071
1072    // Keep track of if we can take an interrupt at this boundary
1073    delayedCommit[tid] = instruction->isDelayedCommit();
1074
1075    return instruction;
1076}
1077
1078template<class Impl>
1079void
1080DefaultFetch<Impl>::fetch(bool &status_change)
1081{
1082    //////////////////////////////////////////
1083    // Start actual fetch
1084    //////////////////////////////////////////
1085    ThreadID tid = getFetchingThread(fetchPolicy);
1086
1087    if (tid == InvalidThreadID || drainPending) {
1088        // Breaks looping condition in tick()
1089        threadFetched = numFetchingThreads;
1090
1091        if (numThreads == 1) {  // @todo Per-thread stats
1092            profileStall(0);
1093        }
1094
1095        return;
1096    }
1097
1098    DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
1099
1100    // The current PC.
1101    TheISA::PCState thisPC = pc[tid];
1102
1103    Addr pcOffset = fetchOffset[tid];
1104    Addr fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask;
1105
1106    bool inRom = isRomMicroPC(thisPC.microPC());
1107
1108    // If returning from the delay of a cache miss, then update the status
1109    // to running, otherwise do the cache access.  Possibly move this up
1110    // to tick() function.
1111    if (fetchStatus[tid] == IcacheAccessComplete) {
1112        DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n", tid);
1113
1114        fetchStatus[tid] = Running;
1115        status_change = true;
1116    } else if (fetchStatus[tid] == Running) {
1117        // Align the fetch PC so its at the start of a cache block.
1118        Addr block_PC = icacheBlockAlignPC(fetchAddr);
1119
1120        // If buffer is no longer valid or fetchAddr has moved to point
1121        // to the next cache block, AND we have no remaining ucode
1122        // from a macro-op, then start fetch from icache.
1123        if (!(cacheDataValid[tid] && block_PC == cacheDataPC[tid])
1124            && !inRom && !macroop[tid]) {
1125            DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
1126                    "instruction, starting at PC %s.\n", tid, thisPC);
1127
1128            fetchCacheLine(fetchAddr, tid, thisPC.instAddr());
1129
1130            if (fetchStatus[tid] == IcacheWaitResponse)
1131                ++icacheStallCycles;
1132            else if (fetchStatus[tid] == ItlbWait)
1133                ++fetchTlbCycles;
1134            else
1135                ++fetchMiscStallCycles;
1136            return;
1137        } else if ((checkInterrupt(thisPC.instAddr()) && !delayedCommit[tid])
1138                   || isSwitchedOut()) {
1139            // Stall CPU if an interrupt is posted and we're not issuing
1140            // an delayed commit micro-op currently (delayed commit instructions
1141            // are not interruptable by interrupts, only faults)
1142            ++fetchMiscStallCycles;
1143            return;
1144        }
1145    } else {
1146        if (fetchStatus[tid] == Idle) {
1147            ++fetchIdleCycles;
1148            DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid);
1149        }
1150
1151        // Status is Idle, so fetch should do nothing.
1152        return;
1153    }
1154
1155    ++fetchCycles;
1156
1157    TheISA::PCState nextPC = thisPC;
1158
1159    StaticInstPtr staticInst = NULL;
1160    StaticInstPtr curMacroop = macroop[tid];
1161
1162    // If the read of the first instruction was successful, then grab the
1163    // instructions from the rest of the cache line and put them into the
1164    // queue heading to decode.
1165
1166    DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
1167            "decode.\n", tid);
1168
1169    // Need to keep track of whether or not a predicted branch
1170    // ended this fetch block.
1171    bool predictedBranch = false;
1172
1173    TheISA::MachInst *cacheInsts =
1174        reinterpret_cast<TheISA::MachInst *>(cacheData[tid]);
1175
1176    const unsigned numInsts = cacheBlkSize / instSize;
1177    unsigned blkOffset = (fetchAddr - cacheDataPC[tid]) / instSize;
1178
1179    // Loop through instruction memory from the cache.
1180    // Keep issuing while fetchWidth is available and branch is not
1181    // predicted taken
1182    while (numInst < fetchWidth && !predictedBranch) {
1183
1184        // We need to process more memory if we aren't going to get a
1185        // StaticInst from the rom, the current macroop, or what's already
1186        // in the predecoder.
1187        bool needMem = !inRom && !curMacroop && !predecoder.extMachInstReady();
1188
1189        if (needMem) {
1190            if (blkOffset >= numInsts) {
1191                // We need to process more memory, but we've run out of the
1192                // current block.
1193                break;
1194            }
1195
1196            if (ISA_HAS_DELAY_SLOT && pcOffset == 0) {
1197                // Walk past any annulled delay slot instructions.
1198                Addr pcAddr = thisPC.instAddr() & BaseCPU::PCMask;
1199                while (fetchAddr != pcAddr && blkOffset < numInsts) {
1200                    blkOffset++;
1201                    fetchAddr += instSize;
1202                }
1203                if (blkOffset >= numInsts)
1204                    break;
1205            }
1206            MachInst inst = TheISA::gtoh(cacheInsts[blkOffset]);
1207
1208            predecoder.setTC(cpu->thread[tid]->getTC());
1209            predecoder.moreBytes(thisPC, fetchAddr, inst);
1210
1211            if (predecoder.needMoreBytes()) {
1212                blkOffset++;
1213                fetchAddr += instSize;
1214                pcOffset += instSize;
1215            }
1216        }
1217
1218        // Extract as many instructions and/or microops as we can from
1219        // the memory we've processed so far.
1220        do {
1221            if (!(curMacroop || inRom)) {
1222                if (predecoder.extMachInstReady()) {
1223                    ExtMachInst extMachInst =
1224                        predecoder.getExtMachInst(thisPC);
1225                    staticInst =
1226                        decoder.decode(extMachInst, thisPC.instAddr());
1227
1228                    // Increment stat of fetched instructions.
1229                    ++fetchedInsts;
1230
1231                    if (staticInst->isMacroop()) {
1232                        curMacroop = staticInst;
1233                    } else {
1234                        pcOffset = 0;
1235                    }
1236                } else {
1237                    // We need more bytes for this instruction so blkOffset and
1238                    // pcOffset will be updated
1239                    break;
1240                }
1241            }
1242            // Whether we're moving to a new macroop because we're at the
1243            // end of the current one, or the branch predictor incorrectly
1244            // thinks we are...
1245            bool newMacro = false;
1246            if (curMacroop || inRom) {
1247                if (inRom) {
1248                    staticInst = cpu->microcodeRom.fetchMicroop(
1249                            thisPC.microPC(), curMacroop);
1250                } else {
1251                    staticInst = curMacroop->fetchMicroop(thisPC.microPC());
1252                }
1253                newMacro |= staticInst->isLastMicroop();
1254            }
1255
1256            DynInstPtr instruction =
1257                buildInst(tid, staticInst, curMacroop,
1258                          thisPC, nextPC, true);
1259
1260            numInst++;
1261
1262#if TRACING_ON
1263            instruction->fetchTick = curTick();
1264#endif
1265
1266            nextPC = thisPC;
1267
1268            // If we're branching after this instruction, quite fetching
1269            // from the same block then.
1270            predictedBranch |= thisPC.branching();
1271            predictedBranch |=
1272                lookupAndUpdateNextPC(instruction, nextPC);
1273            if (predictedBranch) {
1274                DPRINTF(Fetch, "Branch detected with PC = %s\n", thisPC);
1275            }
1276
1277            newMacro |= thisPC.instAddr() != nextPC.instAddr();
1278
1279            // Move to the next instruction, unless we have a branch.
1280            thisPC = nextPC;
1281
1282            if (newMacro) {
1283                fetchAddr = thisPC.instAddr() & BaseCPU::PCMask;
1284                blkOffset = (fetchAddr - cacheDataPC[tid]) / instSize;
1285                pcOffset = 0;
1286                curMacroop = NULL;
1287            }
1288
1289            if (instruction->isQuiesce()) {
1290                DPRINTF(Fetch,
1291                        "Quiesce instruction encountered, halting fetch!");
1292                fetchStatus[tid] = QuiescePending;
1293                status_change = true;
1294                break;
1295            }
1296        } while ((curMacroop || predecoder.extMachInstReady()) &&
1297                 numInst < fetchWidth);
1298    }
1299
1300    if (predictedBranch) {
1301        DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch "
1302                "instruction encountered.\n", tid);
1303    } else if (numInst >= fetchWidth) {
1304        DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth "
1305                "for this cycle.\n", tid);
1306    } else if (blkOffset >= cacheBlkSize) {
1307        DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache "
1308                "block.\n", tid);
1309    }
1310
1311    macroop[tid] = curMacroop;
1312    fetchOffset[tid] = pcOffset;
1313
1314    if (numInst > 0) {
1315        wroteToTimeBuffer = true;
1316    }
1317
1318    pc[tid] = thisPC;
1319
1320    // pipeline a fetch if we're crossing a cache boundary and not in
1321    // a state that would preclude fetching
1322    fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask;
1323    Addr block_PC = icacheBlockAlignPC(fetchAddr);
1324    issuePipelinedIfetch[tid] = block_PC != cacheDataPC[tid] &&
1325        fetchStatus[tid] != IcacheWaitResponse &&
1326        fetchStatus[tid] != ItlbWait &&
1327        fetchStatus[tid] != IcacheWaitRetry &&
1328        fetchStatus[tid] != QuiescePending &&
1329        !curMacroop;
1330}
1331
1332template<class Impl>
1333void
1334DefaultFetch<Impl>::recvRetry()
1335{
1336    if (retryPkt != NULL) {
1337        assert(cacheBlocked);
1338        assert(retryTid != InvalidThreadID);
1339        assert(fetchStatus[retryTid] == IcacheWaitRetry);
1340
1341        if (cpu->getIcachePort()->sendTiming(retryPkt)) {
1342            fetchStatus[retryTid] = IcacheWaitResponse;
1343            retryPkt = NULL;
1344            retryTid = InvalidThreadID;
1345            cacheBlocked = false;
1346        }
1347    } else {
1348        assert(retryTid == InvalidThreadID);
1349        // Access has been squashed since it was sent out.  Just clear
1350        // the cache being blocked.
1351        cacheBlocked = false;
1352    }
1353}
1354
1355///////////////////////////////////////
1356//                                   //
1357//  SMT FETCH POLICY MAINTAINED HERE //
1358//                                   //
1359///////////////////////////////////////
1360template<class Impl>
1361ThreadID
1362DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority)
1363{
1364    if (numThreads > 1) {
1365        switch (fetch_priority) {
1366
1367          case SingleThread:
1368            return 0;
1369
1370          case RoundRobin:
1371            return roundRobin();
1372
1373          case IQ:
1374            return iqCount();
1375
1376          case LSQ:
1377            return lsqCount();
1378
1379          case Branch:
1380            return branchCount();
1381
1382          default:
1383            return InvalidThreadID;
1384        }
1385    } else {
1386        list<ThreadID>::iterator thread = activeThreads->begin();
1387        if (thread == activeThreads->end()) {
1388            return InvalidThreadID;
1389        }
1390
1391        ThreadID tid = *thread;
1392
1393        if (fetchStatus[tid] == Running ||
1394            fetchStatus[tid] == IcacheAccessComplete ||
1395            fetchStatus[tid] == Idle) {
1396            return tid;
1397        } else {
1398            return InvalidThreadID;
1399        }
1400    }
1401}
1402
1403
1404template<class Impl>
1405ThreadID
1406DefaultFetch<Impl>::roundRobin()
1407{
1408    list<ThreadID>::iterator pri_iter = priorityList.begin();
1409    list<ThreadID>::iterator end      = priorityList.end();
1410
1411    ThreadID high_pri;
1412
1413    while (pri_iter != end) {
1414        high_pri = *pri_iter;
1415
1416        assert(high_pri <= numThreads);
1417
1418        if (fetchStatus[high_pri] == Running ||
1419            fetchStatus[high_pri] == IcacheAccessComplete ||
1420            fetchStatus[high_pri] == Idle) {
1421
1422            priorityList.erase(pri_iter);
1423            priorityList.push_back(high_pri);
1424
1425            return high_pri;
1426        }
1427
1428        pri_iter++;
1429    }
1430
1431    return InvalidThreadID;
1432}
1433
1434template<class Impl>
1435ThreadID
1436DefaultFetch<Impl>::iqCount()
1437{
1438    std::priority_queue<unsigned> PQ;
1439    std::map<unsigned, ThreadID> threadMap;
1440
1441    list<ThreadID>::iterator threads = activeThreads->begin();
1442    list<ThreadID>::iterator end = activeThreads->end();
1443
1444    while (threads != end) {
1445        ThreadID tid = *threads++;
1446        unsigned iqCount = fromIEW->iewInfo[tid].iqCount;
1447
1448        PQ.push(iqCount);
1449        threadMap[iqCount] = tid;
1450    }
1451
1452    while (!PQ.empty()) {
1453        ThreadID high_pri = threadMap[PQ.top()];
1454
1455        if (fetchStatus[high_pri] == Running ||
1456            fetchStatus[high_pri] == IcacheAccessComplete ||
1457            fetchStatus[high_pri] == Idle)
1458            return high_pri;
1459        else
1460            PQ.pop();
1461
1462    }
1463
1464    return InvalidThreadID;
1465}
1466
1467template<class Impl>
1468ThreadID
1469DefaultFetch<Impl>::lsqCount()
1470{
1471    std::priority_queue<unsigned> PQ;
1472    std::map<unsigned, ThreadID> threadMap;
1473
1474    list<ThreadID>::iterator threads = activeThreads->begin();
1475    list<ThreadID>::iterator end = activeThreads->end();
1476
1477    while (threads != end) {
1478        ThreadID tid = *threads++;
1479        unsigned ldstqCount = fromIEW->iewInfo[tid].ldstqCount;
1480
1481        PQ.push(ldstqCount);
1482        threadMap[ldstqCount] = tid;
1483    }
1484
1485    while (!PQ.empty()) {
1486        ThreadID high_pri = threadMap[PQ.top()];
1487
1488        if (fetchStatus[high_pri] == Running ||
1489            fetchStatus[high_pri] == IcacheAccessComplete ||
1490            fetchStatus[high_pri] == Idle)
1491            return high_pri;
1492        else
1493            PQ.pop();
1494    }
1495
1496    return InvalidThreadID;
1497}
1498
1499template<class Impl>
1500ThreadID
1501DefaultFetch<Impl>::branchCount()
1502{
1503#if 0
1504    list<ThreadID>::iterator thread = activeThreads->begin();
1505    assert(thread != activeThreads->end());
1506    ThreadID tid = *thread;
1507#endif
1508
1509    panic("Branch Count Fetch policy unimplemented\n");
1510    return InvalidThreadID;
1511}
1512
1513template<class Impl>
1514void
1515DefaultFetch<Impl>::pipelineIcacheAccesses(ThreadID tid)
1516{
1517    if (!issuePipelinedIfetch[tid]) {
1518        return;
1519    }
1520
1521    // The next PC to access.
1522    TheISA::PCState thisPC = pc[tid];
1523
1524    if (isRomMicroPC(thisPC.microPC())) {
1525        return;
1526    }
1527
1528    Addr pcOffset = fetchOffset[tid];
1529    Addr fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask;
1530
1531    // Align the fetch PC so its at the start of a cache block.
1532    Addr block_PC = icacheBlockAlignPC(fetchAddr);
1533
1534    // Unless buffer already got the block, fetch it from icache.
1535    if (!(cacheDataValid[tid] && block_PC == cacheDataPC[tid])) {
1536        DPRINTF(Fetch, "[tid:%i]: Issuing a pipelined I-cache access, "
1537                "starting at PC %s.\n", tid, thisPC);
1538
1539        fetchCacheLine(fetchAddr, tid, thisPC.instAddr());
1540    }
1541}
1542
1543template<class Impl>
1544void
1545DefaultFetch<Impl>::profileStall(ThreadID tid) {
1546    DPRINTF(Fetch,"There are no more threads available to fetch from.\n");
1547
1548    // @todo Per-thread stats
1549
1550    if (drainPending) {
1551        ++fetchPendingDrainCycles;
1552        DPRINTF(Fetch, "Fetch is waiting for a drain!\n");
1553    } else if (activeThreads->empty()) {
1554        ++fetchNoActiveThreadStallCycles;
1555        DPRINTF(Fetch, "Fetch has no active thread!\n");
1556    } else if (fetchStatus[tid] == Blocked) {
1557        ++fetchBlockedCycles;
1558        DPRINTF(Fetch, "[tid:%i]: Fetch is blocked!\n", tid);
1559    } else if (fetchStatus[tid] == Squashing) {
1560        ++fetchSquashCycles;
1561        DPRINTF(Fetch, "[tid:%i]: Fetch is squashing!\n", tid);
1562    } else if (fetchStatus[tid] == IcacheWaitResponse) {
1563        ++icacheStallCycles;
1564        DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n",
1565                tid);
1566    } else if (fetchStatus[tid] == ItlbWait) {
1567        ++fetchTlbCycles;
1568        DPRINTF(Fetch, "[tid:%i]: Fetch is waiting ITLB walk to "
1569                "finish!\n", tid);
1570    } else if (fetchStatus[tid] == TrapPending) {
1571        ++fetchPendingTrapStallCycles;
1572        DPRINTF(Fetch, "[tid:%i]: Fetch is waiting for a pending trap!\n",
1573                tid);
1574    } else if (fetchStatus[tid] == QuiescePending) {
1575        ++fetchPendingQuiesceStallCycles;
1576        DPRINTF(Fetch, "[tid:%i]: Fetch is waiting for a pending quiesce "
1577                "instruction!\n", tid);
1578    } else if (fetchStatus[tid] == IcacheWaitRetry) {
1579        ++fetchIcacheWaitRetryStallCycles;
1580        DPRINTF(Fetch, "[tid:%i]: Fetch is waiting for an I-cache retry!\n",
1581                tid);
1582    } else if (fetchStatus[tid] == NoGoodAddr) {
1583            DPRINTF(Fetch, "[tid:%i]: Fetch predicted non-executable address\n",
1584                    tid);
1585    } else {
1586        DPRINTF(Fetch, "[tid:%i]: Unexpected fetch stall reason (Status: %i).\n",
1587             tid, fetchStatus[tid]);
1588    }
1589}
1590