fetch_impl.hh revision 8462:80492ae5148e
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 * Korey Sewell 42 */ 43 44#include <algorithm> 45#include <cstring> 46 47#include "arch/isa_traits.hh" 48#include "arch/utility.hh" 49#include "base/types.hh" 50#include "config/the_isa.hh" 51#include "config/use_checker.hh" 52#include "cpu/base.hh" 53#include "cpu/checker/cpu.hh" 54#include "cpu/o3/fetch.hh" 55#include "cpu/exetrace.hh" 56#include "debug/Activity.hh" 57#include "debug/Fetch.hh" 58#include "mem/packet.hh" 59#include "mem/request.hh" 60#include "params/DerivO3CPU.hh" 61#include "sim/byteswap.hh" 62#include "sim/core.hh" 63#include "sim/eventq.hh" 64 65#if FULL_SYSTEM 66#include "arch/tlb.hh" 67#include "arch/vtophys.hh" 68#include "sim/system.hh" 69#endif // FULL_SYSTEM 70 71using namespace std; 72 73template<class Impl> 74void 75DefaultFetch<Impl>::IcachePort::setPeer(Port *port) 76{ 77 Port::setPeer(port); 78 79 fetch->setIcache(); 80} 81 82template<class Impl> 83Tick 84DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt) 85{ 86 panic("DefaultFetch doesn't expect recvAtomic callback!"); 87 return curTick(); 88} 89 90template<class Impl> 91void 92DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt) 93{ 94 DPRINTF(Fetch, "DefaultFetch doesn't update its state from a " 95 "functional call.\n"); 96} 97 98template<class Impl> 99void 100DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status) 101{ 102 if (status == RangeChange) { 103 if (!snoopRangeSent) { 104 snoopRangeSent = true; 105 sendStatusChange(Port::RangeChange); 106 } 107 return; 108 } 109 110 panic("DefaultFetch doesn't expect recvStatusChange callback!"); 111} 112 113template<class Impl> 114bool 115DefaultFetch<Impl>::IcachePort::recvTiming(PacketPtr pkt) 116{ 117 DPRINTF(Fetch, "Received timing\n"); 118 if (pkt->isResponse()) { 119 // We shouldn't ever get a block in ownership state 120 assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted())); 121 122 fetch->processCacheCompletion(pkt); 123 } 124 //else Snooped a coherence request, just return 125 return true; 126} 127 128template<class Impl> 129void 130DefaultFetch<Impl>::IcachePort::recvRetry() 131{ 132 fetch->recvRetry(); 133} 134 135template<class Impl> 136DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params) 137 : cpu(_cpu), 138 branchPred(params), 139 predecoder(NULL), 140 numInst(0), 141 decodeToFetchDelay(params->decodeToFetchDelay), 142 renameToFetchDelay(params->renameToFetchDelay), 143 iewToFetchDelay(params->iewToFetchDelay), 144 commitToFetchDelay(params->commitToFetchDelay), 145 fetchWidth(params->fetchWidth), 146 cacheBlocked(false), 147 retryPkt(NULL), 148 retryTid(InvalidThreadID), 149 numThreads(params->numThreads), 150 numFetchingThreads(params->smtNumFetchingThreads), 151 interruptPending(false), 152 drainPending(false), 153 switchedOut(false), 154 finishTranslationEvent(this) 155{ 156 if (numThreads > Impl::MaxThreads) 157 fatal("numThreads (%d) is larger than compiled limit (%d),\n" 158 "\tincrease MaxThreads in src/cpu/o3/impl.hh\n", 159 numThreads, static_cast<int>(Impl::MaxThreads)); 160 161 // Set fetch stage's status to inactive. 162 _status = Inactive; 163 164 std::string policy = params->smtFetchPolicy; 165 166 // Convert string to lowercase 167 std::transform(policy.begin(), policy.end(), policy.begin(), 168 (int(*)(int)) tolower); 169 170 // Figure out fetch policy 171 if (policy == "singlethread") { 172 fetchPolicy = SingleThread; 173 if (numThreads > 1) 174 panic("Invalid Fetch Policy for a SMT workload."); 175 } else if (policy == "roundrobin") { 176 fetchPolicy = RoundRobin; 177 DPRINTF(Fetch, "Fetch policy set to Round Robin\n"); 178 } else if (policy == "branch") { 179 fetchPolicy = Branch; 180 DPRINTF(Fetch, "Fetch policy set to Branch Count\n"); 181 } else if (policy == "iqcount") { 182 fetchPolicy = IQ; 183 DPRINTF(Fetch, "Fetch policy set to IQ count\n"); 184 } else if (policy == "lsqcount") { 185 fetchPolicy = LSQ; 186 DPRINTF(Fetch, "Fetch policy set to LSQ count\n"); 187 } else { 188 fatal("Invalid Fetch Policy. Options Are: {SingleThread," 189 " RoundRobin,LSQcount,IQcount}\n"); 190 } 191 192 // Get the size of an instruction. 193 instSize = sizeof(TheISA::MachInst); 194 195 // Name is finally available, so create the port. 196 icachePort = new IcachePort(this); 197 198 icachePort->snoopRangeSent = false; 199 200#if USE_CHECKER 201 if (cpu->checker) { 202 cpu->checker->setIcachePort(icachePort); 203 } 204#endif 205} 206 207template <class Impl> 208std::string 209DefaultFetch<Impl>::name() const 210{ 211 return cpu->name() + ".fetch"; 212} 213 214template <class Impl> 215void 216DefaultFetch<Impl>::regStats() 217{ 218 icacheStallCycles 219 .name(name() + ".icacheStallCycles") 220 .desc("Number of cycles fetch is stalled on an Icache miss") 221 .prereq(icacheStallCycles); 222 223 fetchedInsts 224 .name(name() + ".Insts") 225 .desc("Number of instructions fetch has processed") 226 .prereq(fetchedInsts); 227 228 fetchedBranches 229 .name(name() + ".Branches") 230 .desc("Number of branches that fetch encountered") 231 .prereq(fetchedBranches); 232 233 predictedBranches 234 .name(name() + ".predictedBranches") 235 .desc("Number of branches that fetch has predicted taken") 236 .prereq(predictedBranches); 237 238 fetchCycles 239 .name(name() + ".Cycles") 240 .desc("Number of cycles fetch has run and was not squashing or" 241 " blocked") 242 .prereq(fetchCycles); 243 244 fetchSquashCycles 245 .name(name() + ".SquashCycles") 246 .desc("Number of cycles fetch has spent squashing") 247 .prereq(fetchSquashCycles); 248 249 fetchTlbCycles 250 .name(name() + ".TlbCycles") 251 .desc("Number of cycles fetch has spent waiting for tlb") 252 .prereq(fetchTlbCycles); 253 254 fetchIdleCycles 255 .name(name() + ".IdleCycles") 256 .desc("Number of cycles fetch was idle") 257 .prereq(fetchIdleCycles); 258 259 fetchBlockedCycles 260 .name(name() + ".BlockedCycles") 261 .desc("Number of cycles fetch has spent blocked") 262 .prereq(fetchBlockedCycles); 263 264 fetchedCacheLines 265 .name(name() + ".CacheLines") 266 .desc("Number of cache lines fetched") 267 .prereq(fetchedCacheLines); 268 269 fetchMiscStallCycles 270 .name(name() + ".MiscStallCycles") 271 .desc("Number of cycles fetch has spent waiting on interrupts, or " 272 "bad addresses, or out of MSHRs") 273 .prereq(fetchMiscStallCycles); 274 275 fetchPendingDrainCycles 276 .name(name() + ".PendingDrainCycles") 277 .desc("Number of cycles fetch has spent waiting on pipes to drain") 278 .prereq(fetchPendingDrainCycles); 279 280 fetchNoActiveThreadStallCycles 281 .name(name() + ".NoActiveThreadStallCycles") 282 .desc("Number of stall cycles due to no active thread to fetch from") 283 .prereq(fetchNoActiveThreadStallCycles); 284 285 fetchPendingTrapStallCycles 286 .name(name() + ".PendingTrapStallCycles") 287 .desc("Number of stall cycles due to pending traps") 288 .prereq(fetchPendingTrapStallCycles); 289 290 fetchPendingQuiesceStallCycles 291 .name(name() + ".PendingQuiesceStallCycles") 292 .desc("Number of stall cycles due to pending quiesce instructions") 293 .prereq(fetchPendingQuiesceStallCycles); 294 295 fetchIcacheWaitRetryStallCycles 296 .name(name() + ".IcacheWaitRetryStallCycles") 297 .desc("Number of stall cycles due to full MSHR") 298 .prereq(fetchIcacheWaitRetryStallCycles); 299 300 fetchIcacheSquashes 301 .name(name() + ".IcacheSquashes") 302 .desc("Number of outstanding Icache misses that were squashed") 303 .prereq(fetchIcacheSquashes); 304 305 fetchTlbSquashes 306 .name(name() + ".ItlbSquashes") 307 .desc("Number of outstanding ITLB misses that were squashed") 308 .prereq(fetchTlbSquashes); 309 310 fetchNisnDist 311 .init(/* base value */ 0, 312 /* last value */ fetchWidth, 313 /* bucket size */ 1) 314 .name(name() + ".rateDist") 315 .desc("Number of instructions fetched each cycle (Total)") 316 .flags(Stats::pdf); 317 318 idleRate 319 .name(name() + ".idleRate") 320 .desc("Percent of cycles fetch was idle") 321 .prereq(idleRate); 322 idleRate = fetchIdleCycles * 100 / cpu->numCycles; 323 324 branchRate 325 .name(name() + ".branchRate") 326 .desc("Number of branch fetches per cycle") 327 .flags(Stats::total); 328 branchRate = fetchedBranches / cpu->numCycles; 329 330 fetchRate 331 .name(name() + ".rate") 332 .desc("Number of inst fetches per cycle") 333 .flags(Stats::total); 334 fetchRate = fetchedInsts / cpu->numCycles; 335 336 branchPred.regStats(); 337} 338 339template<class Impl> 340void 341DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer) 342{ 343 timeBuffer = time_buffer; 344 345 // Create wires to get information from proper places in time buffer. 346 fromDecode = timeBuffer->getWire(-decodeToFetchDelay); 347 fromRename = timeBuffer->getWire(-renameToFetchDelay); 348 fromIEW = timeBuffer->getWire(-iewToFetchDelay); 349 fromCommit = timeBuffer->getWire(-commitToFetchDelay); 350} 351 352template<class Impl> 353void 354DefaultFetch<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr) 355{ 356 activeThreads = at_ptr; 357} 358 359template<class Impl> 360void 361DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 362{ 363 fetchQueue = fq_ptr; 364 365 // Create wire to write information to proper place in fetch queue. 366 toDecode = fetchQueue->getWire(0); 367} 368 369template<class Impl> 370void 371DefaultFetch<Impl>::initStage() 372{ 373 // Setup PC and nextPC with initial state. 374 for (ThreadID tid = 0; tid < numThreads; tid++) { 375 pc[tid] = cpu->pcState(tid); 376 fetchOffset[tid] = 0; 377 macroop[tid] = NULL; 378 delayedCommit[tid] = false; 379 } 380 381 for (ThreadID tid = 0; tid < numThreads; tid++) { 382 383 fetchStatus[tid] = Running; 384 385 priorityList.push_back(tid); 386 387 memReq[tid] = NULL; 388 389 stalls[tid].decode = false; 390 stalls[tid].rename = false; 391 stalls[tid].iew = false; 392 stalls[tid].commit = false; 393 } 394 395 // Schedule fetch to get the correct PC from the CPU 396 // scheduleFetchStartupEvent(1); 397 398 // Fetch needs to start fetching instructions at the very beginning, 399 // so it must start up in active state. 400 switchToActive(); 401} 402 403template<class Impl> 404void 405DefaultFetch<Impl>::setIcache() 406{ 407 // Size of cache block. 408 cacheBlkSize = icachePort->peerBlockSize(); 409 410 // Create mask to get rid of offset bits. 411 cacheBlkMask = (cacheBlkSize - 1); 412 413 for (ThreadID tid = 0; tid < numThreads; tid++) { 414 // Create space to store a cache line. 415 cacheData[tid] = new uint8_t[cacheBlkSize]; 416 cacheDataPC[tid] = 0; 417 cacheDataValid[tid] = false; 418 } 419} 420 421template<class Impl> 422void 423DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt) 424{ 425 ThreadID tid = pkt->req->threadId(); 426 427 DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n", tid); 428 429 assert(!pkt->wasNacked()); 430 431 // Only change the status if it's still waiting on the icache access 432 // to return. 433 if (fetchStatus[tid] != IcacheWaitResponse || 434 pkt->req != memReq[tid] || 435 isSwitchedOut()) { 436 ++fetchIcacheSquashes; 437 delete pkt->req; 438 delete pkt; 439 return; 440 } 441 442 memcpy(cacheData[tid], pkt->getPtr<uint8_t>(), cacheBlkSize); 443 cacheDataValid[tid] = true; 444 445 if (!drainPending) { 446 // Wake up the CPU (if it went to sleep and was waiting on 447 // this completion event). 448 cpu->wakeCPU(); 449 450 DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n", 451 tid); 452 453 switchToActive(); 454 } 455 456 // Only switch to IcacheAccessComplete if we're not stalled as well. 457 if (checkStall(tid)) { 458 fetchStatus[tid] = Blocked; 459 } else { 460 fetchStatus[tid] = IcacheAccessComplete; 461 } 462 463 // Reset the mem req to NULL. 464 delete pkt->req; 465 delete pkt; 466 memReq[tid] = NULL; 467} 468 469template <class Impl> 470bool 471DefaultFetch<Impl>::drain() 472{ 473 // Fetch is ready to drain at any time. 474 cpu->signalDrained(); 475 drainPending = true; 476 return true; 477} 478 479template <class Impl> 480void 481DefaultFetch<Impl>::resume() 482{ 483 drainPending = false; 484} 485 486template <class Impl> 487void 488DefaultFetch<Impl>::switchOut() 489{ 490 switchedOut = true; 491 // Branch predictor needs to have its state cleared. 492 branchPred.switchOut(); 493} 494 495template <class Impl> 496void 497DefaultFetch<Impl>::takeOverFrom() 498{ 499 // Reset all state 500 for (ThreadID i = 0; i < Impl::MaxThreads; ++i) { 501 stalls[i].decode = 0; 502 stalls[i].rename = 0; 503 stalls[i].iew = 0; 504 stalls[i].commit = 0; 505 pc[i] = cpu->pcState(i); 506 fetchStatus[i] = Running; 507 } 508 numInst = 0; 509 wroteToTimeBuffer = false; 510 _status = Inactive; 511 switchedOut = false; 512 interruptPending = false; 513 branchPred.takeOverFrom(); 514} 515 516template <class Impl> 517void 518DefaultFetch<Impl>::wakeFromQuiesce() 519{ 520 DPRINTF(Fetch, "Waking up from quiesce\n"); 521 // Hopefully this is safe 522 // @todo: Allow other threads to wake from quiesce. 523 fetchStatus[0] = Running; 524} 525 526template <class Impl> 527inline void 528DefaultFetch<Impl>::switchToActive() 529{ 530 if (_status == Inactive) { 531 DPRINTF(Activity, "Activating stage.\n"); 532 533 cpu->activateStage(O3CPU::FetchIdx); 534 535 _status = Active; 536 } 537} 538 539template <class Impl> 540inline void 541DefaultFetch<Impl>::switchToInactive() 542{ 543 if (_status == Active) { 544 DPRINTF(Activity, "Deactivating stage.\n"); 545 546 cpu->deactivateStage(O3CPU::FetchIdx); 547 548 _status = Inactive; 549 } 550} 551 552template <class Impl> 553bool 554DefaultFetch<Impl>::lookupAndUpdateNextPC( 555 DynInstPtr &inst, TheISA::PCState &nextPC) 556{ 557 // Do branch prediction check here. 558 // A bit of a misnomer...next_PC is actually the current PC until 559 // this function updates it. 560 bool predict_taken; 561 562 if (!inst->isControl()) { 563 TheISA::advancePC(nextPC, inst->staticInst); 564 inst->setPredTarg(nextPC); 565 inst->setPredTaken(false); 566 return false; 567 } 568 569 ThreadID tid = inst->threadNumber; 570 predict_taken = branchPred.predict(inst, nextPC, tid); 571 572 if (predict_taken) { 573 DPRINTF(Fetch, "[tid:%i]: [sn:%i]: Branch predicted to be taken to %s.\n", 574 tid, inst->seqNum, nextPC); 575 } else { 576 DPRINTF(Fetch, "[tid:%i]: [sn:%i]:Branch predicted to be not taken.\n", 577 tid, inst->seqNum); 578 } 579 580 DPRINTF(Fetch, "[tid:%i]: [sn:%i] Branch predicted to go to %s.\n", 581 tid, inst->seqNum, nextPC); 582 inst->setPredTarg(nextPC); 583 inst->setPredTaken(predict_taken); 584 585 ++fetchedBranches; 586 587 if (predict_taken) { 588 ++predictedBranches; 589 } 590 591 return predict_taken; 592} 593 594template <class Impl> 595bool 596DefaultFetch<Impl>::fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc) 597{ 598 Fault fault = NoFault; 599 600 // @todo: not sure if these should block translation. 601 //AlphaDep 602 if (cacheBlocked) { 603 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n", 604 tid); 605 return false; 606 } else if (isSwitchedOut()) { 607 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, switched out\n", 608 tid); 609 return false; 610 } else if (checkInterrupt(pc)) { 611 // Hold off fetch from getting new instructions when: 612 // Cache is blocked, or 613 // while an interrupt is pending and we're not in PAL mode, or 614 // fetch is switched out. 615 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n", 616 tid); 617 return false; 618 } 619 620 // Align the fetch address so it's at the start of a cache block. 621 Addr block_PC = icacheBlockAlignPC(vaddr); 622 623 DPRINTF(Fetch, "[tid:%i] Fetching cache line %#x for addr %#x\n", 624 tid, block_PC, vaddr); 625 626 // Setup the memReq to do a read of the first instruction's address. 627 // Set the appropriate read size and flags as well. 628 // Build request here. 629 RequestPtr mem_req = 630 new Request(tid, block_PC, cacheBlkSize, Request::INST_FETCH, 631 pc, cpu->thread[tid]->contextId(), tid); 632 633 memReq[tid] = mem_req; 634 635 // Initiate translation of the icache block 636 fetchStatus[tid] = ItlbWait; 637 FetchTranslation *trans = new FetchTranslation(this); 638 cpu->itb->translateTiming(mem_req, cpu->thread[tid]->getTC(), 639 trans, BaseTLB::Execute); 640 return true; 641} 642 643template <class Impl> 644void 645DefaultFetch<Impl>::finishTranslation(Fault fault, RequestPtr mem_req) 646{ 647 ThreadID tid = mem_req->threadId(); 648 Addr block_PC = mem_req->getVaddr(); 649 650 // Wake up CPU if it was idle 651 cpu->wakeCPU(); 652 653 if (fetchStatus[tid] != ItlbWait || mem_req != memReq[tid] || 654 mem_req->getVaddr() != memReq[tid]->getVaddr() || isSwitchedOut()) { 655 DPRINTF(Fetch, "[tid:%i] Ignoring itlb completed after squash\n", 656 tid); 657 ++fetchTlbSquashes; 658 delete mem_req; 659 return; 660 } 661 662 663 // If translation was successful, attempt to read the icache block. 664 if (fault == NoFault) { 665 // Check that we're not going off into random memory 666 // If we have, just wait around for commit to squash something and put 667 // us on the right track 668 if (!cpu->system->isMemory(mem_req->getPaddr())) { 669 warn("Address %#x is outside of physical memory, stopping fetch\n", 670 mem_req->getPaddr()); 671 fetchStatus[tid] = NoGoodAddr; 672 delete mem_req; 673 memReq[tid] = NULL; 674 return; 675 } 676 677 // Build packet here. 678 PacketPtr data_pkt = new Packet(mem_req, 679 MemCmd::ReadReq, Packet::Broadcast); 680 data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]); 681 682 cacheDataPC[tid] = block_PC; 683 cacheDataValid[tid] = false; 684 DPRINTF(Fetch, "Fetch: Doing instruction read.\n"); 685 686 fetchedCacheLines++; 687 688 // Access the cache. 689 if (!icachePort->sendTiming(data_pkt)) { 690 assert(retryPkt == NULL); 691 assert(retryTid == InvalidThreadID); 692 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid); 693 694 fetchStatus[tid] = IcacheWaitRetry; 695 retryPkt = data_pkt; 696 retryTid = tid; 697 cacheBlocked = true; 698 } else { 699 DPRINTF(Fetch, "[tid:%i]: Doing Icache access.\n", tid); 700 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache " 701 "response.\n", tid); 702 703 lastIcacheStall[tid] = curTick(); 704 fetchStatus[tid] = IcacheWaitResponse; 705 } 706 } else { 707 if (!(numInst < fetchWidth)) { 708 assert(!finishTranslationEvent.scheduled()); 709 finishTranslationEvent.setFault(fault); 710 finishTranslationEvent.setReq(mem_req); 711 cpu->schedule(finishTranslationEvent, cpu->nextCycle(curTick() + cpu->ticks(1))); 712 return; 713 } 714 DPRINTF(Fetch, "[tid:%i] Got back req with addr %#x but expected %#x\n", 715 tid, mem_req->getVaddr(), memReq[tid]->getVaddr()); 716 // Translation faulted, icache request won't be sent. 717 delete mem_req; 718 memReq[tid] = NULL; 719 720 // Send the fault to commit. This thread will not do anything 721 // until commit handles the fault. The only other way it can 722 // wake up is if a squash comes along and changes the PC. 723 TheISA::PCState fetchPC = pc[tid]; 724 725 DPRINTF(Fetch, "[tid:%i]: Translation faulted, building noop.\n", tid); 726 // We will use a nop in ordier to carry the fault. 727 DynInstPtr instruction = buildInst(tid, 728 StaticInstPtr(TheISA::NoopMachInst, fetchPC.instAddr()), 729 NULL, fetchPC, fetchPC, false); 730 731 instruction->setPredTarg(fetchPC); 732 instruction->fault = fault; 733 wroteToTimeBuffer = true; 734 735 DPRINTF(Activity, "Activity this cycle.\n"); 736 cpu->activityThisCycle(); 737 738 fetchStatus[tid] = TrapPending; 739 740 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n", tid); 741 DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %s.\n", 742 tid, fault->name(), pc[tid]); 743 } 744 _status = updateFetchStatus(); 745} 746 747template <class Impl> 748inline void 749DefaultFetch<Impl>::doSquash(const TheISA::PCState &newPC, ThreadID tid) 750{ 751 DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %s.\n", 752 tid, newPC); 753 754 pc[tid] = newPC; 755 fetchOffset[tid] = 0; 756 macroop[tid] = NULL; 757 predecoder.reset(); 758 759 // Clear the icache miss if it's outstanding. 760 if (fetchStatus[tid] == IcacheWaitResponse) { 761 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n", 762 tid); 763 memReq[tid] = NULL; 764 } else if (fetchStatus[tid] == ItlbWait) { 765 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding ITLB miss.\n", 766 tid); 767 memReq[tid] = NULL; 768 } 769 770 // Get rid of the retrying packet if it was from this thread. 771 if (retryTid == tid) { 772 assert(cacheBlocked); 773 if (retryPkt) { 774 delete retryPkt->req; 775 delete retryPkt; 776 } 777 retryPkt = NULL; 778 retryTid = InvalidThreadID; 779 } 780 781 fetchStatus[tid] = Squashing; 782 783 ++fetchSquashCycles; 784} 785 786template<class Impl> 787void 788DefaultFetch<Impl>::squashFromDecode(const TheISA::PCState &newPC, 789 const InstSeqNum &seq_num, ThreadID tid) 790{ 791 DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n", tid); 792 793 doSquash(newPC, tid); 794 795 // Tell the CPU to remove any instructions that are in flight between 796 // fetch and decode. 797 cpu->removeInstsUntil(seq_num, tid); 798} 799 800template<class Impl> 801bool 802DefaultFetch<Impl>::checkStall(ThreadID tid) const 803{ 804 bool ret_val = false; 805 806 if (cpu->contextSwitch) { 807 DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid); 808 ret_val = true; 809 } else if (stalls[tid].decode) { 810 DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid); 811 ret_val = true; 812 } else if (stalls[tid].rename) { 813 DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid); 814 ret_val = true; 815 } else if (stalls[tid].iew) { 816 DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid); 817 ret_val = true; 818 } else if (stalls[tid].commit) { 819 DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid); 820 ret_val = true; 821 } 822 823 return ret_val; 824} 825 826template<class Impl> 827typename DefaultFetch<Impl>::FetchStatus 828DefaultFetch<Impl>::updateFetchStatus() 829{ 830 //Check Running 831 list<ThreadID>::iterator threads = activeThreads->begin(); 832 list<ThreadID>::iterator end = activeThreads->end(); 833 834 while (threads != end) { 835 ThreadID tid = *threads++; 836 837 if (fetchStatus[tid] == Running || 838 fetchStatus[tid] == Squashing || 839 fetchStatus[tid] == IcacheAccessComplete) { 840 841 if (_status == Inactive) { 842 DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid); 843 844 if (fetchStatus[tid] == IcacheAccessComplete) { 845 DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache" 846 "completion\n",tid); 847 } 848 849 cpu->activateStage(O3CPU::FetchIdx); 850 } 851 852 return Active; 853 } 854 } 855 856 // Stage is switching from active to inactive, notify CPU of it. 857 if (_status == Active) { 858 DPRINTF(Activity, "Deactivating stage.\n"); 859 860 cpu->deactivateStage(O3CPU::FetchIdx); 861 } 862 863 return Inactive; 864} 865 866template <class Impl> 867void 868DefaultFetch<Impl>::squash(const TheISA::PCState &newPC, 869 const InstSeqNum &seq_num, DynInstPtr &squashInst, 870 ThreadID tid) 871{ 872 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n", tid); 873 874 doSquash(newPC, tid); 875 876 // Tell the CPU to remove any instructions that are not in the ROB. 877 cpu->removeInstsNotInROB(tid); 878} 879 880template <class Impl> 881void 882DefaultFetch<Impl>::tick() 883{ 884 list<ThreadID>::iterator threads = activeThreads->begin(); 885 list<ThreadID>::iterator end = activeThreads->end(); 886 bool status_change = false; 887 888 wroteToTimeBuffer = false; 889 890 for (ThreadID i = 0; i < Impl::MaxThreads; ++i) { 891 issuePipelinedIfetch[i] = false; 892 } 893 894 while (threads != end) { 895 ThreadID tid = *threads++; 896 897 // Check the signals for each thread to determine the proper status 898 // for each thread. 899 bool updated_status = checkSignalsAndUpdate(tid); 900 status_change = status_change || updated_status; 901 } 902 903 DPRINTF(Fetch, "Running stage.\n"); 904 905 #if FULL_SYSTEM 906 if (fromCommit->commitInfo[0].interruptPending) { 907 interruptPending = true; 908 } 909 910 if (fromCommit->commitInfo[0].clearInterrupt) { 911 interruptPending = false; 912 } 913#endif 914 915 for (threadFetched = 0; threadFetched < numFetchingThreads; 916 threadFetched++) { 917 // Fetch each of the actively fetching threads. 918 fetch(status_change); 919 } 920 921 // Record number of instructions fetched this cycle for distribution. 922 fetchNisnDist.sample(numInst); 923 924 if (status_change) { 925 // Change the fetch stage status if there was a status change. 926 _status = updateFetchStatus(); 927 } 928 929 // If there was activity this cycle, inform the CPU of it. 930 if (wroteToTimeBuffer || cpu->contextSwitch) { 931 DPRINTF(Activity, "Activity this cycle.\n"); 932 933 cpu->activityThisCycle(); 934 } 935 936 // Issue the next I-cache request if possible. 937 for (ThreadID i = 0; i < Impl::MaxThreads; ++i) { 938 if (issuePipelinedIfetch[i]) { 939 pipelineIcacheAccesses(i); 940 } 941 } 942 943 // Reset the number of the instruction we've fetched. 944 numInst = 0; 945} 946 947template <class Impl> 948bool 949DefaultFetch<Impl>::checkSignalsAndUpdate(ThreadID tid) 950{ 951 // Update the per thread stall statuses. 952 if (fromDecode->decodeBlock[tid]) { 953 stalls[tid].decode = true; 954 } 955 956 if (fromDecode->decodeUnblock[tid]) { 957 assert(stalls[tid].decode); 958 assert(!fromDecode->decodeBlock[tid]); 959 stalls[tid].decode = false; 960 } 961 962 if (fromRename->renameBlock[tid]) { 963 stalls[tid].rename = true; 964 } 965 966 if (fromRename->renameUnblock[tid]) { 967 assert(stalls[tid].rename); 968 assert(!fromRename->renameBlock[tid]); 969 stalls[tid].rename = false; 970 } 971 972 if (fromIEW->iewBlock[tid]) { 973 stalls[tid].iew = true; 974 } 975 976 if (fromIEW->iewUnblock[tid]) { 977 assert(stalls[tid].iew); 978 assert(!fromIEW->iewBlock[tid]); 979 stalls[tid].iew = false; 980 } 981 982 if (fromCommit->commitBlock[tid]) { 983 stalls[tid].commit = true; 984 } 985 986 if (fromCommit->commitUnblock[tid]) { 987 assert(stalls[tid].commit); 988 assert(!fromCommit->commitBlock[tid]); 989 stalls[tid].commit = false; 990 } 991 992 // Check squash signals from commit. 993 if (fromCommit->commitInfo[tid].squash) { 994 995 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash " 996 "from commit.\n",tid); 997 // In any case, squash. 998 squash(fromCommit->commitInfo[tid].pc, 999 fromCommit->commitInfo[tid].doneSeqNum, 1000 fromCommit->commitInfo[tid].squashInst, tid); 1001 1002 // If it was a branch mispredict on a control instruction, update the 1003 // branch predictor with that instruction, otherwise just kill the 1004 // invalid state we generated in after sequence number 1005 if (fromCommit->commitInfo[tid].mispredictInst && 1006 fromCommit->commitInfo[tid].mispredictInst->isControl()) { 1007 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum, 1008 fromCommit->commitInfo[tid].pc, 1009 fromCommit->commitInfo[tid].branchTaken, 1010 tid); 1011 } else { 1012 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum, 1013 tid); 1014 } 1015 1016 return true; 1017 } else if (fromCommit->commitInfo[tid].doneSeqNum) { 1018 // Update the branch predictor if it wasn't a squashed instruction 1019 // that was broadcasted. 1020 branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid); 1021 } 1022 1023 // Check ROB squash signals from commit. 1024 if (fromCommit->commitInfo[tid].robSquashing) { 1025 DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid); 1026 1027 // Continue to squash. 1028 fetchStatus[tid] = Squashing; 1029 1030 return true; 1031 } 1032 1033 // Check squash signals from decode. 1034 if (fromDecode->decodeInfo[tid].squash) { 1035 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash " 1036 "from decode.\n",tid); 1037 1038 // Update the branch predictor. 1039 if (fromDecode->decodeInfo[tid].branchMispredict) { 1040 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum, 1041 fromDecode->decodeInfo[tid].nextPC, 1042 fromDecode->decodeInfo[tid].branchTaken, 1043 tid); 1044 } else { 1045 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum, 1046 tid); 1047 } 1048 1049 if (fetchStatus[tid] != Squashing) { 1050 1051 TheISA::PCState nextPC = fromDecode->decodeInfo[tid].nextPC; 1052 DPRINTF(Fetch, "Squashing from decode with PC = %s\n", nextPC); 1053 // Squash unless we're already squashing 1054 squashFromDecode(fromDecode->decodeInfo[tid].nextPC, 1055 fromDecode->decodeInfo[tid].doneSeqNum, 1056 tid); 1057 1058 return true; 1059 } 1060 } 1061 1062 if (checkStall(tid) && 1063 fetchStatus[tid] != IcacheWaitResponse && 1064 fetchStatus[tid] != IcacheWaitRetry) { 1065 DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid); 1066 1067 fetchStatus[tid] = Blocked; 1068 1069 return true; 1070 } 1071 1072 if (fetchStatus[tid] == Blocked || 1073 fetchStatus[tid] == Squashing) { 1074 // Switch status to running if fetch isn't being told to block or 1075 // squash this cycle. 1076 DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n", 1077 tid); 1078 1079 fetchStatus[tid] = Running; 1080 1081 return true; 1082 } 1083 1084 // If we've reached this point, we have not gotten any signals that 1085 // cause fetch to change its status. Fetch remains the same as before. 1086 return false; 1087} 1088 1089template<class Impl> 1090typename Impl::DynInstPtr 1091DefaultFetch<Impl>::buildInst(ThreadID tid, StaticInstPtr staticInst, 1092 StaticInstPtr curMacroop, TheISA::PCState thisPC, 1093 TheISA::PCState nextPC, bool trace) 1094{ 1095 // Get a sequence number. 1096 InstSeqNum seq = cpu->getAndIncrementInstSeq(); 1097 1098 // Create a new DynInst from the instruction fetched. 1099 DynInstPtr instruction = 1100 new DynInst(staticInst, thisPC, nextPC, seq, cpu); 1101 instruction->setTid(tid); 1102 1103 instruction->setASID(tid); 1104 1105 instruction->setThreadState(cpu->thread[tid]); 1106 1107 DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x (%d) created " 1108 "[sn:%lli].\n", tid, thisPC.instAddr(), 1109 thisPC.microPC(), seq); 1110 1111 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", tid, 1112 instruction->staticInst-> 1113 disassemble(thisPC.instAddr())); 1114 1115#if TRACING_ON 1116 if (trace) { 1117 instruction->traceData = 1118 cpu->getTracer()->getInstRecord(curTick(), cpu->tcBase(tid), 1119 instruction->staticInst, thisPC, curMacroop); 1120 } 1121#else 1122 instruction->traceData = NULL; 1123#endif 1124 1125 // Add instruction to the CPU's list of instructions. 1126 instruction->setInstListIt(cpu->addInst(instruction)); 1127 1128 // Write the instruction to the first slot in the queue 1129 // that heads to decode. 1130 assert(numInst < fetchWidth); 1131 toDecode->insts[toDecode->size++] = instruction; 1132 1133 // Keep track of if we can take an interrupt at this boundary 1134 delayedCommit[tid] = instruction->isDelayedCommit(); 1135 1136 return instruction; 1137} 1138 1139template<class Impl> 1140void 1141DefaultFetch<Impl>::fetch(bool &status_change) 1142{ 1143 ////////////////////////////////////////// 1144 // Start actual fetch 1145 ////////////////////////////////////////// 1146 ThreadID tid = getFetchingThread(fetchPolicy); 1147 1148 if (tid == InvalidThreadID || drainPending) { 1149 // Breaks looping condition in tick() 1150 threadFetched = numFetchingThreads; 1151 1152 if (numThreads == 1) { // @todo Per-thread stats 1153 profileStall(0); 1154 } 1155 1156 return; 1157 } 1158 1159 DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid); 1160 1161 // The current PC. 1162 TheISA::PCState thisPC = pc[tid]; 1163 1164 Addr pcOffset = fetchOffset[tid]; 1165 Addr fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask; 1166 1167 bool inRom = isRomMicroPC(thisPC.microPC()); 1168 1169 // If returning from the delay of a cache miss, then update the status 1170 // to running, otherwise do the cache access. Possibly move this up 1171 // to tick() function. 1172 if (fetchStatus[tid] == IcacheAccessComplete) { 1173 DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n", tid); 1174 1175 fetchStatus[tid] = Running; 1176 status_change = true; 1177 } else if (fetchStatus[tid] == Running) { 1178 // Align the fetch PC so its at the start of a cache block. 1179 Addr block_PC = icacheBlockAlignPC(fetchAddr); 1180 1181 // If buffer is no longer valid or fetchAddr has moved to point 1182 // to the next cache block, AND we have no remaining ucode 1183 // from a macro-op, then start fetch from icache. 1184 if (!(cacheDataValid[tid] && block_PC == cacheDataPC[tid]) 1185 && !inRom && !macroop[tid]) { 1186 DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read " 1187 "instruction, starting at PC %s.\n", tid, thisPC); 1188 1189 fetchCacheLine(fetchAddr, tid, thisPC.instAddr()); 1190 1191 if (fetchStatus[tid] == IcacheWaitResponse) 1192 ++icacheStallCycles; 1193 else if (fetchStatus[tid] == ItlbWait) 1194 ++fetchTlbCycles; 1195 else 1196 ++fetchMiscStallCycles; 1197 return; 1198 } else if ((checkInterrupt(thisPC.instAddr()) && !delayedCommit[tid]) 1199 || isSwitchedOut()) { 1200 // Stall CPU if an interrupt is posted and we're not issuing 1201 // an delayed commit micro-op currently (delayed commit instructions 1202 // are not interruptable by interrupts, only faults) 1203 ++fetchMiscStallCycles; 1204 return; 1205 } 1206 } else { 1207 if (fetchStatus[tid] == Idle) { 1208 ++fetchIdleCycles; 1209 DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid); 1210 } 1211 1212 // Status is Idle, so fetch should do nothing. 1213 return; 1214 } 1215 1216 ++fetchCycles; 1217 1218 TheISA::PCState nextPC = thisPC; 1219 1220 StaticInstPtr staticInst = NULL; 1221 StaticInstPtr curMacroop = macroop[tid]; 1222 1223 // If the read of the first instruction was successful, then grab the 1224 // instructions from the rest of the cache line and put them into the 1225 // queue heading to decode. 1226 1227 DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to " 1228 "decode.\n", tid); 1229 1230 // Need to keep track of whether or not a predicted branch 1231 // ended this fetch block. 1232 bool predictedBranch = false; 1233 1234 TheISA::MachInst *cacheInsts = 1235 reinterpret_cast<TheISA::MachInst *>(cacheData[tid]); 1236 1237 const unsigned numInsts = cacheBlkSize / instSize; 1238 unsigned blkOffset = (fetchAddr - cacheDataPC[tid]) / instSize; 1239 1240 // Loop through instruction memory from the cache. 1241 // Keep issuing while we have not reached the end of the block or a 1242 // macroop is active and fetchWidth is available and branch is not 1243 // predicted taken 1244 while ((blkOffset < numInsts || curMacroop) && 1245 numInst < fetchWidth && !predictedBranch) { 1246 1247 // If we need to process more memory, do it now. 1248 if (!(curMacroop || inRom) && !predecoder.extMachInstReady()) { 1249 if (ISA_HAS_DELAY_SLOT && pcOffset == 0) { 1250 // Walk past any annulled delay slot instructions. 1251 Addr pcAddr = thisPC.instAddr() & BaseCPU::PCMask; 1252 while (fetchAddr != pcAddr && blkOffset < numInsts) { 1253 blkOffset++; 1254 fetchAddr += instSize; 1255 } 1256 if (blkOffset >= numInsts) 1257 break; 1258 } 1259 MachInst inst = TheISA::gtoh(cacheInsts[blkOffset]); 1260 1261 predecoder.setTC(cpu->thread[tid]->getTC()); 1262 predecoder.moreBytes(thisPC, fetchAddr, inst); 1263 1264 if (predecoder.needMoreBytes()) { 1265 blkOffset++; 1266 fetchAddr += instSize; 1267 pcOffset += instSize; 1268 } 1269 } 1270 1271 // Extract as many instructions and/or microops as we can from 1272 // the memory we've processed so far. 1273 do { 1274 if (!(curMacroop || inRom)) { 1275 if (predecoder.extMachInstReady()) { 1276 ExtMachInst extMachInst; 1277 1278 extMachInst = predecoder.getExtMachInst(thisPC); 1279 staticInst = StaticInstPtr(extMachInst, 1280 thisPC.instAddr()); 1281 1282 // Increment stat of fetched instructions. 1283 ++fetchedInsts; 1284 1285 if (staticInst->isMacroop()) { 1286 curMacroop = staticInst; 1287 } else { 1288 pcOffset = 0; 1289 } 1290 } else { 1291 // We need more bytes for this instruction so blkOffset and 1292 // pcOffset will be updated 1293 break; 1294 } 1295 } 1296 if (curMacroop || inRom) { 1297 if (inRom) { 1298 staticInst = cpu->microcodeRom.fetchMicroop( 1299 thisPC.microPC(), curMacroop); 1300 } else { 1301 staticInst = curMacroop->fetchMicroop(thisPC.microPC()); 1302 } 1303 if (staticInst->isLastMicroop()) { 1304 curMacroop = NULL; 1305 pcOffset = 0; 1306 } 1307 } 1308 1309 DynInstPtr instruction = 1310 buildInst(tid, staticInst, curMacroop, 1311 thisPC, nextPC, true); 1312 1313 numInst++; 1314 1315 nextPC = thisPC; 1316 1317 // If we're branching after this instruction, quite fetching 1318 // from the same block then. 1319 predictedBranch |= thisPC.branching(); 1320 predictedBranch |= 1321 lookupAndUpdateNextPC(instruction, nextPC); 1322 if (predictedBranch) { 1323 DPRINTF(Fetch, "Branch detected with PC = %s\n", thisPC); 1324 } 1325 1326 // Move to the next instruction, unless we have a branch. 1327 thisPC = nextPC; 1328 1329 if (instruction->isQuiesce()) { 1330 DPRINTF(Fetch, 1331 "Quiesce instruction encountered, halting fetch!"); 1332 fetchStatus[tid] = QuiescePending; 1333 status_change = true; 1334 break; 1335 } 1336 } while ((curMacroop || predecoder.extMachInstReady()) && 1337 numInst < fetchWidth); 1338 } 1339 1340 if (predictedBranch) { 1341 DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch " 1342 "instruction encountered.\n", tid); 1343 } else if (numInst >= fetchWidth) { 1344 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth " 1345 "for this cycle.\n", tid); 1346 } else if (blkOffset >= cacheBlkSize) { 1347 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache " 1348 "block.\n", tid); 1349 } 1350 1351 macroop[tid] = curMacroop; 1352 fetchOffset[tid] = pcOffset; 1353 1354 if (numInst > 0) { 1355 wroteToTimeBuffer = true; 1356 } 1357 1358 pc[tid] = thisPC; 1359 1360 // pipeline a fetch if we're crossing a cache boundary and not in 1361 // a state that would preclude fetching 1362 fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask; 1363 Addr block_PC = icacheBlockAlignPC(fetchAddr); 1364 issuePipelinedIfetch[tid] = block_PC != cacheDataPC[tid] && 1365 fetchStatus[tid] != IcacheWaitResponse && 1366 fetchStatus[tid] != ItlbWait && 1367 fetchStatus[tid] != IcacheWaitRetry && 1368 fetchStatus[tid] != QuiescePending && 1369 !curMacroop; 1370} 1371 1372template<class Impl> 1373void 1374DefaultFetch<Impl>::recvRetry() 1375{ 1376 if (retryPkt != NULL) { 1377 assert(cacheBlocked); 1378 assert(retryTid != InvalidThreadID); 1379 assert(fetchStatus[retryTid] == IcacheWaitRetry); 1380 1381 if (icachePort->sendTiming(retryPkt)) { 1382 fetchStatus[retryTid] = IcacheWaitResponse; 1383 retryPkt = NULL; 1384 retryTid = InvalidThreadID; 1385 cacheBlocked = false; 1386 } 1387 } else { 1388 assert(retryTid == InvalidThreadID); 1389 // Access has been squashed since it was sent out. Just clear 1390 // the cache being blocked. 1391 cacheBlocked = false; 1392 } 1393} 1394 1395/////////////////////////////////////// 1396// // 1397// SMT FETCH POLICY MAINTAINED HERE // 1398// // 1399/////////////////////////////////////// 1400template<class Impl> 1401ThreadID 1402DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority) 1403{ 1404 if (numThreads > 1) { 1405 switch (fetch_priority) { 1406 1407 case SingleThread: 1408 return 0; 1409 1410 case RoundRobin: 1411 return roundRobin(); 1412 1413 case IQ: 1414 return iqCount(); 1415 1416 case LSQ: 1417 return lsqCount(); 1418 1419 case Branch: 1420 return branchCount(); 1421 1422 default: 1423 return InvalidThreadID; 1424 } 1425 } else { 1426 list<ThreadID>::iterator thread = activeThreads->begin(); 1427 if (thread == activeThreads->end()) { 1428 return InvalidThreadID; 1429 } 1430 1431 ThreadID tid = *thread; 1432 1433 if (fetchStatus[tid] == Running || 1434 fetchStatus[tid] == IcacheAccessComplete || 1435 fetchStatus[tid] == Idle) { 1436 return tid; 1437 } else { 1438 return InvalidThreadID; 1439 } 1440 } 1441} 1442 1443 1444template<class Impl> 1445ThreadID 1446DefaultFetch<Impl>::roundRobin() 1447{ 1448 list<ThreadID>::iterator pri_iter = priorityList.begin(); 1449 list<ThreadID>::iterator end = priorityList.end(); 1450 1451 ThreadID high_pri; 1452 1453 while (pri_iter != end) { 1454 high_pri = *pri_iter; 1455 1456 assert(high_pri <= numThreads); 1457 1458 if (fetchStatus[high_pri] == Running || 1459 fetchStatus[high_pri] == IcacheAccessComplete || 1460 fetchStatus[high_pri] == Idle) { 1461 1462 priorityList.erase(pri_iter); 1463 priorityList.push_back(high_pri); 1464 1465 return high_pri; 1466 } 1467 1468 pri_iter++; 1469 } 1470 1471 return InvalidThreadID; 1472} 1473 1474template<class Impl> 1475ThreadID 1476DefaultFetch<Impl>::iqCount() 1477{ 1478 std::priority_queue<unsigned> PQ; 1479 std::map<unsigned, ThreadID> threadMap; 1480 1481 list<ThreadID>::iterator threads = activeThreads->begin(); 1482 list<ThreadID>::iterator end = activeThreads->end(); 1483 1484 while (threads != end) { 1485 ThreadID tid = *threads++; 1486 unsigned iqCount = fromIEW->iewInfo[tid].iqCount; 1487 1488 PQ.push(iqCount); 1489 threadMap[iqCount] = tid; 1490 } 1491 1492 while (!PQ.empty()) { 1493 ThreadID high_pri = threadMap[PQ.top()]; 1494 1495 if (fetchStatus[high_pri] == Running || 1496 fetchStatus[high_pri] == IcacheAccessComplete || 1497 fetchStatus[high_pri] == Idle) 1498 return high_pri; 1499 else 1500 PQ.pop(); 1501 1502 } 1503 1504 return InvalidThreadID; 1505} 1506 1507template<class Impl> 1508ThreadID 1509DefaultFetch<Impl>::lsqCount() 1510{ 1511 std::priority_queue<unsigned> PQ; 1512 std::map<unsigned, ThreadID> threadMap; 1513 1514 list<ThreadID>::iterator threads = activeThreads->begin(); 1515 list<ThreadID>::iterator end = activeThreads->end(); 1516 1517 while (threads != end) { 1518 ThreadID tid = *threads++; 1519 unsigned ldstqCount = fromIEW->iewInfo[tid].ldstqCount; 1520 1521 PQ.push(ldstqCount); 1522 threadMap[ldstqCount] = tid; 1523 } 1524 1525 while (!PQ.empty()) { 1526 ThreadID high_pri = threadMap[PQ.top()]; 1527 1528 if (fetchStatus[high_pri] == Running || 1529 fetchStatus[high_pri] == IcacheAccessComplete || 1530 fetchStatus[high_pri] == Idle) 1531 return high_pri; 1532 else 1533 PQ.pop(); 1534 } 1535 1536 return InvalidThreadID; 1537} 1538 1539template<class Impl> 1540ThreadID 1541DefaultFetch<Impl>::branchCount() 1542{ 1543#if 0 1544 list<ThreadID>::iterator thread = activeThreads->begin(); 1545 assert(thread != activeThreads->end()); 1546 ThreadID tid = *thread; 1547#endif 1548 1549 panic("Branch Count Fetch policy unimplemented\n"); 1550 return InvalidThreadID; 1551} 1552 1553template<class Impl> 1554void 1555DefaultFetch<Impl>::pipelineIcacheAccesses(ThreadID tid) 1556{ 1557 if (!issuePipelinedIfetch[tid]) { 1558 return; 1559 } 1560 1561 // The next PC to access. 1562 TheISA::PCState thisPC = pc[tid]; 1563 1564 if (isRomMicroPC(thisPC.microPC())) { 1565 return; 1566 } 1567 1568 Addr pcOffset = fetchOffset[tid]; 1569 Addr fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask; 1570 1571 // Align the fetch PC so its at the start of a cache block. 1572 Addr block_PC = icacheBlockAlignPC(fetchAddr); 1573 1574 // Unless buffer already got the block, fetch it from icache. 1575 if (!(cacheDataValid[tid] && block_PC == cacheDataPC[tid])) { 1576 DPRINTF(Fetch, "[tid:%i]: Issuing a pipelined I-cache access, " 1577 "starting at PC %s.\n", tid, thisPC); 1578 1579 fetchCacheLine(fetchAddr, tid, thisPC.instAddr()); 1580 } 1581} 1582 1583template<class Impl> 1584void 1585DefaultFetch<Impl>::profileStall(ThreadID tid) { 1586 DPRINTF(Fetch,"There are no more threads available to fetch from.\n"); 1587 1588 // @todo Per-thread stats 1589 1590 if (drainPending) { 1591 ++fetchPendingDrainCycles; 1592 DPRINTF(Fetch, "Fetch is waiting for a drain!\n"); 1593 } else if (activeThreads->empty()) { 1594 ++fetchNoActiveThreadStallCycles; 1595 DPRINTF(Fetch, "Fetch has no active thread!\n"); 1596 } else if (fetchStatus[tid] == Blocked) { 1597 ++fetchBlockedCycles; 1598 DPRINTF(Fetch, "[tid:%i]: Fetch is blocked!\n", tid); 1599 } else if (fetchStatus[tid] == Squashing) { 1600 ++fetchSquashCycles; 1601 DPRINTF(Fetch, "[tid:%i]: Fetch is squashing!\n", tid); 1602 } else if (fetchStatus[tid] == IcacheWaitResponse) { 1603 ++icacheStallCycles; 1604 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n", 1605 tid); 1606 } else if (fetchStatus[tid] == ItlbWait) { 1607 ++fetchTlbCycles; 1608 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting ITLB walk to " 1609 "finish!\n", tid); 1610 } else if (fetchStatus[tid] == TrapPending) { 1611 ++fetchPendingTrapStallCycles; 1612 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting for a pending trap!\n", 1613 tid); 1614 } else if (fetchStatus[tid] == QuiescePending) { 1615 ++fetchPendingQuiesceStallCycles; 1616 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting for a pending quiesce " 1617 "instruction!\n", tid); 1618 } else if (fetchStatus[tid] == IcacheWaitRetry) { 1619 ++fetchIcacheWaitRetryStallCycles; 1620 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting for an I-cache retry!\n", 1621 tid); 1622 } else if (fetchStatus[tid] == NoGoodAddr) { 1623 DPRINTF(Fetch, "[tid:%i]: Fetch predicted non-executable address\n", 1624 tid); 1625 } else { 1626 DPRINTF(Fetch, "[tid:%i]: Unexpected fetch stall reason (Status: %i).\n", 1627 tid, fetchStatus[tid]); 1628 } 1629} 1630