fetch_impl.hh revision 8138:f08692f2932e
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 * Korey Sewell 42 */ 43 44#include <algorithm> 45#include <cstring> 46 47#include "arch/isa_traits.hh" 48#include "arch/utility.hh" 49#include "base/types.hh" 50#include "config/the_isa.hh" 51#include "config/use_checker.hh" 52#include "cpu/checker/cpu.hh" 53#include "cpu/exetrace.hh" 54#include "cpu/o3/fetch.hh" 55#include "mem/packet.hh" 56#include "mem/request.hh" 57#include "params/DerivO3CPU.hh" 58#include "sim/byteswap.hh" 59#include "sim/core.hh" 60 61#if FULL_SYSTEM 62#include "arch/tlb.hh" 63#include "arch/vtophys.hh" 64#include "sim/system.hh" 65#endif // FULL_SYSTEM 66 67using namespace std; 68 69template<class Impl> 70void 71DefaultFetch<Impl>::IcachePort::setPeer(Port *port) 72{ 73 Port::setPeer(port); 74 75 fetch->setIcache(); 76} 77 78template<class Impl> 79Tick 80DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt) 81{ 82 panic("DefaultFetch doesn't expect recvAtomic callback!"); 83 return curTick(); 84} 85 86template<class Impl> 87void 88DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt) 89{ 90 DPRINTF(Fetch, "DefaultFetch doesn't update its state from a " 91 "functional call."); 92} 93 94template<class Impl> 95void 96DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status) 97{ 98 if (status == RangeChange) { 99 if (!snoopRangeSent) { 100 snoopRangeSent = true; 101 sendStatusChange(Port::RangeChange); 102 } 103 return; 104 } 105 106 panic("DefaultFetch doesn't expect recvStatusChange callback!"); 107} 108 109template<class Impl> 110bool 111DefaultFetch<Impl>::IcachePort::recvTiming(PacketPtr pkt) 112{ 113 DPRINTF(Fetch, "Received timing\n"); 114 if (pkt->isResponse()) { 115 // We shouldn't ever get a block in ownership state 116 assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted())); 117 118 fetch->processCacheCompletion(pkt); 119 } 120 //else Snooped a coherence request, just return 121 return true; 122} 123 124template<class Impl> 125void 126DefaultFetch<Impl>::IcachePort::recvRetry() 127{ 128 fetch->recvRetry(); 129} 130 131template<class Impl> 132DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params) 133 : cpu(_cpu), 134 branchPred(params), 135 predecoder(NULL), 136 decodeToFetchDelay(params->decodeToFetchDelay), 137 renameToFetchDelay(params->renameToFetchDelay), 138 iewToFetchDelay(params->iewToFetchDelay), 139 commitToFetchDelay(params->commitToFetchDelay), 140 fetchWidth(params->fetchWidth), 141 cacheBlocked(false), 142 retryPkt(NULL), 143 retryTid(InvalidThreadID), 144 numThreads(params->numThreads), 145 numFetchingThreads(params->smtNumFetchingThreads), 146 interruptPending(false), 147 drainPending(false), 148 switchedOut(false) 149{ 150 if (numThreads > Impl::MaxThreads) 151 fatal("numThreads (%d) is larger than compiled limit (%d),\n" 152 "\tincrease MaxThreads in src/cpu/o3/impl.hh\n", 153 numThreads, static_cast<int>(Impl::MaxThreads)); 154 155 // Set fetch stage's status to inactive. 156 _status = Inactive; 157 158 std::string policy = params->smtFetchPolicy; 159 160 // Convert string to lowercase 161 std::transform(policy.begin(), policy.end(), policy.begin(), 162 (int(*)(int)) tolower); 163 164 // Figure out fetch policy 165 if (policy == "singlethread") { 166 fetchPolicy = SingleThread; 167 if (numThreads > 1) 168 panic("Invalid Fetch Policy for a SMT workload."); 169 } else if (policy == "roundrobin") { 170 fetchPolicy = RoundRobin; 171 DPRINTF(Fetch, "Fetch policy set to Round Robin\n"); 172 } else if (policy == "branch") { 173 fetchPolicy = Branch; 174 DPRINTF(Fetch, "Fetch policy set to Branch Count\n"); 175 } else if (policy == "iqcount") { 176 fetchPolicy = IQ; 177 DPRINTF(Fetch, "Fetch policy set to IQ count\n"); 178 } else if (policy == "lsqcount") { 179 fetchPolicy = LSQ; 180 DPRINTF(Fetch, "Fetch policy set to LSQ count\n"); 181 } else { 182 fatal("Invalid Fetch Policy. Options Are: {SingleThread," 183 " RoundRobin,LSQcount,IQcount}\n"); 184 } 185 186 // Get the size of an instruction. 187 instSize = sizeof(TheISA::MachInst); 188 189 // Name is finally available, so create the port. 190 icachePort = new IcachePort(this); 191 192 icachePort->snoopRangeSent = false; 193 194#if USE_CHECKER 195 if (cpu->checker) { 196 cpu->checker->setIcachePort(icachePort); 197 } 198#endif 199} 200 201template <class Impl> 202std::string 203DefaultFetch<Impl>::name() const 204{ 205 return cpu->name() + ".fetch"; 206} 207 208template <class Impl> 209void 210DefaultFetch<Impl>::regStats() 211{ 212 icacheStallCycles 213 .name(name() + ".icacheStallCycles") 214 .desc("Number of cycles fetch is stalled on an Icache miss") 215 .prereq(icacheStallCycles); 216 217 fetchedInsts 218 .name(name() + ".Insts") 219 .desc("Number of instructions fetch has processed") 220 .prereq(fetchedInsts); 221 222 fetchedBranches 223 .name(name() + ".Branches") 224 .desc("Number of branches that fetch encountered") 225 .prereq(fetchedBranches); 226 227 predictedBranches 228 .name(name() + ".predictedBranches") 229 .desc("Number of branches that fetch has predicted taken") 230 .prereq(predictedBranches); 231 232 fetchCycles 233 .name(name() + ".Cycles") 234 .desc("Number of cycles fetch has run and was not squashing or" 235 " blocked") 236 .prereq(fetchCycles); 237 238 fetchSquashCycles 239 .name(name() + ".SquashCycles") 240 .desc("Number of cycles fetch has spent squashing") 241 .prereq(fetchSquashCycles); 242 243 fetchTlbCycles 244 .name(name() + ".TlbCycles") 245 .desc("Number of cycles fetch has spent waiting for tlb") 246 .prereq(fetchTlbCycles); 247 248 fetchIdleCycles 249 .name(name() + ".IdleCycles") 250 .desc("Number of cycles fetch was idle") 251 .prereq(fetchIdleCycles); 252 253 fetchBlockedCycles 254 .name(name() + ".BlockedCycles") 255 .desc("Number of cycles fetch has spent blocked") 256 .prereq(fetchBlockedCycles); 257 258 fetchedCacheLines 259 .name(name() + ".CacheLines") 260 .desc("Number of cache lines fetched") 261 .prereq(fetchedCacheLines); 262 263 fetchMiscStallCycles 264 .name(name() + ".MiscStallCycles") 265 .desc("Number of cycles fetch has spent waiting on interrupts, or " 266 "bad addresses, or out of MSHRs") 267 .prereq(fetchMiscStallCycles); 268 269 fetchIcacheSquashes 270 .name(name() + ".IcacheSquashes") 271 .desc("Number of outstanding Icache misses that were squashed") 272 .prereq(fetchIcacheSquashes); 273 274 fetchTlbSquashes 275 .name(name() + ".ItlbSquashes") 276 .desc("Number of outstanding ITLB misses that were squashed") 277 .prereq(fetchTlbSquashes); 278 279 fetchNisnDist 280 .init(/* base value */ 0, 281 /* last value */ fetchWidth, 282 /* bucket size */ 1) 283 .name(name() + ".rateDist") 284 .desc("Number of instructions fetched each cycle (Total)") 285 .flags(Stats::pdf); 286 287 idleRate 288 .name(name() + ".idleRate") 289 .desc("Percent of cycles fetch was idle") 290 .prereq(idleRate); 291 idleRate = fetchIdleCycles * 100 / cpu->numCycles; 292 293 branchRate 294 .name(name() + ".branchRate") 295 .desc("Number of branch fetches per cycle") 296 .flags(Stats::total); 297 branchRate = fetchedBranches / cpu->numCycles; 298 299 fetchRate 300 .name(name() + ".rate") 301 .desc("Number of inst fetches per cycle") 302 .flags(Stats::total); 303 fetchRate = fetchedInsts / cpu->numCycles; 304 305 branchPred.regStats(); 306} 307 308template<class Impl> 309void 310DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer) 311{ 312 timeBuffer = time_buffer; 313 314 // Create wires to get information from proper places in time buffer. 315 fromDecode = timeBuffer->getWire(-decodeToFetchDelay); 316 fromRename = timeBuffer->getWire(-renameToFetchDelay); 317 fromIEW = timeBuffer->getWire(-iewToFetchDelay); 318 fromCommit = timeBuffer->getWire(-commitToFetchDelay); 319} 320 321template<class Impl> 322void 323DefaultFetch<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr) 324{ 325 activeThreads = at_ptr; 326} 327 328template<class Impl> 329void 330DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 331{ 332 fetchQueue = fq_ptr; 333 334 // Create wire to write information to proper place in fetch queue. 335 toDecode = fetchQueue->getWire(0); 336} 337 338template<class Impl> 339void 340DefaultFetch<Impl>::initStage() 341{ 342 // Setup PC and nextPC with initial state. 343 for (ThreadID tid = 0; tid < numThreads; tid++) { 344 pc[tid] = cpu->pcState(tid); 345 fetchOffset[tid] = 0; 346 macroop[tid] = NULL; 347 } 348 349 for (ThreadID tid = 0; tid < numThreads; tid++) { 350 351 fetchStatus[tid] = Running; 352 353 priorityList.push_back(tid); 354 355 memReq[tid] = NULL; 356 357 stalls[tid].decode = false; 358 stalls[tid].rename = false; 359 stalls[tid].iew = false; 360 stalls[tid].commit = false; 361 } 362 363 // Schedule fetch to get the correct PC from the CPU 364 // scheduleFetchStartupEvent(1); 365 366 // Fetch needs to start fetching instructions at the very beginning, 367 // so it must start up in active state. 368 switchToActive(); 369} 370 371template<class Impl> 372void 373DefaultFetch<Impl>::setIcache() 374{ 375 // Size of cache block. 376 cacheBlkSize = icachePort->peerBlockSize(); 377 378 // Create mask to get rid of offset bits. 379 cacheBlkMask = (cacheBlkSize - 1); 380 381 for (ThreadID tid = 0; tid < numThreads; tid++) { 382 // Create space to store a cache line. 383 cacheData[tid] = new uint8_t[cacheBlkSize]; 384 cacheDataPC[tid] = 0; 385 cacheDataValid[tid] = false; 386 } 387} 388 389template<class Impl> 390void 391DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt) 392{ 393 ThreadID tid = pkt->req->threadId(); 394 395 DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n", tid); 396 397 assert(!pkt->wasNacked()); 398 399 // Only change the status if it's still waiting on the icache access 400 // to return. 401 if (fetchStatus[tid] != IcacheWaitResponse || 402 pkt->req != memReq[tid] || 403 isSwitchedOut()) { 404 ++fetchIcacheSquashes; 405 delete pkt->req; 406 delete pkt; 407 return; 408 } 409 410 memcpy(cacheData[tid], pkt->getPtr<uint8_t>(), cacheBlkSize); 411 cacheDataValid[tid] = true; 412 413 if (!drainPending) { 414 // Wake up the CPU (if it went to sleep and was waiting on 415 // this completion event). 416 cpu->wakeCPU(); 417 418 DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n", 419 tid); 420 421 switchToActive(); 422 } 423 424 // Only switch to IcacheAccessComplete if we're not stalled as well. 425 if (checkStall(tid)) { 426 fetchStatus[tid] = Blocked; 427 } else { 428 fetchStatus[tid] = IcacheAccessComplete; 429 } 430 431 // Reset the mem req to NULL. 432 delete pkt->req; 433 delete pkt; 434 memReq[tid] = NULL; 435} 436 437template <class Impl> 438bool 439DefaultFetch<Impl>::drain() 440{ 441 // Fetch is ready to drain at any time. 442 cpu->signalDrained(); 443 drainPending = true; 444 return true; 445} 446 447template <class Impl> 448void 449DefaultFetch<Impl>::resume() 450{ 451 drainPending = false; 452} 453 454template <class Impl> 455void 456DefaultFetch<Impl>::switchOut() 457{ 458 switchedOut = true; 459 // Branch predictor needs to have its state cleared. 460 branchPred.switchOut(); 461} 462 463template <class Impl> 464void 465DefaultFetch<Impl>::takeOverFrom() 466{ 467 // Reset all state 468 for (ThreadID i = 0; i < Impl::MaxThreads; ++i) { 469 stalls[i].decode = 0; 470 stalls[i].rename = 0; 471 stalls[i].iew = 0; 472 stalls[i].commit = 0; 473 pc[i] = cpu->pcState(i); 474 fetchStatus[i] = Running; 475 } 476 numInst = 0; 477 wroteToTimeBuffer = false; 478 _status = Inactive; 479 switchedOut = false; 480 interruptPending = false; 481 branchPred.takeOverFrom(); 482} 483 484template <class Impl> 485void 486DefaultFetch<Impl>::wakeFromQuiesce() 487{ 488 DPRINTF(Fetch, "Waking up from quiesce\n"); 489 // Hopefully this is safe 490 // @todo: Allow other threads to wake from quiesce. 491 fetchStatus[0] = Running; 492} 493 494template <class Impl> 495inline void 496DefaultFetch<Impl>::switchToActive() 497{ 498 if (_status == Inactive) { 499 DPRINTF(Activity, "Activating stage.\n"); 500 501 cpu->activateStage(O3CPU::FetchIdx); 502 503 _status = Active; 504 } 505} 506 507template <class Impl> 508inline void 509DefaultFetch<Impl>::switchToInactive() 510{ 511 if (_status == Active) { 512 DPRINTF(Activity, "Deactivating stage.\n"); 513 514 cpu->deactivateStage(O3CPU::FetchIdx); 515 516 _status = Inactive; 517 } 518} 519 520template <class Impl> 521bool 522DefaultFetch<Impl>::lookupAndUpdateNextPC( 523 DynInstPtr &inst, TheISA::PCState &nextPC) 524{ 525 // Do branch prediction check here. 526 // A bit of a misnomer...next_PC is actually the current PC until 527 // this function updates it. 528 bool predict_taken; 529 530 if (!inst->isControl()) { 531 TheISA::advancePC(nextPC, inst->staticInst); 532 inst->setPredTarg(nextPC); 533 inst->setPredTaken(false); 534 return false; 535 } 536 537 ThreadID tid = inst->threadNumber; 538 predict_taken = branchPred.predict(inst, nextPC, tid); 539 540 if (predict_taken) { 541 DPRINTF(Fetch, "[tid:%i]: [sn:%i]: Branch predicted to be taken to %s.\n", 542 tid, inst->seqNum, nextPC); 543 } else { 544 DPRINTF(Fetch, "[tid:%i]: [sn:%i]:Branch predicted to be not taken.\n", 545 tid, inst->seqNum); 546 } 547 548 DPRINTF(Fetch, "[tid:%i]: [sn:%i] Branch predicted to go to %s.\n", 549 tid, inst->seqNum, nextPC); 550 inst->setPredTarg(nextPC); 551 inst->setPredTaken(predict_taken); 552 553 ++fetchedBranches; 554 555 if (predict_taken) { 556 ++predictedBranches; 557 } 558 559 return predict_taken; 560} 561 562template <class Impl> 563bool 564DefaultFetch<Impl>::fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc) 565{ 566 Fault fault = NoFault; 567 568 // @todo: not sure if these should block translation. 569 //AlphaDep 570 if (cacheBlocked) { 571 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n", 572 tid); 573 return false; 574 } else if (isSwitchedOut()) { 575 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, switched out\n", 576 tid); 577 return false; 578 } else if (checkInterrupt(pc)) { 579 // Hold off fetch from getting new instructions when: 580 // Cache is blocked, or 581 // while an interrupt is pending and we're not in PAL mode, or 582 // fetch is switched out. 583 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n", 584 tid); 585 return false; 586 } 587 588 // Align the fetch address so it's at the start of a cache block. 589 Addr block_PC = icacheBlockAlignPC(vaddr); 590 591 DPRINTF(Fetch, "[tid:%i] Fetching cache line %#x for addr %#x\n", 592 tid, block_PC, vaddr); 593 594 // Setup the memReq to do a read of the first instruction's address. 595 // Set the appropriate read size and flags as well. 596 // Build request here. 597 RequestPtr mem_req = 598 new Request(tid, block_PC, cacheBlkSize, Request::INST_FETCH, 599 pc, cpu->thread[tid]->contextId(), tid); 600 601 memReq[tid] = mem_req; 602 603 // Initiate translation of the icache block 604 fetchStatus[tid] = ItlbWait; 605 FetchTranslation *trans = new FetchTranslation(this); 606 cpu->itb->translateTiming(mem_req, cpu->thread[tid]->getTC(), 607 trans, BaseTLB::Execute); 608 return true; 609} 610 611template <class Impl> 612void 613DefaultFetch<Impl>::finishTranslation(Fault fault, RequestPtr mem_req) 614{ 615 ThreadID tid = mem_req->threadId(); 616 Addr block_PC = mem_req->getVaddr(); 617 618 // Wake up CPU if it was idle 619 cpu->wakeCPU(); 620 621 if (fetchStatus[tid] != ItlbWait || mem_req != memReq[tid] || 622 mem_req->getVaddr() != memReq[tid]->getVaddr() || isSwitchedOut()) { 623 DPRINTF(Fetch, "[tid:%i] Ignoring itlb completed after squash\n", 624 tid); 625 ++fetchTlbSquashes; 626 delete mem_req; 627 return; 628 } 629 630 631 // If translation was successful, attempt to read the icache block. 632 if (fault == NoFault) { 633 // Build packet here. 634 PacketPtr data_pkt = new Packet(mem_req, 635 MemCmd::ReadReq, Packet::Broadcast); 636 data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]); 637 638 cacheDataPC[tid] = block_PC; 639 cacheDataValid[tid] = false; 640 DPRINTF(Fetch, "Fetch: Doing instruction read.\n"); 641 642 fetchedCacheLines++; 643 644 // Access the cache. 645 if (!icachePort->sendTiming(data_pkt)) { 646 assert(retryPkt == NULL); 647 assert(retryTid == InvalidThreadID); 648 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid); 649 650 fetchStatus[tid] = IcacheWaitRetry; 651 retryPkt = data_pkt; 652 retryTid = tid; 653 cacheBlocked = true; 654 } else { 655 DPRINTF(Fetch, "[tid:%i]: Doing Icache access.\n", tid); 656 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache " 657 "response.\n", tid); 658 659 lastIcacheStall[tid] = curTick(); 660 fetchStatus[tid] = IcacheWaitResponse; 661 } 662 } else { 663 DPRINTF(Fetch, "[tid:%i] Got back req with addr %#x but expected %#x\n", 664 mem_req->getVaddr(), memReq[tid]->getVaddr()); 665 // Translation faulted, icache request won't be sent. 666 delete mem_req; 667 memReq[tid] = NULL; 668 669 // Send the fault to commit. This thread will not do anything 670 // until commit handles the fault. The only other way it can 671 // wake up is if a squash comes along and changes the PC. 672 TheISA::PCState fetchPC = pc[tid]; 673 674 DPRINTF(Fetch, "[tid:%i]: Translation faulted, building noop.\n", tid); 675 // We will use a nop in ordier to carry the fault. 676 DynInstPtr instruction = buildInst(tid, 677 StaticInstPtr(TheISA::NoopMachInst, fetchPC.instAddr()), 678 NULL, fetchPC, fetchPC, false); 679 680 instruction->setPredTarg(fetchPC); 681 instruction->fault = fault; 682 wroteToTimeBuffer = true; 683 684 DPRINTF(Activity, "Activity this cycle.\n"); 685 cpu->activityThisCycle(); 686 687 fetchStatus[tid] = TrapPending; 688 689 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n", tid); 690 DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %s.\n", 691 tid, fault->name(), pc[tid]); 692 } 693 _status = updateFetchStatus(); 694} 695 696template <class Impl> 697inline void 698DefaultFetch<Impl>::doSquash(const TheISA::PCState &newPC, ThreadID tid) 699{ 700 DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %s.\n", 701 tid, newPC); 702 703 pc[tid] = newPC; 704 fetchOffset[tid] = 0; 705 macroop[tid] = NULL; 706 predecoder.reset(); 707 708 // Clear the icache miss if it's outstanding. 709 if (fetchStatus[tid] == IcacheWaitResponse) { 710 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n", 711 tid); 712 memReq[tid] = NULL; 713 } else if (fetchStatus[tid] == ItlbWait) { 714 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding ITLB miss.\n", 715 tid); 716 memReq[tid] = NULL; 717 } 718 719 // Get rid of the retrying packet if it was from this thread. 720 if (retryTid == tid) { 721 assert(cacheBlocked); 722 if (retryPkt) { 723 delete retryPkt->req; 724 delete retryPkt; 725 } 726 retryPkt = NULL; 727 retryTid = InvalidThreadID; 728 } 729 730 fetchStatus[tid] = Squashing; 731 732 ++fetchSquashCycles; 733} 734 735template<class Impl> 736void 737DefaultFetch<Impl>::squashFromDecode(const TheISA::PCState &newPC, 738 const InstSeqNum &seq_num, ThreadID tid) 739{ 740 DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n", tid); 741 742 doSquash(newPC, tid); 743 744 // Tell the CPU to remove any instructions that are in flight between 745 // fetch and decode. 746 cpu->removeInstsUntil(seq_num, tid); 747} 748 749template<class Impl> 750bool 751DefaultFetch<Impl>::checkStall(ThreadID tid) const 752{ 753 bool ret_val = false; 754 755 if (cpu->contextSwitch) { 756 DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid); 757 ret_val = true; 758 } else if (stalls[tid].decode) { 759 DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid); 760 ret_val = true; 761 } else if (stalls[tid].rename) { 762 DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid); 763 ret_val = true; 764 } else if (stalls[tid].iew) { 765 DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid); 766 ret_val = true; 767 } else if (stalls[tid].commit) { 768 DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid); 769 ret_val = true; 770 } 771 772 return ret_val; 773} 774 775template<class Impl> 776typename DefaultFetch<Impl>::FetchStatus 777DefaultFetch<Impl>::updateFetchStatus() 778{ 779 //Check Running 780 list<ThreadID>::iterator threads = activeThreads->begin(); 781 list<ThreadID>::iterator end = activeThreads->end(); 782 783 while (threads != end) { 784 ThreadID tid = *threads++; 785 786 if (fetchStatus[tid] == Running || 787 fetchStatus[tid] == Squashing || 788 fetchStatus[tid] == IcacheAccessComplete) { 789 790 if (_status == Inactive) { 791 DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid); 792 793 if (fetchStatus[tid] == IcacheAccessComplete) { 794 DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache" 795 "completion\n",tid); 796 } 797 798 cpu->activateStage(O3CPU::FetchIdx); 799 } 800 801 return Active; 802 } 803 } 804 805 // Stage is switching from active to inactive, notify CPU of it. 806 if (_status == Active) { 807 DPRINTF(Activity, "Deactivating stage.\n"); 808 809 cpu->deactivateStage(O3CPU::FetchIdx); 810 } 811 812 return Inactive; 813} 814 815template <class Impl> 816void 817DefaultFetch<Impl>::squash(const TheISA::PCState &newPC, 818 const InstSeqNum &seq_num, DynInstPtr &squashInst, 819 ThreadID tid) 820{ 821 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n", tid); 822 823 doSquash(newPC, tid); 824 if (squashInst) 825 predecoder.reset(squashInst->staticInst->machInst); 826 827 // Tell the CPU to remove any instructions that are not in the ROB. 828 cpu->removeInstsNotInROB(tid); 829} 830 831template <class Impl> 832void 833DefaultFetch<Impl>::tick() 834{ 835 list<ThreadID>::iterator threads = activeThreads->begin(); 836 list<ThreadID>::iterator end = activeThreads->end(); 837 bool status_change = false; 838 839 wroteToTimeBuffer = false; 840 841 while (threads != end) { 842 ThreadID tid = *threads++; 843 844 // Check the signals for each thread to determine the proper status 845 // for each thread. 846 bool updated_status = checkSignalsAndUpdate(tid); 847 status_change = status_change || updated_status; 848 } 849 850 DPRINTF(Fetch, "Running stage.\n"); 851 852 // Reset the number of the instruction we're fetching. 853 numInst = 0; 854 855#if FULL_SYSTEM 856 if (fromCommit->commitInfo[0].interruptPending) { 857 interruptPending = true; 858 } 859 860 if (fromCommit->commitInfo[0].clearInterrupt) { 861 interruptPending = false; 862 } 863#endif 864 865 for (threadFetched = 0; threadFetched < numFetchingThreads; 866 threadFetched++) { 867 // Fetch each of the actively fetching threads. 868 fetch(status_change); 869 } 870 871 // Record number of instructions fetched this cycle for distribution. 872 fetchNisnDist.sample(numInst); 873 874 if (status_change) { 875 // Change the fetch stage status if there was a status change. 876 _status = updateFetchStatus(); 877 } 878 879 // If there was activity this cycle, inform the CPU of it. 880 if (wroteToTimeBuffer || cpu->contextSwitch) { 881 DPRINTF(Activity, "Activity this cycle.\n"); 882 883 cpu->activityThisCycle(); 884 } 885} 886 887template <class Impl> 888bool 889DefaultFetch<Impl>::checkSignalsAndUpdate(ThreadID tid) 890{ 891 // Update the per thread stall statuses. 892 if (fromDecode->decodeBlock[tid]) { 893 stalls[tid].decode = true; 894 } 895 896 if (fromDecode->decodeUnblock[tid]) { 897 assert(stalls[tid].decode); 898 assert(!fromDecode->decodeBlock[tid]); 899 stalls[tid].decode = false; 900 } 901 902 if (fromRename->renameBlock[tid]) { 903 stalls[tid].rename = true; 904 } 905 906 if (fromRename->renameUnblock[tid]) { 907 assert(stalls[tid].rename); 908 assert(!fromRename->renameBlock[tid]); 909 stalls[tid].rename = false; 910 } 911 912 if (fromIEW->iewBlock[tid]) { 913 stalls[tid].iew = true; 914 } 915 916 if (fromIEW->iewUnblock[tid]) { 917 assert(stalls[tid].iew); 918 assert(!fromIEW->iewBlock[tid]); 919 stalls[tid].iew = false; 920 } 921 922 if (fromCommit->commitBlock[tid]) { 923 stalls[tid].commit = true; 924 } 925 926 if (fromCommit->commitUnblock[tid]) { 927 assert(stalls[tid].commit); 928 assert(!fromCommit->commitBlock[tid]); 929 stalls[tid].commit = false; 930 } 931 932 // Check squash signals from commit. 933 if (fromCommit->commitInfo[tid].squash) { 934 935 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash " 936 "from commit.\n",tid); 937 // In any case, squash. 938 squash(fromCommit->commitInfo[tid].pc, 939 fromCommit->commitInfo[tid].doneSeqNum, 940 fromCommit->commitInfo[tid].squashInst, tid); 941 942 // If it was a branch mispredict on a control instruction, update the 943 // branch predictor with that instruction, otherwise just kill the 944 // invalid state we generated in after sequence number 945 if (fromCommit->commitInfo[tid].mispredictInst && 946 fromCommit->commitInfo[tid].mispredictInst->isControl()) { 947 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum, 948 fromCommit->commitInfo[tid].pc, 949 fromCommit->commitInfo[tid].branchTaken, 950 tid); 951 } else { 952 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum, 953 tid); 954 } 955 956 return true; 957 } else if (fromCommit->commitInfo[tid].doneSeqNum) { 958 // Update the branch predictor if it wasn't a squashed instruction 959 // that was broadcasted. 960 branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid); 961 } 962 963 // Check ROB squash signals from commit. 964 if (fromCommit->commitInfo[tid].robSquashing) { 965 DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid); 966 967 // Continue to squash. 968 fetchStatus[tid] = Squashing; 969 970 return true; 971 } 972 973 // Check squash signals from decode. 974 if (fromDecode->decodeInfo[tid].squash) { 975 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash " 976 "from decode.\n",tid); 977 978 // Update the branch predictor. 979 if (fromDecode->decodeInfo[tid].branchMispredict) { 980 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum, 981 fromDecode->decodeInfo[tid].nextPC, 982 fromDecode->decodeInfo[tid].branchTaken, 983 tid); 984 } else { 985 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum, 986 tid); 987 } 988 989 if (fetchStatus[tid] != Squashing) { 990 991 TheISA::PCState nextPC = fromDecode->decodeInfo[tid].nextPC; 992 DPRINTF(Fetch, "Squashing from decode with PC = %s\n", nextPC); 993 // Squash unless we're already squashing 994 squashFromDecode(fromDecode->decodeInfo[tid].nextPC, 995 fromDecode->decodeInfo[tid].doneSeqNum, 996 tid); 997 998 return true; 999 } 1000 } 1001 1002 if (checkStall(tid) && 1003 fetchStatus[tid] != IcacheWaitResponse && 1004 fetchStatus[tid] != IcacheWaitRetry) { 1005 DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid); 1006 1007 fetchStatus[tid] = Blocked; 1008 1009 return true; 1010 } 1011 1012 if (fetchStatus[tid] == Blocked || 1013 fetchStatus[tid] == Squashing) { 1014 // Switch status to running if fetch isn't being told to block or 1015 // squash this cycle. 1016 DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n", 1017 tid); 1018 1019 fetchStatus[tid] = Running; 1020 1021 return true; 1022 } 1023 1024 // If we've reached this point, we have not gotten any signals that 1025 // cause fetch to change its status. Fetch remains the same as before. 1026 return false; 1027} 1028 1029template<class Impl> 1030typename Impl::DynInstPtr 1031DefaultFetch<Impl>::buildInst(ThreadID tid, StaticInstPtr staticInst, 1032 StaticInstPtr curMacroop, TheISA::PCState thisPC, 1033 TheISA::PCState nextPC, bool trace) 1034{ 1035 // Get a sequence number. 1036 InstSeqNum seq = cpu->getAndIncrementInstSeq(); 1037 1038 // Create a new DynInst from the instruction fetched. 1039 DynInstPtr instruction = 1040 new DynInst(staticInst, thisPC, nextPC, seq, cpu); 1041 instruction->setTid(tid); 1042 1043 instruction->setASID(tid); 1044 1045 instruction->setThreadState(cpu->thread[tid]); 1046 1047 DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x (%d) created " 1048 "[sn:%lli].\n", tid, thisPC.instAddr(), 1049 thisPC.microPC(), seq); 1050 1051 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", tid, 1052 instruction->staticInst-> 1053 disassemble(thisPC.instAddr())); 1054 1055#if TRACING_ON 1056 if (trace) { 1057 instruction->traceData = 1058 cpu->getTracer()->getInstRecord(curTick(), cpu->tcBase(tid), 1059 instruction->staticInst, thisPC, curMacroop); 1060 } 1061#else 1062 instruction->traceData = NULL; 1063#endif 1064 1065 // Add instruction to the CPU's list of instructions. 1066 instruction->setInstListIt(cpu->addInst(instruction)); 1067 1068 // Write the instruction to the first slot in the queue 1069 // that heads to decode. 1070 assert(numInst < fetchWidth); 1071 toDecode->insts[toDecode->size++] = instruction; 1072 1073 return instruction; 1074} 1075 1076template<class Impl> 1077void 1078DefaultFetch<Impl>::fetch(bool &status_change) 1079{ 1080 ////////////////////////////////////////// 1081 // Start actual fetch 1082 ////////////////////////////////////////// 1083 ThreadID tid = getFetchingThread(fetchPolicy); 1084 1085 if (tid == InvalidThreadID || drainPending) { 1086 DPRINTF(Fetch,"There are no more threads available to fetch from.\n"); 1087 1088 // Breaks looping condition in tick() 1089 threadFetched = numFetchingThreads; 1090 return; 1091 } 1092 1093 DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid); 1094 1095 // The current PC. 1096 TheISA::PCState thisPC = pc[tid]; 1097 1098 Addr pcOffset = fetchOffset[tid]; 1099 Addr fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask; 1100 1101 bool inRom = isRomMicroPC(thisPC.microPC()); 1102 1103 // If returning from the delay of a cache miss, then update the status 1104 // to running, otherwise do the cache access. Possibly move this up 1105 // to tick() function. 1106 if (fetchStatus[tid] == IcacheAccessComplete) { 1107 DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n", tid); 1108 1109 fetchStatus[tid] = Running; 1110 status_change = true; 1111 } else if (fetchStatus[tid] == Running) { 1112 // Align the fetch PC so its at the start of a cache block. 1113 Addr block_PC = icacheBlockAlignPC(fetchAddr); 1114 1115 // Unless buffer already got the block, fetch it from icache. 1116 if (!(cacheDataValid[tid] && block_PC == cacheDataPC[tid]) && !inRom) { 1117 DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read " 1118 "instruction, starting at PC %s.\n", tid, thisPC); 1119 1120 fetchCacheLine(fetchAddr, tid, thisPC.instAddr()); 1121 1122 if (fetchStatus[tid] == IcacheWaitResponse) 1123 ++icacheStallCycles; 1124 else if (fetchStatus[tid] == ItlbWait) 1125 ++fetchTlbCycles; 1126 else 1127 ++fetchMiscStallCycles; 1128 return; 1129 } else if (checkInterrupt(thisPC.instAddr()) || isSwitchedOut()) { 1130 ++fetchMiscStallCycles; 1131 return; 1132 } 1133 } else { 1134 if (fetchStatus[tid] == Idle) { 1135 ++fetchIdleCycles; 1136 DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid); 1137 } else if (fetchStatus[tid] == Blocked) { 1138 ++fetchBlockedCycles; 1139 DPRINTF(Fetch, "[tid:%i]: Fetch is blocked!\n", tid); 1140 } else if (fetchStatus[tid] == Squashing) { 1141 ++fetchSquashCycles; 1142 DPRINTF(Fetch, "[tid:%i]: Fetch is squashing!\n", tid); 1143 } else if (fetchStatus[tid] == IcacheWaitResponse) { 1144 ++icacheStallCycles; 1145 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n", 1146 tid); 1147 } else if (fetchStatus[tid] == ItlbWait) { 1148 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting ITLB walk to " 1149 "finish! \n", tid); 1150 ++fetchTlbCycles; 1151 } else if (fetchStatus[tid] == TrapPending) { 1152 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting for a pending trap\n", 1153 tid); 1154 } 1155 1156 1157 // Status is Idle, Squashing, Blocked, ItlbWait or IcacheWaitResponse 1158 // so fetch should do nothing. 1159 return; 1160 } 1161 1162 ++fetchCycles; 1163 1164 TheISA::PCState nextPC = thisPC; 1165 1166 StaticInstPtr staticInst = NULL; 1167 StaticInstPtr curMacroop = macroop[tid]; 1168 1169 // If the read of the first instruction was successful, then grab the 1170 // instructions from the rest of the cache line and put them into the 1171 // queue heading to decode. 1172 1173 DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to " 1174 "decode.\n", tid); 1175 1176 // Need to keep track of whether or not a predicted branch 1177 // ended this fetch block. 1178 bool predictedBranch = false; 1179 1180 TheISA::MachInst *cacheInsts = 1181 reinterpret_cast<TheISA::MachInst *>(cacheData[tid]); 1182 1183 const unsigned numInsts = cacheBlkSize / instSize; 1184 unsigned blkOffset = (fetchAddr - cacheDataPC[tid]) / instSize; 1185 1186 // Loop through instruction memory from the cache. 1187 while (blkOffset < numInsts && 1188 numInst < fetchWidth && 1189 !predictedBranch) { 1190 1191 // If we need to process more memory, do it now. 1192 if (!(curMacroop || inRom) && !predecoder.extMachInstReady()) { 1193 if (ISA_HAS_DELAY_SLOT && pcOffset == 0) { 1194 // Walk past any annulled delay slot instructions. 1195 Addr pcAddr = thisPC.instAddr() & BaseCPU::PCMask; 1196 while (fetchAddr != pcAddr && blkOffset < numInsts) { 1197 blkOffset++; 1198 fetchAddr += instSize; 1199 } 1200 if (blkOffset >= numInsts) 1201 break; 1202 } 1203 MachInst inst = TheISA::gtoh(cacheInsts[blkOffset]); 1204 1205 predecoder.setTC(cpu->thread[tid]->getTC()); 1206 predecoder.moreBytes(thisPC, fetchAddr, inst); 1207 1208 if (predecoder.needMoreBytes()) { 1209 blkOffset++; 1210 fetchAddr += instSize; 1211 pcOffset += instSize; 1212 } 1213 } 1214 1215 // Extract as many instructions and/or microops as we can from 1216 // the memory we've processed so far. 1217 do { 1218 if (!(curMacroop || inRom)) { 1219 if (predecoder.extMachInstReady()) { 1220 ExtMachInst extMachInst; 1221 1222 extMachInst = predecoder.getExtMachInst(thisPC); 1223 staticInst = StaticInstPtr(extMachInst, 1224 thisPC.instAddr()); 1225 1226 // Increment stat of fetched instructions. 1227 ++fetchedInsts; 1228 1229 if (staticInst->isMacroop()) { 1230 curMacroop = staticInst; 1231 } else { 1232 pcOffset = 0; 1233 } 1234 } else { 1235 // We need more bytes for this instruction. 1236 break; 1237 } 1238 } 1239 if (curMacroop || inRom) { 1240 if (inRom) { 1241 staticInst = cpu->microcodeRom.fetchMicroop( 1242 thisPC.microPC(), curMacroop); 1243 } else { 1244 staticInst = curMacroop->fetchMicroop(thisPC.microPC()); 1245 } 1246 if (staticInst->isLastMicroop()) { 1247 curMacroop = NULL; 1248 pcOffset = 0; 1249 } 1250 } 1251 1252 DynInstPtr instruction = 1253 buildInst(tid, staticInst, curMacroop, 1254 thisPC, nextPC, true); 1255 1256 numInst++; 1257 1258 nextPC = thisPC; 1259 1260 // If we're branching after this instruction, quite fetching 1261 // from the same block then. 1262 predictedBranch |= thisPC.branching(); 1263 predictedBranch |= 1264 lookupAndUpdateNextPC(instruction, nextPC); 1265 if (predictedBranch) { 1266 DPRINTF(Fetch, "Branch detected with PC = %s\n", thisPC); 1267 } 1268 1269 // Move to the next instruction, unless we have a branch. 1270 thisPC = nextPC; 1271 1272 if (instruction->isQuiesce()) { 1273 DPRINTF(Fetch, 1274 "Quiesce instruction encountered, halting fetch!"); 1275 fetchStatus[tid] = QuiescePending; 1276 status_change = true; 1277 break; 1278 } 1279 } while ((curMacroop || predecoder.extMachInstReady()) && 1280 numInst < fetchWidth); 1281 } 1282 1283 if (predictedBranch) { 1284 DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch " 1285 "instruction encountered.\n", tid); 1286 } else if (numInst >= fetchWidth) { 1287 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth " 1288 "for this cycle.\n", tid); 1289 } else if (blkOffset >= cacheBlkSize) { 1290 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache " 1291 "block.\n", tid); 1292 } 1293 1294 macroop[tid] = curMacroop; 1295 fetchOffset[tid] = pcOffset; 1296 1297 if (numInst > 0) { 1298 wroteToTimeBuffer = true; 1299 } 1300 1301 pc[tid] = thisPC; 1302} 1303 1304template<class Impl> 1305void 1306DefaultFetch<Impl>::recvRetry() 1307{ 1308 if (retryPkt != NULL) { 1309 assert(cacheBlocked); 1310 assert(retryTid != InvalidThreadID); 1311 assert(fetchStatus[retryTid] == IcacheWaitRetry); 1312 1313 if (icachePort->sendTiming(retryPkt)) { 1314 fetchStatus[retryTid] = IcacheWaitResponse; 1315 retryPkt = NULL; 1316 retryTid = InvalidThreadID; 1317 cacheBlocked = false; 1318 } 1319 } else { 1320 assert(retryTid == InvalidThreadID); 1321 // Access has been squashed since it was sent out. Just clear 1322 // the cache being blocked. 1323 cacheBlocked = false; 1324 } 1325} 1326 1327/////////////////////////////////////// 1328// // 1329// SMT FETCH POLICY MAINTAINED HERE // 1330// // 1331/////////////////////////////////////// 1332template<class Impl> 1333ThreadID 1334DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority) 1335{ 1336 if (numThreads > 1) { 1337 switch (fetch_priority) { 1338 1339 case SingleThread: 1340 return 0; 1341 1342 case RoundRobin: 1343 return roundRobin(); 1344 1345 case IQ: 1346 return iqCount(); 1347 1348 case LSQ: 1349 return lsqCount(); 1350 1351 case Branch: 1352 return branchCount(); 1353 1354 default: 1355 return InvalidThreadID; 1356 } 1357 } else { 1358 list<ThreadID>::iterator thread = activeThreads->begin(); 1359 if (thread == activeThreads->end()) { 1360 return InvalidThreadID; 1361 } 1362 1363 ThreadID tid = *thread; 1364 1365 if (fetchStatus[tid] == Running || 1366 fetchStatus[tid] == IcacheAccessComplete || 1367 fetchStatus[tid] == Idle) { 1368 return tid; 1369 } else { 1370 return InvalidThreadID; 1371 } 1372 } 1373} 1374 1375 1376template<class Impl> 1377ThreadID 1378DefaultFetch<Impl>::roundRobin() 1379{ 1380 list<ThreadID>::iterator pri_iter = priorityList.begin(); 1381 list<ThreadID>::iterator end = priorityList.end(); 1382 1383 ThreadID high_pri; 1384 1385 while (pri_iter != end) { 1386 high_pri = *pri_iter; 1387 1388 assert(high_pri <= numThreads); 1389 1390 if (fetchStatus[high_pri] == Running || 1391 fetchStatus[high_pri] == IcacheAccessComplete || 1392 fetchStatus[high_pri] == Idle) { 1393 1394 priorityList.erase(pri_iter); 1395 priorityList.push_back(high_pri); 1396 1397 return high_pri; 1398 } 1399 1400 pri_iter++; 1401 } 1402 1403 return InvalidThreadID; 1404} 1405 1406template<class Impl> 1407ThreadID 1408DefaultFetch<Impl>::iqCount() 1409{ 1410 std::priority_queue<unsigned> PQ; 1411 std::map<unsigned, ThreadID> threadMap; 1412 1413 list<ThreadID>::iterator threads = activeThreads->begin(); 1414 list<ThreadID>::iterator end = activeThreads->end(); 1415 1416 while (threads != end) { 1417 ThreadID tid = *threads++; 1418 unsigned iqCount = fromIEW->iewInfo[tid].iqCount; 1419 1420 PQ.push(iqCount); 1421 threadMap[iqCount] = tid; 1422 } 1423 1424 while (!PQ.empty()) { 1425 ThreadID high_pri = threadMap[PQ.top()]; 1426 1427 if (fetchStatus[high_pri] == Running || 1428 fetchStatus[high_pri] == IcacheAccessComplete || 1429 fetchStatus[high_pri] == Idle) 1430 return high_pri; 1431 else 1432 PQ.pop(); 1433 1434 } 1435 1436 return InvalidThreadID; 1437} 1438 1439template<class Impl> 1440ThreadID 1441DefaultFetch<Impl>::lsqCount() 1442{ 1443 std::priority_queue<unsigned> PQ; 1444 std::map<unsigned, ThreadID> threadMap; 1445 1446 list<ThreadID>::iterator threads = activeThreads->begin(); 1447 list<ThreadID>::iterator end = activeThreads->end(); 1448 1449 while (threads != end) { 1450 ThreadID tid = *threads++; 1451 unsigned ldstqCount = fromIEW->iewInfo[tid].ldstqCount; 1452 1453 PQ.push(ldstqCount); 1454 threadMap[ldstqCount] = tid; 1455 } 1456 1457 while (!PQ.empty()) { 1458 ThreadID high_pri = threadMap[PQ.top()]; 1459 1460 if (fetchStatus[high_pri] == Running || 1461 fetchStatus[high_pri] == IcacheAccessComplete || 1462 fetchStatus[high_pri] == Idle) 1463 return high_pri; 1464 else 1465 PQ.pop(); 1466 } 1467 1468 return InvalidThreadID; 1469} 1470 1471template<class Impl> 1472ThreadID 1473DefaultFetch<Impl>::branchCount() 1474{ 1475#if 0 1476 list<ThreadID>::iterator thread = activeThreads->begin(); 1477 assert(thread != activeThreads->end()); 1478 ThreadID tid = *thread; 1479#endif 1480 1481 panic("Branch Count Fetch policy unimplemented\n"); 1482 return InvalidThreadID; 1483} 1484