fetch_impl.hh revision 8064:5b111ae7e7d4
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 * Korey Sewell 42 */ 43 44#include <algorithm> 45#include <cstring> 46 47#include "arch/isa_traits.hh" 48#include "arch/utility.hh" 49#include "base/types.hh" 50#include "config/the_isa.hh" 51#include "config/use_checker.hh" 52#include "cpu/checker/cpu.hh" 53#include "cpu/exetrace.hh" 54#include "cpu/o3/fetch.hh" 55#include "mem/packet.hh" 56#include "mem/request.hh" 57#include "params/DerivO3CPU.hh" 58#include "sim/byteswap.hh" 59#include "sim/core.hh" 60 61#if FULL_SYSTEM 62#include "arch/tlb.hh" 63#include "arch/vtophys.hh" 64#include "sim/system.hh" 65#endif // FULL_SYSTEM 66 67using namespace std; 68 69template<class Impl> 70void 71DefaultFetch<Impl>::IcachePort::setPeer(Port *port) 72{ 73 Port::setPeer(port); 74 75 fetch->setIcache(); 76} 77 78template<class Impl> 79Tick 80DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt) 81{ 82 panic("DefaultFetch doesn't expect recvAtomic callback!"); 83 return curTick(); 84} 85 86template<class Impl> 87void 88DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt) 89{ 90 DPRINTF(Fetch, "DefaultFetch doesn't update its state from a " 91 "functional call."); 92} 93 94template<class Impl> 95void 96DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status) 97{ 98 if (status == RangeChange) { 99 if (!snoopRangeSent) { 100 snoopRangeSent = true; 101 sendStatusChange(Port::RangeChange); 102 } 103 return; 104 } 105 106 panic("DefaultFetch doesn't expect recvStatusChange callback!"); 107} 108 109template<class Impl> 110bool 111DefaultFetch<Impl>::IcachePort::recvTiming(PacketPtr pkt) 112{ 113 DPRINTF(Fetch, "Received timing\n"); 114 if (pkt->isResponse()) { 115 fetch->processCacheCompletion(pkt); 116 } 117 //else Snooped a coherence request, just return 118 return true; 119} 120 121template<class Impl> 122void 123DefaultFetch<Impl>::IcachePort::recvRetry() 124{ 125 fetch->recvRetry(); 126} 127 128template<class Impl> 129DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params) 130 : cpu(_cpu), 131 branchPred(params), 132 predecoder(NULL), 133 decodeToFetchDelay(params->decodeToFetchDelay), 134 renameToFetchDelay(params->renameToFetchDelay), 135 iewToFetchDelay(params->iewToFetchDelay), 136 commitToFetchDelay(params->commitToFetchDelay), 137 fetchWidth(params->fetchWidth), 138 cacheBlocked(false), 139 retryPkt(NULL), 140 retryTid(InvalidThreadID), 141 numThreads(params->numThreads), 142 numFetchingThreads(params->smtNumFetchingThreads), 143 interruptPending(false), 144 drainPending(false), 145 switchedOut(false) 146{ 147 if (numThreads > Impl::MaxThreads) 148 fatal("numThreads (%d) is larger than compiled limit (%d),\n" 149 "\tincrease MaxThreads in src/cpu/o3/impl.hh\n", 150 numThreads, static_cast<int>(Impl::MaxThreads)); 151 152 // Set fetch stage's status to inactive. 153 _status = Inactive; 154 155 std::string policy = params->smtFetchPolicy; 156 157 // Convert string to lowercase 158 std::transform(policy.begin(), policy.end(), policy.begin(), 159 (int(*)(int)) tolower); 160 161 // Figure out fetch policy 162 if (policy == "singlethread") { 163 fetchPolicy = SingleThread; 164 if (numThreads > 1) 165 panic("Invalid Fetch Policy for a SMT workload."); 166 } else if (policy == "roundrobin") { 167 fetchPolicy = RoundRobin; 168 DPRINTF(Fetch, "Fetch policy set to Round Robin\n"); 169 } else if (policy == "branch") { 170 fetchPolicy = Branch; 171 DPRINTF(Fetch, "Fetch policy set to Branch Count\n"); 172 } else if (policy == "iqcount") { 173 fetchPolicy = IQ; 174 DPRINTF(Fetch, "Fetch policy set to IQ count\n"); 175 } else if (policy == "lsqcount") { 176 fetchPolicy = LSQ; 177 DPRINTF(Fetch, "Fetch policy set to LSQ count\n"); 178 } else { 179 fatal("Invalid Fetch Policy. Options Are: {SingleThread," 180 " RoundRobin,LSQcount,IQcount}\n"); 181 } 182 183 // Get the size of an instruction. 184 instSize = sizeof(TheISA::MachInst); 185 186 // Name is finally available, so create the port. 187 icachePort = new IcachePort(this); 188 189 icachePort->snoopRangeSent = false; 190 191#if USE_CHECKER 192 if (cpu->checker) { 193 cpu->checker->setIcachePort(icachePort); 194 } 195#endif 196} 197 198template <class Impl> 199std::string 200DefaultFetch<Impl>::name() const 201{ 202 return cpu->name() + ".fetch"; 203} 204 205template <class Impl> 206void 207DefaultFetch<Impl>::regStats() 208{ 209 icacheStallCycles 210 .name(name() + ".icacheStallCycles") 211 .desc("Number of cycles fetch is stalled on an Icache miss") 212 .prereq(icacheStallCycles); 213 214 fetchedInsts 215 .name(name() + ".Insts") 216 .desc("Number of instructions fetch has processed") 217 .prereq(fetchedInsts); 218 219 fetchedBranches 220 .name(name() + ".Branches") 221 .desc("Number of branches that fetch encountered") 222 .prereq(fetchedBranches); 223 224 predictedBranches 225 .name(name() + ".predictedBranches") 226 .desc("Number of branches that fetch has predicted taken") 227 .prereq(predictedBranches); 228 229 fetchCycles 230 .name(name() + ".Cycles") 231 .desc("Number of cycles fetch has run and was not squashing or" 232 " blocked") 233 .prereq(fetchCycles); 234 235 fetchSquashCycles 236 .name(name() + ".SquashCycles") 237 .desc("Number of cycles fetch has spent squashing") 238 .prereq(fetchSquashCycles); 239 240 fetchTlbCycles 241 .name(name() + ".TlbCycles") 242 .desc("Number of cycles fetch has spent waiting for tlb") 243 .prereq(fetchTlbCycles); 244 245 fetchIdleCycles 246 .name(name() + ".IdleCycles") 247 .desc("Number of cycles fetch was idle") 248 .prereq(fetchIdleCycles); 249 250 fetchBlockedCycles 251 .name(name() + ".BlockedCycles") 252 .desc("Number of cycles fetch has spent blocked") 253 .prereq(fetchBlockedCycles); 254 255 fetchedCacheLines 256 .name(name() + ".CacheLines") 257 .desc("Number of cache lines fetched") 258 .prereq(fetchedCacheLines); 259 260 fetchMiscStallCycles 261 .name(name() + ".MiscStallCycles") 262 .desc("Number of cycles fetch has spent waiting on interrupts, or " 263 "bad addresses, or out of MSHRs") 264 .prereq(fetchMiscStallCycles); 265 266 fetchIcacheSquashes 267 .name(name() + ".IcacheSquashes") 268 .desc("Number of outstanding Icache misses that were squashed") 269 .prereq(fetchIcacheSquashes); 270 271 fetchTlbSquashes 272 .name(name() + ".ItlbSquashes") 273 .desc("Number of outstanding ITLB misses that were squashed") 274 .prereq(fetchTlbSquashes); 275 276 fetchNisnDist 277 .init(/* base value */ 0, 278 /* last value */ fetchWidth, 279 /* bucket size */ 1) 280 .name(name() + ".rateDist") 281 .desc("Number of instructions fetched each cycle (Total)") 282 .flags(Stats::pdf); 283 284 idleRate 285 .name(name() + ".idleRate") 286 .desc("Percent of cycles fetch was idle") 287 .prereq(idleRate); 288 idleRate = fetchIdleCycles * 100 / cpu->numCycles; 289 290 branchRate 291 .name(name() + ".branchRate") 292 .desc("Number of branch fetches per cycle") 293 .flags(Stats::total); 294 branchRate = fetchedBranches / cpu->numCycles; 295 296 fetchRate 297 .name(name() + ".rate") 298 .desc("Number of inst fetches per cycle") 299 .flags(Stats::total); 300 fetchRate = fetchedInsts / cpu->numCycles; 301 302 branchPred.regStats(); 303} 304 305template<class Impl> 306void 307DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer) 308{ 309 timeBuffer = time_buffer; 310 311 // Create wires to get information from proper places in time buffer. 312 fromDecode = timeBuffer->getWire(-decodeToFetchDelay); 313 fromRename = timeBuffer->getWire(-renameToFetchDelay); 314 fromIEW = timeBuffer->getWire(-iewToFetchDelay); 315 fromCommit = timeBuffer->getWire(-commitToFetchDelay); 316} 317 318template<class Impl> 319void 320DefaultFetch<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr) 321{ 322 activeThreads = at_ptr; 323} 324 325template<class Impl> 326void 327DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 328{ 329 fetchQueue = fq_ptr; 330 331 // Create wire to write information to proper place in fetch queue. 332 toDecode = fetchQueue->getWire(0); 333} 334 335template<class Impl> 336void 337DefaultFetch<Impl>::initStage() 338{ 339 // Setup PC and nextPC with initial state. 340 for (ThreadID tid = 0; tid < numThreads; tid++) { 341 pc[tid] = cpu->pcState(tid); 342 fetchOffset[tid] = 0; 343 macroop[tid] = NULL; 344 } 345 346 for (ThreadID tid = 0; tid < numThreads; tid++) { 347 348 fetchStatus[tid] = Running; 349 350 priorityList.push_back(tid); 351 352 memReq[tid] = NULL; 353 354 stalls[tid].decode = false; 355 stalls[tid].rename = false; 356 stalls[tid].iew = false; 357 stalls[tid].commit = false; 358 } 359 360 // Schedule fetch to get the correct PC from the CPU 361 // scheduleFetchStartupEvent(1); 362 363 // Fetch needs to start fetching instructions at the very beginning, 364 // so it must start up in active state. 365 switchToActive(); 366} 367 368template<class Impl> 369void 370DefaultFetch<Impl>::setIcache() 371{ 372 // Size of cache block. 373 cacheBlkSize = icachePort->peerBlockSize(); 374 375 // Create mask to get rid of offset bits. 376 cacheBlkMask = (cacheBlkSize - 1); 377 378 for (ThreadID tid = 0; tid < numThreads; tid++) { 379 // Create space to store a cache line. 380 cacheData[tid] = new uint8_t[cacheBlkSize]; 381 cacheDataPC[tid] = 0; 382 cacheDataValid[tid] = false; 383 } 384} 385 386template<class Impl> 387void 388DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt) 389{ 390 ThreadID tid = pkt->req->threadId(); 391 392 DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n", tid); 393 394 assert(!pkt->wasNacked()); 395 396 // Only change the status if it's still waiting on the icache access 397 // to return. 398 if (fetchStatus[tid] != IcacheWaitResponse || 399 pkt->req != memReq[tid] || 400 isSwitchedOut()) { 401 ++fetchIcacheSquashes; 402 delete pkt->req; 403 delete pkt; 404 return; 405 } 406 407 memcpy(cacheData[tid], pkt->getPtr<uint8_t>(), cacheBlkSize); 408 cacheDataValid[tid] = true; 409 410 if (!drainPending) { 411 // Wake up the CPU (if it went to sleep and was waiting on 412 // this completion event). 413 cpu->wakeCPU(); 414 415 DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n", 416 tid); 417 418 switchToActive(); 419 } 420 421 // Only switch to IcacheAccessComplete if we're not stalled as well. 422 if (checkStall(tid)) { 423 fetchStatus[tid] = Blocked; 424 } else { 425 fetchStatus[tid] = IcacheAccessComplete; 426 } 427 428 // Reset the mem req to NULL. 429 delete pkt->req; 430 delete pkt; 431 memReq[tid] = NULL; 432} 433 434template <class Impl> 435bool 436DefaultFetch<Impl>::drain() 437{ 438 // Fetch is ready to drain at any time. 439 cpu->signalDrained(); 440 drainPending = true; 441 return true; 442} 443 444template <class Impl> 445void 446DefaultFetch<Impl>::resume() 447{ 448 drainPending = false; 449} 450 451template <class Impl> 452void 453DefaultFetch<Impl>::switchOut() 454{ 455 switchedOut = true; 456 // Branch predictor needs to have its state cleared. 457 branchPred.switchOut(); 458} 459 460template <class Impl> 461void 462DefaultFetch<Impl>::takeOverFrom() 463{ 464 // Reset all state 465 for (ThreadID i = 0; i < Impl::MaxThreads; ++i) { 466 stalls[i].decode = 0; 467 stalls[i].rename = 0; 468 stalls[i].iew = 0; 469 stalls[i].commit = 0; 470 pc[i] = cpu->pcState(i); 471 fetchStatus[i] = Running; 472 } 473 numInst = 0; 474 wroteToTimeBuffer = false; 475 _status = Inactive; 476 switchedOut = false; 477 interruptPending = false; 478 branchPred.takeOverFrom(); 479} 480 481template <class Impl> 482void 483DefaultFetch<Impl>::wakeFromQuiesce() 484{ 485 DPRINTF(Fetch, "Waking up from quiesce\n"); 486 // Hopefully this is safe 487 // @todo: Allow other threads to wake from quiesce. 488 fetchStatus[0] = Running; 489} 490 491template <class Impl> 492inline void 493DefaultFetch<Impl>::switchToActive() 494{ 495 if (_status == Inactive) { 496 DPRINTF(Activity, "Activating stage.\n"); 497 498 cpu->activateStage(O3CPU::FetchIdx); 499 500 _status = Active; 501 } 502} 503 504template <class Impl> 505inline void 506DefaultFetch<Impl>::switchToInactive() 507{ 508 if (_status == Active) { 509 DPRINTF(Activity, "Deactivating stage.\n"); 510 511 cpu->deactivateStage(O3CPU::FetchIdx); 512 513 _status = Inactive; 514 } 515} 516 517template <class Impl> 518bool 519DefaultFetch<Impl>::lookupAndUpdateNextPC( 520 DynInstPtr &inst, TheISA::PCState &nextPC) 521{ 522 // Do branch prediction check here. 523 // A bit of a misnomer...next_PC is actually the current PC until 524 // this function updates it. 525 bool predict_taken; 526 527 if (!inst->isControl()) { 528 TheISA::advancePC(nextPC, inst->staticInst); 529 inst->setPredTarg(nextPC); 530 inst->setPredTaken(false); 531 return false; 532 } 533 534 ThreadID tid = inst->threadNumber; 535 predict_taken = branchPred.predict(inst, nextPC, tid); 536 537 if (predict_taken) { 538 DPRINTF(Fetch, "[tid:%i]: [sn:%i]: Branch predicted to be taken to %s.\n", 539 tid, inst->seqNum, nextPC); 540 } else { 541 DPRINTF(Fetch, "[tid:%i]: [sn:%i]:Branch predicted to be not taken.\n", 542 tid, inst->seqNum); 543 } 544 545 DPRINTF(Fetch, "[tid:%i]: [sn:%i] Branch predicted to go to %s.\n", 546 tid, inst->seqNum, nextPC); 547 inst->setPredTarg(nextPC); 548 inst->setPredTaken(predict_taken); 549 550 ++fetchedBranches; 551 552 if (predict_taken) { 553 ++predictedBranches; 554 } 555 556 return predict_taken; 557} 558 559template <class Impl> 560bool 561DefaultFetch<Impl>::fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc) 562{ 563 Fault fault = NoFault; 564 565 // @todo: not sure if these should block translation. 566 //AlphaDep 567 if (cacheBlocked) { 568 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n", 569 tid); 570 return false; 571 } else if (isSwitchedOut()) { 572 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, switched out\n", 573 tid); 574 return false; 575 } else if (checkInterrupt(pc)) { 576 // Hold off fetch from getting new instructions when: 577 // Cache is blocked, or 578 // while an interrupt is pending and we're not in PAL mode, or 579 // fetch is switched out. 580 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n", 581 tid); 582 return false; 583 } 584 585 // Align the fetch address so it's at the start of a cache block. 586 Addr block_PC = icacheBlockAlignPC(vaddr); 587 588 DPRINTF(Fetch, "[tid:%i] Fetching cache line %#x for addr %#x\n", 589 tid, block_PC, vaddr); 590 591 // Setup the memReq to do a read of the first instruction's address. 592 // Set the appropriate read size and flags as well. 593 // Build request here. 594 RequestPtr mem_req = 595 new Request(tid, block_PC, cacheBlkSize, Request::INST_FETCH, 596 pc, cpu->thread[tid]->contextId(), tid); 597 598 memReq[tid] = mem_req; 599 600 // Initiate translation of the icache block 601 fetchStatus[tid] = ItlbWait; 602 FetchTranslation *trans = new FetchTranslation(this); 603 cpu->itb->translateTiming(mem_req, cpu->thread[tid]->getTC(), 604 trans, BaseTLB::Execute); 605 return true; 606} 607 608template <class Impl> 609void 610DefaultFetch<Impl>::finishTranslation(Fault fault, RequestPtr mem_req) 611{ 612 ThreadID tid = mem_req->threadId(); 613 Addr block_PC = mem_req->getVaddr(); 614 615 // Wake up CPU if it was idle 616 cpu->wakeCPU(); 617 618 if (fetchStatus[tid] != ItlbWait || mem_req != memReq[tid] || 619 mem_req->getVaddr() != memReq[tid]->getVaddr() || isSwitchedOut()) { 620 DPRINTF(Fetch, "[tid:%i] Ignoring itlb completed after squash\n", 621 tid); 622 ++fetchTlbSquashes; 623 delete mem_req; 624 return; 625 } 626 627 628 // If translation was successful, attempt to read the icache block. 629 if (fault == NoFault) { 630 // Build packet here. 631 PacketPtr data_pkt = new Packet(mem_req, 632 MemCmd::ReadReq, Packet::Broadcast); 633 data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]); 634 635 cacheDataPC[tid] = block_PC; 636 cacheDataValid[tid] = false; 637 DPRINTF(Fetch, "Fetch: Doing instruction read.\n"); 638 639 fetchedCacheLines++; 640 641 // Access the cache. 642 if (!icachePort->sendTiming(data_pkt)) { 643 assert(retryPkt == NULL); 644 assert(retryTid == InvalidThreadID); 645 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid); 646 647 fetchStatus[tid] = IcacheWaitRetry; 648 retryPkt = data_pkt; 649 retryTid = tid; 650 cacheBlocked = true; 651 } else { 652 DPRINTF(Fetch, "[tid:%i]: Doing Icache access.\n", tid); 653 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache " 654 "response.\n", tid); 655 656 lastIcacheStall[tid] = curTick(); 657 fetchStatus[tid] = IcacheWaitResponse; 658 } 659 } else { 660 DPRINTF(Fetch, "[tid:%i] Got back req with addr %#x but expected %#x\n", 661 mem_req->getVaddr(), memReq[tid]->getVaddr()); 662 // Translation faulted, icache request won't be sent. 663 delete mem_req; 664 memReq[tid] = NULL; 665 666 // Send the fault to commit. This thread will not do anything 667 // until commit handles the fault. The only other way it can 668 // wake up is if a squash comes along and changes the PC. 669 TheISA::PCState fetchPC = pc[tid]; 670 671 DPRINTF(Fetch, "[tid:%i]: Translation faulted, building noop.\n", tid); 672 // We will use a nop in ordier to carry the fault. 673 DynInstPtr instruction = buildInst(tid, 674 StaticInstPtr(TheISA::NoopMachInst, fetchPC.instAddr()), 675 NULL, fetchPC, fetchPC, false); 676 677 instruction->setPredTarg(fetchPC); 678 instruction->fault = fault; 679 wroteToTimeBuffer = true; 680 681 DPRINTF(Activity, "Activity this cycle.\n"); 682 cpu->activityThisCycle(); 683 684 fetchStatus[tid] = TrapPending; 685 686 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n", tid); 687 DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %s.\n", 688 tid, fault->name(), pc[tid]); 689 } 690 _status = updateFetchStatus(); 691} 692 693template <class Impl> 694inline void 695DefaultFetch<Impl>::doSquash(const TheISA::PCState &newPC, ThreadID tid) 696{ 697 DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %s.\n", 698 tid, newPC); 699 700 pc[tid] = newPC; 701 fetchOffset[tid] = 0; 702 macroop[tid] = NULL; 703 predecoder.reset(); 704 705 // Clear the icache miss if it's outstanding. 706 if (fetchStatus[tid] == IcacheWaitResponse) { 707 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n", 708 tid); 709 memReq[tid] = NULL; 710 } else if (fetchStatus[tid] == ItlbWait) { 711 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding ITLB miss.\n", 712 tid); 713 memReq[tid] = NULL; 714 } 715 716 // Get rid of the retrying packet if it was from this thread. 717 if (retryTid == tid) { 718 assert(cacheBlocked); 719 if (retryPkt) { 720 delete retryPkt->req; 721 delete retryPkt; 722 } 723 retryPkt = NULL; 724 retryTid = InvalidThreadID; 725 } 726 727 fetchStatus[tid] = Squashing; 728 729 ++fetchSquashCycles; 730} 731 732template<class Impl> 733void 734DefaultFetch<Impl>::squashFromDecode(const TheISA::PCState &newPC, 735 const InstSeqNum &seq_num, ThreadID tid) 736{ 737 DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n", tid); 738 739 doSquash(newPC, tid); 740 741 // Tell the CPU to remove any instructions that are in flight between 742 // fetch and decode. 743 cpu->removeInstsUntil(seq_num, tid); 744} 745 746template<class Impl> 747bool 748DefaultFetch<Impl>::checkStall(ThreadID tid) const 749{ 750 bool ret_val = false; 751 752 if (cpu->contextSwitch) { 753 DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid); 754 ret_val = true; 755 } else if (stalls[tid].decode) { 756 DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid); 757 ret_val = true; 758 } else if (stalls[tid].rename) { 759 DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid); 760 ret_val = true; 761 } else if (stalls[tid].iew) { 762 DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid); 763 ret_val = true; 764 } else if (stalls[tid].commit) { 765 DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid); 766 ret_val = true; 767 } 768 769 return ret_val; 770} 771 772template<class Impl> 773typename DefaultFetch<Impl>::FetchStatus 774DefaultFetch<Impl>::updateFetchStatus() 775{ 776 //Check Running 777 list<ThreadID>::iterator threads = activeThreads->begin(); 778 list<ThreadID>::iterator end = activeThreads->end(); 779 780 while (threads != end) { 781 ThreadID tid = *threads++; 782 783 if (fetchStatus[tid] == Running || 784 fetchStatus[tid] == Squashing || 785 fetchStatus[tid] == IcacheAccessComplete) { 786 787 if (_status == Inactive) { 788 DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid); 789 790 if (fetchStatus[tid] == IcacheAccessComplete) { 791 DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache" 792 "completion\n",tid); 793 } 794 795 cpu->activateStage(O3CPU::FetchIdx); 796 } 797 798 return Active; 799 } 800 } 801 802 // Stage is switching from active to inactive, notify CPU of it. 803 if (_status == Active) { 804 DPRINTF(Activity, "Deactivating stage.\n"); 805 806 cpu->deactivateStage(O3CPU::FetchIdx); 807 } 808 809 return Inactive; 810} 811 812template <class Impl> 813void 814DefaultFetch<Impl>::squash(const TheISA::PCState &newPC, 815 const InstSeqNum &seq_num, ThreadID tid) 816{ 817 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n", tid); 818 819 doSquash(newPC, tid); 820 821 // Tell the CPU to remove any instructions that are not in the ROB. 822 cpu->removeInstsNotInROB(tid); 823} 824 825template <class Impl> 826void 827DefaultFetch<Impl>::tick() 828{ 829 list<ThreadID>::iterator threads = activeThreads->begin(); 830 list<ThreadID>::iterator end = activeThreads->end(); 831 bool status_change = false; 832 833 wroteToTimeBuffer = false; 834 835 while (threads != end) { 836 ThreadID tid = *threads++; 837 838 // Check the signals for each thread to determine the proper status 839 // for each thread. 840 bool updated_status = checkSignalsAndUpdate(tid); 841 status_change = status_change || updated_status; 842 } 843 844 DPRINTF(Fetch, "Running stage.\n"); 845 846 // Reset the number of the instruction we're fetching. 847 numInst = 0; 848 849#if FULL_SYSTEM 850 if (fromCommit->commitInfo[0].interruptPending) { 851 interruptPending = true; 852 } 853 854 if (fromCommit->commitInfo[0].clearInterrupt) { 855 interruptPending = false; 856 } 857#endif 858 859 for (threadFetched = 0; threadFetched < numFetchingThreads; 860 threadFetched++) { 861 // Fetch each of the actively fetching threads. 862 fetch(status_change); 863 } 864 865 // Record number of instructions fetched this cycle for distribution. 866 fetchNisnDist.sample(numInst); 867 868 if (status_change) { 869 // Change the fetch stage status if there was a status change. 870 _status = updateFetchStatus(); 871 } 872 873 // If there was activity this cycle, inform the CPU of it. 874 if (wroteToTimeBuffer || cpu->contextSwitch) { 875 DPRINTF(Activity, "Activity this cycle.\n"); 876 877 cpu->activityThisCycle(); 878 } 879} 880 881template <class Impl> 882bool 883DefaultFetch<Impl>::checkSignalsAndUpdate(ThreadID tid) 884{ 885 // Update the per thread stall statuses. 886 if (fromDecode->decodeBlock[tid]) { 887 stalls[tid].decode = true; 888 } 889 890 if (fromDecode->decodeUnblock[tid]) { 891 assert(stalls[tid].decode); 892 assert(!fromDecode->decodeBlock[tid]); 893 stalls[tid].decode = false; 894 } 895 896 if (fromRename->renameBlock[tid]) { 897 stalls[tid].rename = true; 898 } 899 900 if (fromRename->renameUnblock[tid]) { 901 assert(stalls[tid].rename); 902 assert(!fromRename->renameBlock[tid]); 903 stalls[tid].rename = false; 904 } 905 906 if (fromIEW->iewBlock[tid]) { 907 stalls[tid].iew = true; 908 } 909 910 if (fromIEW->iewUnblock[tid]) { 911 assert(stalls[tid].iew); 912 assert(!fromIEW->iewBlock[tid]); 913 stalls[tid].iew = false; 914 } 915 916 if (fromCommit->commitBlock[tid]) { 917 stalls[tid].commit = true; 918 } 919 920 if (fromCommit->commitUnblock[tid]) { 921 assert(stalls[tid].commit); 922 assert(!fromCommit->commitBlock[tid]); 923 stalls[tid].commit = false; 924 } 925 926 // Check squash signals from commit. 927 if (fromCommit->commitInfo[tid].squash) { 928 929 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash " 930 "from commit.\n",tid); 931 // In any case, squash. 932 squash(fromCommit->commitInfo[tid].pc, 933 fromCommit->commitInfo[tid].doneSeqNum, 934 tid); 935 936 // If it was a branch mispredict on a control instruction, update the 937 // branch predictor with that instruction, otherwise just kill the 938 // invalid state we generated in after sequence number 939 assert(!fromCommit->commitInfo[tid].branchMispredict || 940 fromCommit->commitInfo[tid].mispredictInst); 941 942 if (fromCommit->commitInfo[tid].branchMispredict && 943 fromCommit->commitInfo[tid].mispredictInst->isControl()) { 944 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum, 945 fromCommit->commitInfo[tid].pc, 946 fromCommit->commitInfo[tid].branchTaken, 947 tid); 948 } else { 949 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum, 950 tid); 951 } 952 953 return true; 954 } else if (fromCommit->commitInfo[tid].doneSeqNum) { 955 // Update the branch predictor if it wasn't a squashed instruction 956 // that was broadcasted. 957 branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid); 958 } 959 960 // Check ROB squash signals from commit. 961 if (fromCommit->commitInfo[tid].robSquashing) { 962 DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid); 963 964 // Continue to squash. 965 fetchStatus[tid] = Squashing; 966 967 return true; 968 } 969 970 // Check squash signals from decode. 971 if (fromDecode->decodeInfo[tid].squash) { 972 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash " 973 "from decode.\n",tid); 974 975 // Update the branch predictor. 976 if (fromDecode->decodeInfo[tid].branchMispredict) { 977 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum, 978 fromDecode->decodeInfo[tid].nextPC, 979 fromDecode->decodeInfo[tid].branchTaken, 980 tid); 981 } else { 982 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum, 983 tid); 984 } 985 986 if (fetchStatus[tid] != Squashing) { 987 988 TheISA::PCState nextPC = fromDecode->decodeInfo[tid].nextPC; 989 DPRINTF(Fetch, "Squashing from decode with PC = %s\n", nextPC); 990 // Squash unless we're already squashing 991 squashFromDecode(fromDecode->decodeInfo[tid].nextPC, 992 fromDecode->decodeInfo[tid].doneSeqNum, 993 tid); 994 995 return true; 996 } 997 } 998 999 if (checkStall(tid) && 1000 fetchStatus[tid] != IcacheWaitResponse && 1001 fetchStatus[tid] != IcacheWaitRetry) { 1002 DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid); 1003 1004 fetchStatus[tid] = Blocked; 1005 1006 return true; 1007 } 1008 1009 if (fetchStatus[tid] == Blocked || 1010 fetchStatus[tid] == Squashing) { 1011 // Switch status to running if fetch isn't being told to block or 1012 // squash this cycle. 1013 DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n", 1014 tid); 1015 1016 fetchStatus[tid] = Running; 1017 1018 return true; 1019 } 1020 1021 // If we've reached this point, we have not gotten any signals that 1022 // cause fetch to change its status. Fetch remains the same as before. 1023 return false; 1024} 1025 1026template<class Impl> 1027typename Impl::DynInstPtr 1028DefaultFetch<Impl>::buildInst(ThreadID tid, StaticInstPtr staticInst, 1029 StaticInstPtr curMacroop, TheISA::PCState thisPC, 1030 TheISA::PCState nextPC, bool trace) 1031{ 1032 // Get a sequence number. 1033 InstSeqNum seq = cpu->getAndIncrementInstSeq(); 1034 1035 // Create a new DynInst from the instruction fetched. 1036 DynInstPtr instruction = 1037 new DynInst(staticInst, thisPC, nextPC, seq, cpu); 1038 instruction->setTid(tid); 1039 1040 instruction->setASID(tid); 1041 1042 instruction->setThreadState(cpu->thread[tid]); 1043 1044 DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x (%d) created " 1045 "[sn:%lli].\n", tid, thisPC.instAddr(), 1046 thisPC.microPC(), seq); 1047 1048 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", tid, 1049 instruction->staticInst-> 1050 disassemble(thisPC.instAddr())); 1051 1052#if TRACING_ON 1053 if (trace) { 1054 instruction->traceData = 1055 cpu->getTracer()->getInstRecord(curTick(), cpu->tcBase(tid), 1056 instruction->staticInst, thisPC, curMacroop); 1057 } 1058#else 1059 instruction->traceData = NULL; 1060#endif 1061 1062 // Add instruction to the CPU's list of instructions. 1063 instruction->setInstListIt(cpu->addInst(instruction)); 1064 1065 // Write the instruction to the first slot in the queue 1066 // that heads to decode. 1067 assert(numInst < fetchWidth); 1068 toDecode->insts[toDecode->size++] = instruction; 1069 1070 return instruction; 1071} 1072 1073template<class Impl> 1074void 1075DefaultFetch<Impl>::fetch(bool &status_change) 1076{ 1077 ////////////////////////////////////////// 1078 // Start actual fetch 1079 ////////////////////////////////////////// 1080 ThreadID tid = getFetchingThread(fetchPolicy); 1081 1082 if (tid == InvalidThreadID || drainPending) { 1083 DPRINTF(Fetch,"There are no more threads available to fetch from.\n"); 1084 1085 // Breaks looping condition in tick() 1086 threadFetched = numFetchingThreads; 1087 return; 1088 } 1089 1090 DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid); 1091 1092 // The current PC. 1093 TheISA::PCState thisPC = pc[tid]; 1094 1095 Addr pcOffset = fetchOffset[tid]; 1096 Addr fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask; 1097 1098 bool inRom = isRomMicroPC(thisPC.microPC()); 1099 1100 // If returning from the delay of a cache miss, then update the status 1101 // to running, otherwise do the cache access. Possibly move this up 1102 // to tick() function. 1103 if (fetchStatus[tid] == IcacheAccessComplete) { 1104 DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n", tid); 1105 1106 fetchStatus[tid] = Running; 1107 status_change = true; 1108 } else if (fetchStatus[tid] == Running) { 1109 // Align the fetch PC so its at the start of a cache block. 1110 Addr block_PC = icacheBlockAlignPC(fetchAddr); 1111 1112 // Unless buffer already got the block, fetch it from icache. 1113 if (!(cacheDataValid[tid] && block_PC == cacheDataPC[tid]) && !inRom) { 1114 DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read " 1115 "instruction, starting at PC %s.\n", tid, thisPC); 1116 1117 fetchCacheLine(fetchAddr, tid, thisPC.instAddr()); 1118 1119 if (fetchStatus[tid] == IcacheWaitResponse) 1120 ++icacheStallCycles; 1121 else if (fetchStatus[tid] == ItlbWait) 1122 ++fetchTlbCycles; 1123 else 1124 ++fetchMiscStallCycles; 1125 return; 1126 } else if (checkInterrupt(thisPC.instAddr()) || isSwitchedOut()) { 1127 ++fetchMiscStallCycles; 1128 return; 1129 } 1130 } else { 1131 if (fetchStatus[tid] == Idle) { 1132 ++fetchIdleCycles; 1133 DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid); 1134 } else if (fetchStatus[tid] == Blocked) { 1135 ++fetchBlockedCycles; 1136 DPRINTF(Fetch, "[tid:%i]: Fetch is blocked!\n", tid); 1137 } else if (fetchStatus[tid] == Squashing) { 1138 ++fetchSquashCycles; 1139 DPRINTF(Fetch, "[tid:%i]: Fetch is squashing!\n", tid); 1140 } else if (fetchStatus[tid] == IcacheWaitResponse) { 1141 ++icacheStallCycles; 1142 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n", 1143 tid); 1144 } else if (fetchStatus[tid] == ItlbWait) { 1145 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting ITLB walk to " 1146 "finish! \n", tid); 1147 ++fetchTlbCycles; 1148 } else if (fetchStatus[tid] == TrapPending) { 1149 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting for a pending trap\n", 1150 tid); 1151 } 1152 1153 1154 // Status is Idle, Squashing, Blocked, ItlbWait or IcacheWaitResponse 1155 // so fetch should do nothing. 1156 return; 1157 } 1158 1159 ++fetchCycles; 1160 1161 TheISA::PCState nextPC = thisPC; 1162 1163 StaticInstPtr staticInst = NULL; 1164 StaticInstPtr curMacroop = macroop[tid]; 1165 1166 // If the read of the first instruction was successful, then grab the 1167 // instructions from the rest of the cache line and put them into the 1168 // queue heading to decode. 1169 1170 DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to " 1171 "decode.\n", tid); 1172 1173 // Need to keep track of whether or not a predicted branch 1174 // ended this fetch block. 1175 bool predictedBranch = false; 1176 1177 TheISA::MachInst *cacheInsts = 1178 reinterpret_cast<TheISA::MachInst *>(cacheData[tid]); 1179 1180 const unsigned numInsts = cacheBlkSize / instSize; 1181 unsigned blkOffset = (fetchAddr - cacheDataPC[tid]) / instSize; 1182 1183 // Loop through instruction memory from the cache. 1184 while (blkOffset < numInsts && 1185 numInst < fetchWidth && 1186 !predictedBranch) { 1187 1188 // If we need to process more memory, do it now. 1189 if (!(curMacroop || inRom) && !predecoder.extMachInstReady()) { 1190 if (ISA_HAS_DELAY_SLOT && pcOffset == 0) { 1191 // Walk past any annulled delay slot instructions. 1192 Addr pcAddr = thisPC.instAddr() & BaseCPU::PCMask; 1193 while (fetchAddr != pcAddr && blkOffset < numInsts) { 1194 blkOffset++; 1195 fetchAddr += instSize; 1196 } 1197 if (blkOffset >= numInsts) 1198 break; 1199 } 1200 MachInst inst = TheISA::gtoh(cacheInsts[blkOffset]); 1201 1202 predecoder.setTC(cpu->thread[tid]->getTC()); 1203 predecoder.moreBytes(thisPC, fetchAddr, inst); 1204 1205 if (predecoder.needMoreBytes()) { 1206 blkOffset++; 1207 fetchAddr += instSize; 1208 pcOffset += instSize; 1209 } 1210 } 1211 1212 // Extract as many instructions and/or microops as we can from 1213 // the memory we've processed so far. 1214 do { 1215 if (!(curMacroop || inRom)) { 1216 if (predecoder.extMachInstReady()) { 1217 ExtMachInst extMachInst; 1218 1219 extMachInst = predecoder.getExtMachInst(thisPC); 1220 staticInst = StaticInstPtr(extMachInst, 1221 thisPC.instAddr()); 1222 1223 // Increment stat of fetched instructions. 1224 ++fetchedInsts; 1225 1226 if (staticInst->isMacroop()) { 1227 curMacroop = staticInst; 1228 } else { 1229 pcOffset = 0; 1230 } 1231 } else { 1232 // We need more bytes for this instruction. 1233 break; 1234 } 1235 } 1236 if (curMacroop || inRom) { 1237 if (inRom) { 1238 staticInst = cpu->microcodeRom.fetchMicroop( 1239 thisPC.microPC(), curMacroop); 1240 } else { 1241 staticInst = curMacroop->fetchMicroop(thisPC.microPC()); 1242 } 1243 if (staticInst->isLastMicroop()) { 1244 curMacroop = NULL; 1245 pcOffset = 0; 1246 } 1247 } 1248 1249 DynInstPtr instruction = 1250 buildInst(tid, staticInst, curMacroop, 1251 thisPC, nextPC, true); 1252 1253 numInst++; 1254 1255 nextPC = thisPC; 1256 1257 // If we're branching after this instruction, quite fetching 1258 // from the same block then. 1259 predictedBranch |= thisPC.branching(); 1260 predictedBranch |= 1261 lookupAndUpdateNextPC(instruction, nextPC); 1262 if (predictedBranch) { 1263 DPRINTF(Fetch, "Branch detected with PC = %s\n", thisPC); 1264 } 1265 1266 // Move to the next instruction, unless we have a branch. 1267 thisPC = nextPC; 1268 1269 if (instruction->isQuiesce()) { 1270 DPRINTF(Fetch, 1271 "Quiesce instruction encountered, halting fetch!"); 1272 fetchStatus[tid] = QuiescePending; 1273 status_change = true; 1274 break; 1275 } 1276 } while ((curMacroop || predecoder.extMachInstReady()) && 1277 numInst < fetchWidth); 1278 } 1279 1280 if (predictedBranch) { 1281 DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch " 1282 "instruction encountered.\n", tid); 1283 } else if (numInst >= fetchWidth) { 1284 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth " 1285 "for this cycle.\n", tid); 1286 } else if (blkOffset >= cacheBlkSize) { 1287 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache " 1288 "block.\n", tid); 1289 } 1290 1291 macroop[tid] = curMacroop; 1292 fetchOffset[tid] = pcOffset; 1293 1294 if (numInst > 0) { 1295 wroteToTimeBuffer = true; 1296 } 1297 1298 pc[tid] = thisPC; 1299} 1300 1301template<class Impl> 1302void 1303DefaultFetch<Impl>::recvRetry() 1304{ 1305 if (retryPkt != NULL) { 1306 assert(cacheBlocked); 1307 assert(retryTid != InvalidThreadID); 1308 assert(fetchStatus[retryTid] == IcacheWaitRetry); 1309 1310 if (icachePort->sendTiming(retryPkt)) { 1311 fetchStatus[retryTid] = IcacheWaitResponse; 1312 retryPkt = NULL; 1313 retryTid = InvalidThreadID; 1314 cacheBlocked = false; 1315 } 1316 } else { 1317 assert(retryTid == InvalidThreadID); 1318 // Access has been squashed since it was sent out. Just clear 1319 // the cache being blocked. 1320 cacheBlocked = false; 1321 } 1322} 1323 1324/////////////////////////////////////// 1325// // 1326// SMT FETCH POLICY MAINTAINED HERE // 1327// // 1328/////////////////////////////////////// 1329template<class Impl> 1330ThreadID 1331DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority) 1332{ 1333 if (numThreads > 1) { 1334 switch (fetch_priority) { 1335 1336 case SingleThread: 1337 return 0; 1338 1339 case RoundRobin: 1340 return roundRobin(); 1341 1342 case IQ: 1343 return iqCount(); 1344 1345 case LSQ: 1346 return lsqCount(); 1347 1348 case Branch: 1349 return branchCount(); 1350 1351 default: 1352 return InvalidThreadID; 1353 } 1354 } else { 1355 list<ThreadID>::iterator thread = activeThreads->begin(); 1356 if (thread == activeThreads->end()) { 1357 return InvalidThreadID; 1358 } 1359 1360 ThreadID tid = *thread; 1361 1362 if (fetchStatus[tid] == Running || 1363 fetchStatus[tid] == IcacheAccessComplete || 1364 fetchStatus[tid] == Idle) { 1365 return tid; 1366 } else { 1367 return InvalidThreadID; 1368 } 1369 } 1370} 1371 1372 1373template<class Impl> 1374ThreadID 1375DefaultFetch<Impl>::roundRobin() 1376{ 1377 list<ThreadID>::iterator pri_iter = priorityList.begin(); 1378 list<ThreadID>::iterator end = priorityList.end(); 1379 1380 ThreadID high_pri; 1381 1382 while (pri_iter != end) { 1383 high_pri = *pri_iter; 1384 1385 assert(high_pri <= numThreads); 1386 1387 if (fetchStatus[high_pri] == Running || 1388 fetchStatus[high_pri] == IcacheAccessComplete || 1389 fetchStatus[high_pri] == Idle) { 1390 1391 priorityList.erase(pri_iter); 1392 priorityList.push_back(high_pri); 1393 1394 return high_pri; 1395 } 1396 1397 pri_iter++; 1398 } 1399 1400 return InvalidThreadID; 1401} 1402 1403template<class Impl> 1404ThreadID 1405DefaultFetch<Impl>::iqCount() 1406{ 1407 std::priority_queue<ThreadID> PQ; 1408 1409 list<ThreadID>::iterator threads = activeThreads->begin(); 1410 list<ThreadID>::iterator end = activeThreads->end(); 1411 1412 while (threads != end) { 1413 ThreadID tid = *threads++; 1414 1415 PQ.push(fromIEW->iewInfo[tid].iqCount); 1416 } 1417 1418 while (!PQ.empty()) { 1419 ThreadID high_pri = PQ.top(); 1420 1421 if (fetchStatus[high_pri] == Running || 1422 fetchStatus[high_pri] == IcacheAccessComplete || 1423 fetchStatus[high_pri] == Idle) 1424 return high_pri; 1425 else 1426 PQ.pop(); 1427 1428 } 1429 1430 return InvalidThreadID; 1431} 1432 1433template<class Impl> 1434ThreadID 1435DefaultFetch<Impl>::lsqCount() 1436{ 1437 std::priority_queue<ThreadID> PQ; 1438 1439 list<ThreadID>::iterator threads = activeThreads->begin(); 1440 list<ThreadID>::iterator end = activeThreads->end(); 1441 1442 while (threads != end) { 1443 ThreadID tid = *threads++; 1444 1445 PQ.push(fromIEW->iewInfo[tid].ldstqCount); 1446 } 1447 1448 while (!PQ.empty()) { 1449 ThreadID high_pri = PQ.top(); 1450 1451 if (fetchStatus[high_pri] == Running || 1452 fetchStatus[high_pri] == IcacheAccessComplete || 1453 fetchStatus[high_pri] == Idle) 1454 return high_pri; 1455 else 1456 PQ.pop(); 1457 } 1458 1459 return InvalidThreadID; 1460} 1461 1462template<class Impl> 1463ThreadID 1464DefaultFetch<Impl>::branchCount() 1465{ 1466#if 0 1467 list<ThreadID>::iterator thread = activeThreads->begin(); 1468 assert(thread != activeThreads->end()); 1469 ThreadID tid = *thread; 1470#endif 1471 1472 panic("Branch Count Fetch policy unimplemented\n"); 1473 return InvalidThreadID; 1474} 1475