fetch_impl.hh revision 7963:6d955240bb62
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 * Korey Sewell 42 */ 43 44#include <algorithm> 45#include <cstring> 46 47#include "arch/isa_traits.hh" 48#include "arch/utility.hh" 49#include "base/types.hh" 50#include "config/the_isa.hh" 51#include "config/use_checker.hh" 52#include "cpu/checker/cpu.hh" 53#include "cpu/exetrace.hh" 54#include "cpu/o3/fetch.hh" 55#include "mem/packet.hh" 56#include "mem/request.hh" 57#include "params/DerivO3CPU.hh" 58#include "sim/byteswap.hh" 59#include "sim/core.hh" 60 61#if FULL_SYSTEM 62#include "arch/tlb.hh" 63#include "arch/vtophys.hh" 64#include "sim/system.hh" 65#endif // FULL_SYSTEM 66 67using namespace std; 68 69template<class Impl> 70void 71DefaultFetch<Impl>::IcachePort::setPeer(Port *port) 72{ 73 Port::setPeer(port); 74 75 fetch->setIcache(); 76} 77 78template<class Impl> 79Tick 80DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt) 81{ 82 panic("DefaultFetch doesn't expect recvAtomic callback!"); 83 return curTick(); 84} 85 86template<class Impl> 87void 88DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt) 89{ 90 DPRINTF(Fetch, "DefaultFetch doesn't update its state from a " 91 "functional call."); 92} 93 94template<class Impl> 95void 96DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status) 97{ 98 if (status == RangeChange) { 99 if (!snoopRangeSent) { 100 snoopRangeSent = true; 101 sendStatusChange(Port::RangeChange); 102 } 103 return; 104 } 105 106 panic("DefaultFetch doesn't expect recvStatusChange callback!"); 107} 108 109template<class Impl> 110bool 111DefaultFetch<Impl>::IcachePort::recvTiming(PacketPtr pkt) 112{ 113 DPRINTF(Fetch, "Received timing\n"); 114 if (pkt->isResponse()) { 115 fetch->processCacheCompletion(pkt); 116 } 117 //else Snooped a coherence request, just return 118 return true; 119} 120 121template<class Impl> 122void 123DefaultFetch<Impl>::IcachePort::recvRetry() 124{ 125 fetch->recvRetry(); 126} 127 128template<class Impl> 129DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params) 130 : cpu(_cpu), 131 branchPred(params), 132 predecoder(NULL), 133 decodeToFetchDelay(params->decodeToFetchDelay), 134 renameToFetchDelay(params->renameToFetchDelay), 135 iewToFetchDelay(params->iewToFetchDelay), 136 commitToFetchDelay(params->commitToFetchDelay), 137 fetchWidth(params->fetchWidth), 138 cacheBlocked(false), 139 retryPkt(NULL), 140 retryTid(InvalidThreadID), 141 numThreads(params->numThreads), 142 numFetchingThreads(params->smtNumFetchingThreads), 143 interruptPending(false), 144 drainPending(false), 145 switchedOut(false) 146{ 147 if (numThreads > Impl::MaxThreads) 148 fatal("numThreads (%d) is larger than compiled limit (%d),\n" 149 "\tincrease MaxThreads in src/cpu/o3/impl.hh\n", 150 numThreads, static_cast<int>(Impl::MaxThreads)); 151 152 // Set fetch stage's status to inactive. 153 _status = Inactive; 154 155 std::string policy = params->smtFetchPolicy; 156 157 // Convert string to lowercase 158 std::transform(policy.begin(), policy.end(), policy.begin(), 159 (int(*)(int)) tolower); 160 161 // Figure out fetch policy 162 if (policy == "singlethread") { 163 fetchPolicy = SingleThread; 164 if (numThreads > 1) 165 panic("Invalid Fetch Policy for a SMT workload."); 166 } else if (policy == "roundrobin") { 167 fetchPolicy = RoundRobin; 168 DPRINTF(Fetch, "Fetch policy set to Round Robin\n"); 169 } else if (policy == "branch") { 170 fetchPolicy = Branch; 171 DPRINTF(Fetch, "Fetch policy set to Branch Count\n"); 172 } else if (policy == "iqcount") { 173 fetchPolicy = IQ; 174 DPRINTF(Fetch, "Fetch policy set to IQ count\n"); 175 } else if (policy == "lsqcount") { 176 fetchPolicy = LSQ; 177 DPRINTF(Fetch, "Fetch policy set to LSQ count\n"); 178 } else { 179 fatal("Invalid Fetch Policy. Options Are: {SingleThread," 180 " RoundRobin,LSQcount,IQcount}\n"); 181 } 182 183 // Get the size of an instruction. 184 instSize = sizeof(TheISA::MachInst); 185 186 // Name is finally available, so create the port. 187 icachePort = new IcachePort(this); 188 189 icachePort->snoopRangeSent = false; 190 191#if USE_CHECKER 192 if (cpu->checker) { 193 cpu->checker->setIcachePort(icachePort); 194 } 195#endif 196} 197 198template <class Impl> 199std::string 200DefaultFetch<Impl>::name() const 201{ 202 return cpu->name() + ".fetch"; 203} 204 205template <class Impl> 206void 207DefaultFetch<Impl>::regStats() 208{ 209 icacheStallCycles 210 .name(name() + ".icacheStallCycles") 211 .desc("Number of cycles fetch is stalled on an Icache miss") 212 .prereq(icacheStallCycles); 213 214 fetchedInsts 215 .name(name() + ".Insts") 216 .desc("Number of instructions fetch has processed") 217 .prereq(fetchedInsts); 218 219 fetchedBranches 220 .name(name() + ".Branches") 221 .desc("Number of branches that fetch encountered") 222 .prereq(fetchedBranches); 223 224 predictedBranches 225 .name(name() + ".predictedBranches") 226 .desc("Number of branches that fetch has predicted taken") 227 .prereq(predictedBranches); 228 229 fetchCycles 230 .name(name() + ".Cycles") 231 .desc("Number of cycles fetch has run and was not squashing or" 232 " blocked") 233 .prereq(fetchCycles); 234 235 fetchSquashCycles 236 .name(name() + ".SquashCycles") 237 .desc("Number of cycles fetch has spent squashing") 238 .prereq(fetchSquashCycles); 239 240 fetchTlbCycles 241 .name(name() + ".TlbCycles") 242 .desc("Number of cycles fetch has spent waiting for tlb") 243 .prereq(fetchTlbCycles); 244 245 fetchIdleCycles 246 .name(name() + ".IdleCycles") 247 .desc("Number of cycles fetch was idle") 248 .prereq(fetchIdleCycles); 249 250 fetchBlockedCycles 251 .name(name() + ".BlockedCycles") 252 .desc("Number of cycles fetch has spent blocked") 253 .prereq(fetchBlockedCycles); 254 255 fetchedCacheLines 256 .name(name() + ".CacheLines") 257 .desc("Number of cache lines fetched") 258 .prereq(fetchedCacheLines); 259 260 fetchMiscStallCycles 261 .name(name() + ".MiscStallCycles") 262 .desc("Number of cycles fetch has spent waiting on interrupts, or " 263 "bad addresses, or out of MSHRs") 264 .prereq(fetchMiscStallCycles); 265 266 fetchIcacheSquashes 267 .name(name() + ".IcacheSquashes") 268 .desc("Number of outstanding Icache misses that were squashed") 269 .prereq(fetchIcacheSquashes); 270 271 fetchNisnDist 272 .init(/* base value */ 0, 273 /* last value */ fetchWidth, 274 /* bucket size */ 1) 275 .name(name() + ".rateDist") 276 .desc("Number of instructions fetched each cycle (Total)") 277 .flags(Stats::pdf); 278 279 idleRate 280 .name(name() + ".idleRate") 281 .desc("Percent of cycles fetch was idle") 282 .prereq(idleRate); 283 idleRate = fetchIdleCycles * 100 / cpu->numCycles; 284 285 branchRate 286 .name(name() + ".branchRate") 287 .desc("Number of branch fetches per cycle") 288 .flags(Stats::total); 289 branchRate = fetchedBranches / cpu->numCycles; 290 291 fetchRate 292 .name(name() + ".rate") 293 .desc("Number of inst fetches per cycle") 294 .flags(Stats::total); 295 fetchRate = fetchedInsts / cpu->numCycles; 296 297 branchPred.regStats(); 298} 299 300template<class Impl> 301void 302DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer) 303{ 304 timeBuffer = time_buffer; 305 306 // Create wires to get information from proper places in time buffer. 307 fromDecode = timeBuffer->getWire(-decodeToFetchDelay); 308 fromRename = timeBuffer->getWire(-renameToFetchDelay); 309 fromIEW = timeBuffer->getWire(-iewToFetchDelay); 310 fromCommit = timeBuffer->getWire(-commitToFetchDelay); 311} 312 313template<class Impl> 314void 315DefaultFetch<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr) 316{ 317 activeThreads = at_ptr; 318} 319 320template<class Impl> 321void 322DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 323{ 324 fetchQueue = fq_ptr; 325 326 // Create wire to write information to proper place in fetch queue. 327 toDecode = fetchQueue->getWire(0); 328} 329 330template<class Impl> 331void 332DefaultFetch<Impl>::initStage() 333{ 334 // Setup PC and nextPC with initial state. 335 for (ThreadID tid = 0; tid < numThreads; tid++) { 336 pc[tid] = cpu->pcState(tid); 337 fetchOffset[tid] = 0; 338 macroop[tid] = NULL; 339 } 340 341 for (ThreadID tid = 0; tid < numThreads; tid++) { 342 343 fetchStatus[tid] = Running; 344 345 priorityList.push_back(tid); 346 347 memReq[tid] = NULL; 348 349 stalls[tid].decode = false; 350 stalls[tid].rename = false; 351 stalls[tid].iew = false; 352 stalls[tid].commit = false; 353 } 354 355 // Schedule fetch to get the correct PC from the CPU 356 // scheduleFetchStartupEvent(1); 357 358 // Fetch needs to start fetching instructions at the very beginning, 359 // so it must start up in active state. 360 switchToActive(); 361} 362 363template<class Impl> 364void 365DefaultFetch<Impl>::setIcache() 366{ 367 // Size of cache block. 368 cacheBlkSize = icachePort->peerBlockSize(); 369 370 // Create mask to get rid of offset bits. 371 cacheBlkMask = (cacheBlkSize - 1); 372 373 for (ThreadID tid = 0; tid < numThreads; tid++) { 374 // Create space to store a cache line. 375 cacheData[tid] = new uint8_t[cacheBlkSize]; 376 cacheDataPC[tid] = 0; 377 cacheDataValid[tid] = false; 378 } 379} 380 381template<class Impl> 382void 383DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt) 384{ 385 ThreadID tid = pkt->req->threadId(); 386 387 DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n", tid); 388 389 assert(!pkt->wasNacked()); 390 391 // Only change the status if it's still waiting on the icache access 392 // to return. 393 if (fetchStatus[tid] != IcacheWaitResponse || 394 pkt->req != memReq[tid] || 395 isSwitchedOut()) { 396 ++fetchIcacheSquashes; 397 delete pkt->req; 398 delete pkt; 399 return; 400 } 401 402 memcpy(cacheData[tid], pkt->getPtr<uint8_t>(), cacheBlkSize); 403 cacheDataValid[tid] = true; 404 405 if (!drainPending) { 406 // Wake up the CPU (if it went to sleep and was waiting on 407 // this completion event). 408 cpu->wakeCPU(); 409 410 DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n", 411 tid); 412 413 switchToActive(); 414 } 415 416 // Only switch to IcacheAccessComplete if we're not stalled as well. 417 if (checkStall(tid)) { 418 fetchStatus[tid] = Blocked; 419 } else { 420 fetchStatus[tid] = IcacheAccessComplete; 421 } 422 423 // Reset the mem req to NULL. 424 delete pkt->req; 425 delete pkt; 426 memReq[tid] = NULL; 427} 428 429template <class Impl> 430bool 431DefaultFetch<Impl>::drain() 432{ 433 // Fetch is ready to drain at any time. 434 cpu->signalDrained(); 435 drainPending = true; 436 return true; 437} 438 439template <class Impl> 440void 441DefaultFetch<Impl>::resume() 442{ 443 drainPending = false; 444} 445 446template <class Impl> 447void 448DefaultFetch<Impl>::switchOut() 449{ 450 switchedOut = true; 451 // Branch predictor needs to have its state cleared. 452 branchPred.switchOut(); 453} 454 455template <class Impl> 456void 457DefaultFetch<Impl>::takeOverFrom() 458{ 459 // Reset all state 460 for (ThreadID i = 0; i < Impl::MaxThreads; ++i) { 461 stalls[i].decode = 0; 462 stalls[i].rename = 0; 463 stalls[i].iew = 0; 464 stalls[i].commit = 0; 465 pc[i] = cpu->pcState(i); 466 fetchStatus[i] = Running; 467 } 468 numInst = 0; 469 wroteToTimeBuffer = false; 470 _status = Inactive; 471 switchedOut = false; 472 interruptPending = false; 473 branchPred.takeOverFrom(); 474} 475 476template <class Impl> 477void 478DefaultFetch<Impl>::wakeFromQuiesce() 479{ 480 DPRINTF(Fetch, "Waking up from quiesce\n"); 481 // Hopefully this is safe 482 // @todo: Allow other threads to wake from quiesce. 483 fetchStatus[0] = Running; 484} 485 486template <class Impl> 487inline void 488DefaultFetch<Impl>::switchToActive() 489{ 490 if (_status == Inactive) { 491 DPRINTF(Activity, "Activating stage.\n"); 492 493 cpu->activateStage(O3CPU::FetchIdx); 494 495 _status = Active; 496 } 497} 498 499template <class Impl> 500inline void 501DefaultFetch<Impl>::switchToInactive() 502{ 503 if (_status == Active) { 504 DPRINTF(Activity, "Deactivating stage.\n"); 505 506 cpu->deactivateStage(O3CPU::FetchIdx); 507 508 _status = Inactive; 509 } 510} 511 512template <class Impl> 513bool 514DefaultFetch<Impl>::lookupAndUpdateNextPC( 515 DynInstPtr &inst, TheISA::PCState &nextPC) 516{ 517 // Do branch prediction check here. 518 // A bit of a misnomer...next_PC is actually the current PC until 519 // this function updates it. 520 bool predict_taken; 521 522 if (!inst->isControl()) { 523 TheISA::advancePC(nextPC, inst->staticInst); 524 inst->setPredTarg(nextPC); 525 inst->setPredTaken(false); 526 return false; 527 } 528 529 ThreadID tid = inst->threadNumber; 530 predict_taken = branchPred.predict(inst, nextPC, tid); 531 532 if (predict_taken) { 533 DPRINTF(Fetch, "[tid:%i]: [sn:%i]: Branch predicted to be taken to %s.\n", 534 tid, inst->seqNum, nextPC); 535 } else { 536 DPRINTF(Fetch, "[tid:%i]: [sn:%i]:Branch predicted to be not taken.\n", 537 tid, inst->seqNum); 538 } 539 540 DPRINTF(Fetch, "[tid:%i]: [sn:%i] Branch predicted to go to %s.\n", 541 tid, inst->seqNum, nextPC); 542 inst->setPredTarg(nextPC); 543 inst->setPredTaken(predict_taken); 544 545 ++fetchedBranches; 546 547 if (predict_taken) { 548 ++predictedBranches; 549 } 550 551 return predict_taken; 552} 553 554template <class Impl> 555bool 556DefaultFetch<Impl>::fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc) 557{ 558 Fault fault = NoFault; 559 560 // @todo: not sure if these should block translation. 561 //AlphaDep 562 if (cacheBlocked) { 563 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n", 564 tid); 565 return false; 566 } else if (isSwitchedOut()) { 567 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, switched out\n", 568 tid); 569 return false; 570 } else if (checkInterrupt(pc)) { 571 // Hold off fetch from getting new instructions when: 572 // Cache is blocked, or 573 // while an interrupt is pending and we're not in PAL mode, or 574 // fetch is switched out. 575 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n", 576 tid); 577 return false; 578 } 579 580 // Align the fetch address so it's at the start of a cache block. 581 Addr block_PC = icacheBlockAlignPC(vaddr); 582 583 // Setup the memReq to do a read of the first instruction's address. 584 // Set the appropriate read size and flags as well. 585 // Build request here. 586 RequestPtr mem_req = 587 new Request(tid, block_PC, cacheBlkSize, Request::INST_FETCH, 588 pc, cpu->thread[tid]->contextId(), tid); 589 590 memReq[tid] = mem_req; 591 592 // Initiate translation of the icache block 593 fetchStatus[tid] = ItlbWait; 594 FetchTranslation *trans = new FetchTranslation(this); 595 cpu->itb->translateTiming(mem_req, cpu->thread[tid]->getTC(), 596 trans, BaseTLB::Execute); 597 return true; 598} 599 600template <class Impl> 601void 602DefaultFetch<Impl>::finishTranslation(Fault fault, RequestPtr mem_req) 603{ 604 ThreadID tid = mem_req->threadId(); 605 Addr block_PC = mem_req->getVaddr(); 606 607 // Wake up CPU if it was idle 608 cpu->wakeCPU(); 609 610 // If translation was successful, attempt to read the icache block. 611 if (fault == NoFault) { 612 // Build packet here. 613 PacketPtr data_pkt = new Packet(mem_req, 614 MemCmd::ReadReq, Packet::Broadcast); 615 data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]); 616 617 cacheDataPC[tid] = block_PC; 618 cacheDataValid[tid] = false; 619 DPRINTF(Fetch, "Fetch: Doing instruction read.\n"); 620 621 fetchedCacheLines++; 622 623 // Access the cache. 624 if (!icachePort->sendTiming(data_pkt)) { 625 assert(retryPkt == NULL); 626 assert(retryTid == InvalidThreadID); 627 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid); 628 629 fetchStatus[tid] = IcacheWaitRetry; 630 retryPkt = data_pkt; 631 retryTid = tid; 632 cacheBlocked = true; 633 } else { 634 DPRINTF(Fetch, "[tid:%i]: Doing Icache access.\n", tid); 635 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache " 636 "response.\n", tid); 637 638 lastIcacheStall[tid] = curTick(); 639 fetchStatus[tid] = IcacheWaitResponse; 640 } 641 } else { 642 // Translation faulted, icache request won't be sent. 643 delete mem_req; 644 memReq[tid] = NULL; 645 646 // Send the fault to commit. This thread will not do anything 647 // until commit handles the fault. The only other way it can 648 // wake up is if a squash comes along and changes the PC. 649 TheISA::PCState fetchPC = pc[tid]; 650 651 // We will use a nop in ordier to carry the fault. 652 DynInstPtr instruction = buildInst(tid, 653 StaticInstPtr(TheISA::NoopMachInst, fetchPC.instAddr()), 654 NULL, fetchPC, fetchPC, false); 655 656 instruction->setPredTarg(fetchPC); 657 instruction->fault = fault; 658 wroteToTimeBuffer = true; 659 660 DPRINTF(Activity, "Activity this cycle.\n"); 661 cpu->activityThisCycle(); 662 663 fetchStatus[tid] = TrapPending; 664 665 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n", tid); 666 DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %s.\n", 667 tid, fault->name(), pc[tid]); 668 } 669 _status = updateFetchStatus(); 670} 671 672template <class Impl> 673inline void 674DefaultFetch<Impl>::doSquash(const TheISA::PCState &newPC, ThreadID tid) 675{ 676 DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %s.\n", 677 tid, newPC); 678 679 pc[tid] = newPC; 680 fetchOffset[tid] = 0; 681 macroop[tid] = NULL; 682 predecoder.reset(); 683 684 // Clear the icache miss if it's outstanding. 685 if (fetchStatus[tid] == IcacheWaitResponse) { 686 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n", 687 tid); 688 memReq[tid] = NULL; 689 } 690 691 // Get rid of the retrying packet if it was from this thread. 692 if (retryTid == tid) { 693 assert(cacheBlocked); 694 if (retryPkt) { 695 delete retryPkt->req; 696 delete retryPkt; 697 } 698 retryPkt = NULL; 699 retryTid = InvalidThreadID; 700 } 701 702 fetchStatus[tid] = Squashing; 703 704 ++fetchSquashCycles; 705} 706 707template<class Impl> 708void 709DefaultFetch<Impl>::squashFromDecode(const TheISA::PCState &newPC, 710 const InstSeqNum &seq_num, ThreadID tid) 711{ 712 DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n", tid); 713 714 doSquash(newPC, tid); 715 716 // Tell the CPU to remove any instructions that are in flight between 717 // fetch and decode. 718 cpu->removeInstsUntil(seq_num, tid); 719} 720 721template<class Impl> 722bool 723DefaultFetch<Impl>::checkStall(ThreadID tid) const 724{ 725 bool ret_val = false; 726 727 if (cpu->contextSwitch) { 728 DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid); 729 ret_val = true; 730 } else if (stalls[tid].decode) { 731 DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid); 732 ret_val = true; 733 } else if (stalls[tid].rename) { 734 DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid); 735 ret_val = true; 736 } else if (stalls[tid].iew) { 737 DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid); 738 ret_val = true; 739 } else if (stalls[tid].commit) { 740 DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid); 741 ret_val = true; 742 } 743 744 return ret_val; 745} 746 747template<class Impl> 748typename DefaultFetch<Impl>::FetchStatus 749DefaultFetch<Impl>::updateFetchStatus() 750{ 751 //Check Running 752 list<ThreadID>::iterator threads = activeThreads->begin(); 753 list<ThreadID>::iterator end = activeThreads->end(); 754 755 while (threads != end) { 756 ThreadID tid = *threads++; 757 758 if (fetchStatus[tid] == Running || 759 fetchStatus[tid] == Squashing || 760 fetchStatus[tid] == IcacheAccessComplete) { 761 762 if (_status == Inactive) { 763 DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid); 764 765 if (fetchStatus[tid] == IcacheAccessComplete) { 766 DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache" 767 "completion\n",tid); 768 } 769 770 cpu->activateStage(O3CPU::FetchIdx); 771 } 772 773 return Active; 774 } 775 } 776 777 // Stage is switching from active to inactive, notify CPU of it. 778 if (_status == Active) { 779 DPRINTF(Activity, "Deactivating stage.\n"); 780 781 cpu->deactivateStage(O3CPU::FetchIdx); 782 } 783 784 return Inactive; 785} 786 787template <class Impl> 788void 789DefaultFetch<Impl>::squash(const TheISA::PCState &newPC, 790 const InstSeqNum &seq_num, ThreadID tid) 791{ 792 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n", tid); 793 794 doSquash(newPC, tid); 795 796 // Tell the CPU to remove any instructions that are not in the ROB. 797 cpu->removeInstsNotInROB(tid); 798} 799 800template <class Impl> 801void 802DefaultFetch<Impl>::tick() 803{ 804 list<ThreadID>::iterator threads = activeThreads->begin(); 805 list<ThreadID>::iterator end = activeThreads->end(); 806 bool status_change = false; 807 808 wroteToTimeBuffer = false; 809 810 while (threads != end) { 811 ThreadID tid = *threads++; 812 813 // Check the signals for each thread to determine the proper status 814 // for each thread. 815 bool updated_status = checkSignalsAndUpdate(tid); 816 status_change = status_change || updated_status; 817 } 818 819 DPRINTF(Fetch, "Running stage.\n"); 820 821 // Reset the number of the instruction we're fetching. 822 numInst = 0; 823 824#if FULL_SYSTEM 825 if (fromCommit->commitInfo[0].interruptPending) { 826 interruptPending = true; 827 } 828 829 if (fromCommit->commitInfo[0].clearInterrupt) { 830 interruptPending = false; 831 } 832#endif 833 834 for (threadFetched = 0; threadFetched < numFetchingThreads; 835 threadFetched++) { 836 // Fetch each of the actively fetching threads. 837 fetch(status_change); 838 } 839 840 // Record number of instructions fetched this cycle for distribution. 841 fetchNisnDist.sample(numInst); 842 843 if (status_change) { 844 // Change the fetch stage status if there was a status change. 845 _status = updateFetchStatus(); 846 } 847 848 // If there was activity this cycle, inform the CPU of it. 849 if (wroteToTimeBuffer || cpu->contextSwitch) { 850 DPRINTF(Activity, "Activity this cycle.\n"); 851 852 cpu->activityThisCycle(); 853 } 854} 855 856template <class Impl> 857bool 858DefaultFetch<Impl>::checkSignalsAndUpdate(ThreadID tid) 859{ 860 // Update the per thread stall statuses. 861 if (fromDecode->decodeBlock[tid]) { 862 stalls[tid].decode = true; 863 } 864 865 if (fromDecode->decodeUnblock[tid]) { 866 assert(stalls[tid].decode); 867 assert(!fromDecode->decodeBlock[tid]); 868 stalls[tid].decode = false; 869 } 870 871 if (fromRename->renameBlock[tid]) { 872 stalls[tid].rename = true; 873 } 874 875 if (fromRename->renameUnblock[tid]) { 876 assert(stalls[tid].rename); 877 assert(!fromRename->renameBlock[tid]); 878 stalls[tid].rename = false; 879 } 880 881 if (fromIEW->iewBlock[tid]) { 882 stalls[tid].iew = true; 883 } 884 885 if (fromIEW->iewUnblock[tid]) { 886 assert(stalls[tid].iew); 887 assert(!fromIEW->iewBlock[tid]); 888 stalls[tid].iew = false; 889 } 890 891 if (fromCommit->commitBlock[tid]) { 892 stalls[tid].commit = true; 893 } 894 895 if (fromCommit->commitUnblock[tid]) { 896 assert(stalls[tid].commit); 897 assert(!fromCommit->commitBlock[tid]); 898 stalls[tid].commit = false; 899 } 900 901 // Check squash signals from commit. 902 if (fromCommit->commitInfo[tid].squash) { 903 904 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash " 905 "from commit.\n",tid); 906 // In any case, squash. 907 squash(fromCommit->commitInfo[tid].pc, 908 fromCommit->commitInfo[tid].doneSeqNum, 909 tid); 910 911 // If it was a branch mispredict on a control instruction, update the 912 // branch predictor with that instruction, otherwise just kill the 913 // invalid state we generated in after sequence number 914 assert(!fromCommit->commitInfo[tid].branchMispredict || 915 fromCommit->commitInfo[tid].mispredictInst); 916 917 if (fromCommit->commitInfo[tid].branchMispredict && 918 fromCommit->commitInfo[tid].mispredictInst->isControl()) { 919 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum, 920 fromCommit->commitInfo[tid].pc, 921 fromCommit->commitInfo[tid].branchTaken, 922 tid); 923 } else { 924 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum, 925 tid); 926 } 927 928 return true; 929 } else if (fromCommit->commitInfo[tid].doneSeqNum) { 930 // Update the branch predictor if it wasn't a squashed instruction 931 // that was broadcasted. 932 branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid); 933 } 934 935 // Check ROB squash signals from commit. 936 if (fromCommit->commitInfo[tid].robSquashing) { 937 DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid); 938 939 // Continue to squash. 940 fetchStatus[tid] = Squashing; 941 942 return true; 943 } 944 945 // Check squash signals from decode. 946 if (fromDecode->decodeInfo[tid].squash) { 947 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash " 948 "from decode.\n",tid); 949 950 // Update the branch predictor. 951 if (fromDecode->decodeInfo[tid].branchMispredict) { 952 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum, 953 fromDecode->decodeInfo[tid].nextPC, 954 fromDecode->decodeInfo[tid].branchTaken, 955 tid); 956 } else { 957 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum, 958 tid); 959 } 960 961 if (fetchStatus[tid] != Squashing) { 962 963 TheISA::PCState nextPC = fromDecode->decodeInfo[tid].nextPC; 964 DPRINTF(Fetch, "Squashing from decode with PC = %s\n", nextPC); 965 // Squash unless we're already squashing 966 squashFromDecode(fromDecode->decodeInfo[tid].nextPC, 967 fromDecode->decodeInfo[tid].doneSeqNum, 968 tid); 969 970 return true; 971 } 972 } 973 974 if (checkStall(tid) && 975 fetchStatus[tid] != IcacheWaitResponse && 976 fetchStatus[tid] != IcacheWaitRetry) { 977 DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid); 978 979 fetchStatus[tid] = Blocked; 980 981 return true; 982 } 983 984 if (fetchStatus[tid] == Blocked || 985 fetchStatus[tid] == Squashing) { 986 // Switch status to running if fetch isn't being told to block or 987 // squash this cycle. 988 DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n", 989 tid); 990 991 fetchStatus[tid] = Running; 992 993 return true; 994 } 995 996 // If we've reached this point, we have not gotten any signals that 997 // cause fetch to change its status. Fetch remains the same as before. 998 return false; 999} 1000 1001template<class Impl> 1002typename Impl::DynInstPtr 1003DefaultFetch<Impl>::buildInst(ThreadID tid, StaticInstPtr staticInst, 1004 StaticInstPtr curMacroop, TheISA::PCState thisPC, 1005 TheISA::PCState nextPC, bool trace) 1006{ 1007 // Get a sequence number. 1008 InstSeqNum seq = cpu->getAndIncrementInstSeq(); 1009 1010 // Create a new DynInst from the instruction fetched. 1011 DynInstPtr instruction = 1012 new DynInst(staticInst, thisPC, nextPC, seq, cpu); 1013 instruction->setTid(tid); 1014 1015 instruction->setASID(tid); 1016 1017 instruction->setThreadState(cpu->thread[tid]); 1018 1019 DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x (%d) created " 1020 "[sn:%lli].\n", tid, thisPC.instAddr(), 1021 thisPC.microPC(), seq); 1022 1023 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", tid, 1024 instruction->staticInst-> 1025 disassemble(thisPC.instAddr())); 1026 1027#if TRACING_ON 1028 if (trace) { 1029 instruction->traceData = 1030 cpu->getTracer()->getInstRecord(curTick(), cpu->tcBase(tid), 1031 instruction->staticInst, thisPC, curMacroop); 1032 } 1033#else 1034 instruction->traceData = NULL; 1035#endif 1036 1037 // Add instruction to the CPU's list of instructions. 1038 instruction->setInstListIt(cpu->addInst(instruction)); 1039 1040 // Write the instruction to the first slot in the queue 1041 // that heads to decode. 1042 assert(numInst < fetchWidth); 1043 toDecode->insts[toDecode->size++] = instruction; 1044 1045 return instruction; 1046} 1047 1048template<class Impl> 1049void 1050DefaultFetch<Impl>::fetch(bool &status_change) 1051{ 1052 ////////////////////////////////////////// 1053 // Start actual fetch 1054 ////////////////////////////////////////// 1055 ThreadID tid = getFetchingThread(fetchPolicy); 1056 1057 if (tid == InvalidThreadID || drainPending) { 1058 DPRINTF(Fetch,"There are no more threads available to fetch from.\n"); 1059 1060 // Breaks looping condition in tick() 1061 threadFetched = numFetchingThreads; 1062 return; 1063 } 1064 1065 DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid); 1066 1067 // The current PC. 1068 TheISA::PCState thisPC = pc[tid]; 1069 1070 Addr pcOffset = fetchOffset[tid]; 1071 Addr fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask; 1072 1073 bool inRom = isRomMicroPC(thisPC.microPC()); 1074 1075 // If returning from the delay of a cache miss, then update the status 1076 // to running, otherwise do the cache access. Possibly move this up 1077 // to tick() function. 1078 if (fetchStatus[tid] == IcacheAccessComplete) { 1079 DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n", tid); 1080 1081 fetchStatus[tid] = Running; 1082 status_change = true; 1083 } else if (fetchStatus[tid] == Running) { 1084 // Align the fetch PC so its at the start of a cache block. 1085 Addr block_PC = icacheBlockAlignPC(fetchAddr); 1086 1087 // Unless buffer already got the block, fetch it from icache. 1088 if (!(cacheDataValid[tid] && block_PC == cacheDataPC[tid]) && !inRom) { 1089 DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read " 1090 "instruction, starting at PC %s.\n", tid, thisPC); 1091 1092 fetchCacheLine(fetchAddr, tid, thisPC.instAddr()); 1093 1094 if (fetchStatus[tid] == IcacheWaitResponse) 1095 ++icacheStallCycles; 1096 else if (fetchStatus[tid] == ItlbWait) 1097 ++fetchTlbCycles; 1098 else 1099 ++fetchMiscStallCycles; 1100 return; 1101 } else if (checkInterrupt(thisPC.instAddr()) || isSwitchedOut()) { 1102 ++fetchMiscStallCycles; 1103 return; 1104 } 1105 } else { 1106 if (fetchStatus[tid] == Idle) { 1107 ++fetchIdleCycles; 1108 DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid); 1109 } else if (fetchStatus[tid] == Blocked) { 1110 ++fetchBlockedCycles; 1111 DPRINTF(Fetch, "[tid:%i]: Fetch is blocked!\n", tid); 1112 } else if (fetchStatus[tid] == Squashing) { 1113 ++fetchSquashCycles; 1114 DPRINTF(Fetch, "[tid:%i]: Fetch is squashing!\n", tid); 1115 } else if (fetchStatus[tid] == IcacheWaitResponse) { 1116 ++icacheStallCycles; 1117 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n", 1118 tid); 1119 } else if (fetchStatus[tid] == ItlbWait) { 1120 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting ITLB walk to " 1121 "finish! \n", tid); 1122 ++fetchTlbCycles; 1123 } 1124 1125 // Status is Idle, Squashing, Blocked, ItlbWait or IcacheWaitResponse 1126 // so fetch should do nothing. 1127 return; 1128 } 1129 1130 ++fetchCycles; 1131 1132 TheISA::PCState nextPC = thisPC; 1133 1134 StaticInstPtr staticInst = NULL; 1135 StaticInstPtr curMacroop = macroop[tid]; 1136 1137 // If the read of the first instruction was successful, then grab the 1138 // instructions from the rest of the cache line and put them into the 1139 // queue heading to decode. 1140 1141 DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to " 1142 "decode.\n", tid); 1143 1144 // Need to keep track of whether or not a predicted branch 1145 // ended this fetch block. 1146 bool predictedBranch = false; 1147 1148 TheISA::MachInst *cacheInsts = 1149 reinterpret_cast<TheISA::MachInst *>(cacheData[tid]); 1150 1151 const unsigned numInsts = cacheBlkSize / instSize; 1152 unsigned blkOffset = (fetchAddr - cacheDataPC[tid]) / instSize; 1153 1154 // Loop through instruction memory from the cache. 1155 while (blkOffset < numInsts && 1156 numInst < fetchWidth && 1157 !predictedBranch) { 1158 1159 // If we need to process more memory, do it now. 1160 if (!(curMacroop || inRom) && !predecoder.extMachInstReady()) { 1161 if (ISA_HAS_DELAY_SLOT && pcOffset == 0) { 1162 // Walk past any annulled delay slot instructions. 1163 Addr pcAddr = thisPC.instAddr() & BaseCPU::PCMask; 1164 while (fetchAddr != pcAddr && blkOffset < numInsts) { 1165 blkOffset++; 1166 fetchAddr += instSize; 1167 } 1168 if (blkOffset >= numInsts) 1169 break; 1170 } 1171 MachInst inst = TheISA::gtoh(cacheInsts[blkOffset]); 1172 1173 predecoder.setTC(cpu->thread[tid]->getTC()); 1174 predecoder.moreBytes(thisPC, fetchAddr, inst); 1175 1176 if (predecoder.needMoreBytes()) { 1177 blkOffset++; 1178 fetchAddr += instSize; 1179 pcOffset += instSize; 1180 } 1181 } 1182 1183 // Extract as many instructions and/or microops as we can from 1184 // the memory we've processed so far. 1185 do { 1186 if (!(curMacroop || inRom)) { 1187 if (predecoder.extMachInstReady()) { 1188 ExtMachInst extMachInst; 1189 1190 extMachInst = predecoder.getExtMachInst(thisPC); 1191 staticInst = StaticInstPtr(extMachInst, 1192 thisPC.instAddr()); 1193 1194 // Increment stat of fetched instructions. 1195 ++fetchedInsts; 1196 1197 if (staticInst->isMacroop()) { 1198 curMacroop = staticInst; 1199 } else { 1200 pcOffset = 0; 1201 } 1202 } else { 1203 // We need more bytes for this instruction. 1204 break; 1205 } 1206 } 1207 if (curMacroop || inRom) { 1208 if (inRom) { 1209 staticInst = cpu->microcodeRom.fetchMicroop( 1210 thisPC.microPC(), curMacroop); 1211 } else { 1212 staticInst = curMacroop->fetchMicroop(thisPC.microPC()); 1213 } 1214 if (staticInst->isLastMicroop()) { 1215 curMacroop = NULL; 1216 pcOffset = 0; 1217 } 1218 } 1219 1220 DynInstPtr instruction = 1221 buildInst(tid, staticInst, curMacroop, 1222 thisPC, nextPC, true); 1223 1224 numInst++; 1225 1226 nextPC = thisPC; 1227 1228 // If we're branching after this instruction, quite fetching 1229 // from the same block then. 1230 predictedBranch |= thisPC.branching(); 1231 predictedBranch |= 1232 lookupAndUpdateNextPC(instruction, nextPC); 1233 if (predictedBranch) { 1234 DPRINTF(Fetch, "Branch detected with PC = %s\n", thisPC); 1235 } 1236 1237 // Move to the next instruction, unless we have a branch. 1238 thisPC = nextPC; 1239 1240 if (instruction->isQuiesce()) { 1241 DPRINTF(Fetch, 1242 "Quiesce instruction encountered, halting fetch!"); 1243 fetchStatus[tid] = QuiescePending; 1244 status_change = true; 1245 break; 1246 } 1247 } while ((curMacroop || predecoder.extMachInstReady()) && 1248 numInst < fetchWidth); 1249 } 1250 1251 if (predictedBranch) { 1252 DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch " 1253 "instruction encountered.\n", tid); 1254 } else if (numInst >= fetchWidth) { 1255 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth " 1256 "for this cycle.\n", tid); 1257 } else if (blkOffset >= cacheBlkSize) { 1258 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache " 1259 "block.\n", tid); 1260 } 1261 1262 macroop[tid] = curMacroop; 1263 fetchOffset[tid] = pcOffset; 1264 1265 if (numInst > 0) { 1266 wroteToTimeBuffer = true; 1267 } 1268 1269 pc[tid] = thisPC; 1270} 1271 1272template<class Impl> 1273void 1274DefaultFetch<Impl>::recvRetry() 1275{ 1276 if (retryPkt != NULL) { 1277 assert(cacheBlocked); 1278 assert(retryTid != InvalidThreadID); 1279 assert(fetchStatus[retryTid] == IcacheWaitRetry); 1280 1281 if (icachePort->sendTiming(retryPkt)) { 1282 fetchStatus[retryTid] = IcacheWaitResponse; 1283 retryPkt = NULL; 1284 retryTid = InvalidThreadID; 1285 cacheBlocked = false; 1286 } 1287 } else { 1288 assert(retryTid == InvalidThreadID); 1289 // Access has been squashed since it was sent out. Just clear 1290 // the cache being blocked. 1291 cacheBlocked = false; 1292 } 1293} 1294 1295/////////////////////////////////////// 1296// // 1297// SMT FETCH POLICY MAINTAINED HERE // 1298// // 1299/////////////////////////////////////// 1300template<class Impl> 1301ThreadID 1302DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority) 1303{ 1304 if (numThreads > 1) { 1305 switch (fetch_priority) { 1306 1307 case SingleThread: 1308 return 0; 1309 1310 case RoundRobin: 1311 return roundRobin(); 1312 1313 case IQ: 1314 return iqCount(); 1315 1316 case LSQ: 1317 return lsqCount(); 1318 1319 case Branch: 1320 return branchCount(); 1321 1322 default: 1323 return InvalidThreadID; 1324 } 1325 } else { 1326 list<ThreadID>::iterator thread = activeThreads->begin(); 1327 if (thread == activeThreads->end()) { 1328 return InvalidThreadID; 1329 } 1330 1331 ThreadID tid = *thread; 1332 1333 if (fetchStatus[tid] == Running || 1334 fetchStatus[tid] == IcacheAccessComplete || 1335 fetchStatus[tid] == Idle) { 1336 return tid; 1337 } else { 1338 return InvalidThreadID; 1339 } 1340 } 1341} 1342 1343 1344template<class Impl> 1345ThreadID 1346DefaultFetch<Impl>::roundRobin() 1347{ 1348 list<ThreadID>::iterator pri_iter = priorityList.begin(); 1349 list<ThreadID>::iterator end = priorityList.end(); 1350 1351 ThreadID high_pri; 1352 1353 while (pri_iter != end) { 1354 high_pri = *pri_iter; 1355 1356 assert(high_pri <= numThreads); 1357 1358 if (fetchStatus[high_pri] == Running || 1359 fetchStatus[high_pri] == IcacheAccessComplete || 1360 fetchStatus[high_pri] == Idle) { 1361 1362 priorityList.erase(pri_iter); 1363 priorityList.push_back(high_pri); 1364 1365 return high_pri; 1366 } 1367 1368 pri_iter++; 1369 } 1370 1371 return InvalidThreadID; 1372} 1373 1374template<class Impl> 1375ThreadID 1376DefaultFetch<Impl>::iqCount() 1377{ 1378 std::priority_queue<ThreadID> PQ; 1379 1380 list<ThreadID>::iterator threads = activeThreads->begin(); 1381 list<ThreadID>::iterator end = activeThreads->end(); 1382 1383 while (threads != end) { 1384 ThreadID tid = *threads++; 1385 1386 PQ.push(fromIEW->iewInfo[tid].iqCount); 1387 } 1388 1389 while (!PQ.empty()) { 1390 ThreadID high_pri = PQ.top(); 1391 1392 if (fetchStatus[high_pri] == Running || 1393 fetchStatus[high_pri] == IcacheAccessComplete || 1394 fetchStatus[high_pri] == Idle) 1395 return high_pri; 1396 else 1397 PQ.pop(); 1398 1399 } 1400 1401 return InvalidThreadID; 1402} 1403 1404template<class Impl> 1405ThreadID 1406DefaultFetch<Impl>::lsqCount() 1407{ 1408 std::priority_queue<ThreadID> PQ; 1409 1410 list<ThreadID>::iterator threads = activeThreads->begin(); 1411 list<ThreadID>::iterator end = activeThreads->end(); 1412 1413 while (threads != end) { 1414 ThreadID tid = *threads++; 1415 1416 PQ.push(fromIEW->iewInfo[tid].ldstqCount); 1417 } 1418 1419 while (!PQ.empty()) { 1420 ThreadID high_pri = PQ.top(); 1421 1422 if (fetchStatus[high_pri] == Running || 1423 fetchStatus[high_pri] == IcacheAccessComplete || 1424 fetchStatus[high_pri] == Idle) 1425 return high_pri; 1426 else 1427 PQ.pop(); 1428 } 1429 1430 return InvalidThreadID; 1431} 1432 1433template<class Impl> 1434ThreadID 1435DefaultFetch<Impl>::branchCount() 1436{ 1437#if 0 1438 list<ThreadID>::iterator thread = activeThreads->begin(); 1439 assert(thread != activeThreads->end()); 1440 ThreadID tid = *thread; 1441#endif 1442 1443 panic("Branch Count Fetch policy unimplemented\n"); 1444 return InvalidThreadID; 1445} 1446