fetch_impl.hh revision 7764:03efcdc3421f
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#include <algorithm> 33#include <cstring> 34 35#include "arch/isa_traits.hh" 36#include "arch/utility.hh" 37#include "base/types.hh" 38#include "config/the_isa.hh" 39#include "config/use_checker.hh" 40#include "cpu/checker/cpu.hh" 41#include "cpu/exetrace.hh" 42#include "cpu/o3/fetch.hh" 43#include "mem/packet.hh" 44#include "mem/request.hh" 45#include "params/DerivO3CPU.hh" 46#include "sim/byteswap.hh" 47#include "sim/core.hh" 48 49#if FULL_SYSTEM 50#include "arch/tlb.hh" 51#include "arch/vtophys.hh" 52#include "sim/system.hh" 53#endif // FULL_SYSTEM 54 55using namespace std; 56 57template<class Impl> 58void 59DefaultFetch<Impl>::IcachePort::setPeer(Port *port) 60{ 61 Port::setPeer(port); 62 63 fetch->setIcache(); 64} 65 66template<class Impl> 67Tick 68DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt) 69{ 70 panic("DefaultFetch doesn't expect recvAtomic callback!"); 71 return curTick; 72} 73 74template<class Impl> 75void 76DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt) 77{ 78 DPRINTF(Fetch, "DefaultFetch doesn't update its state from a " 79 "functional call."); 80} 81 82template<class Impl> 83void 84DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status) 85{ 86 if (status == RangeChange) { 87 if (!snoopRangeSent) { 88 snoopRangeSent = true; 89 sendStatusChange(Port::RangeChange); 90 } 91 return; 92 } 93 94 panic("DefaultFetch doesn't expect recvStatusChange callback!"); 95} 96 97template<class Impl> 98bool 99DefaultFetch<Impl>::IcachePort::recvTiming(PacketPtr pkt) 100{ 101 DPRINTF(Fetch, "Received timing\n"); 102 if (pkt->isResponse()) { 103 fetch->processCacheCompletion(pkt); 104 } 105 //else Snooped a coherence request, just return 106 return true; 107} 108 109template<class Impl> 110void 111DefaultFetch<Impl>::IcachePort::recvRetry() 112{ 113 fetch->recvRetry(); 114} 115 116template<class Impl> 117DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params) 118 : cpu(_cpu), 119 branchPred(params), 120 predecoder(NULL), 121 decodeToFetchDelay(params->decodeToFetchDelay), 122 renameToFetchDelay(params->renameToFetchDelay), 123 iewToFetchDelay(params->iewToFetchDelay), 124 commitToFetchDelay(params->commitToFetchDelay), 125 fetchWidth(params->fetchWidth), 126 cacheBlocked(false), 127 retryPkt(NULL), 128 retryTid(InvalidThreadID), 129 numThreads(params->numThreads), 130 numFetchingThreads(params->smtNumFetchingThreads), 131 interruptPending(false), 132 drainPending(false), 133 switchedOut(false) 134{ 135 if (numThreads > Impl::MaxThreads) 136 fatal("numThreads (%d) is larger than compiled limit (%d),\n" 137 "\tincrease MaxThreads in src/cpu/o3/impl.hh\n", 138 numThreads, static_cast<int>(Impl::MaxThreads)); 139 140 // Set fetch stage's status to inactive. 141 _status = Inactive; 142 143 std::string policy = params->smtFetchPolicy; 144 145 // Convert string to lowercase 146 std::transform(policy.begin(), policy.end(), policy.begin(), 147 (int(*)(int)) tolower); 148 149 // Figure out fetch policy 150 if (policy == "singlethread") { 151 fetchPolicy = SingleThread; 152 if (numThreads > 1) 153 panic("Invalid Fetch Policy for a SMT workload."); 154 } else if (policy == "roundrobin") { 155 fetchPolicy = RoundRobin; 156 DPRINTF(Fetch, "Fetch policy set to Round Robin\n"); 157 } else if (policy == "branch") { 158 fetchPolicy = Branch; 159 DPRINTF(Fetch, "Fetch policy set to Branch Count\n"); 160 } else if (policy == "iqcount") { 161 fetchPolicy = IQ; 162 DPRINTF(Fetch, "Fetch policy set to IQ count\n"); 163 } else if (policy == "lsqcount") { 164 fetchPolicy = LSQ; 165 DPRINTF(Fetch, "Fetch policy set to LSQ count\n"); 166 } else { 167 fatal("Invalid Fetch Policy. Options Are: {SingleThread," 168 " RoundRobin,LSQcount,IQcount}\n"); 169 } 170 171 // Get the size of an instruction. 172 instSize = sizeof(TheISA::MachInst); 173 174 // Name is finally available, so create the port. 175 icachePort = new IcachePort(this); 176 177 icachePort->snoopRangeSent = false; 178 179#if USE_CHECKER 180 if (cpu->checker) { 181 cpu->checker->setIcachePort(icachePort); 182 } 183#endif 184} 185 186template <class Impl> 187std::string 188DefaultFetch<Impl>::name() const 189{ 190 return cpu->name() + ".fetch"; 191} 192 193template <class Impl> 194void 195DefaultFetch<Impl>::regStats() 196{ 197 icacheStallCycles 198 .name(name() + ".icacheStallCycles") 199 .desc("Number of cycles fetch is stalled on an Icache miss") 200 .prereq(icacheStallCycles); 201 202 fetchedInsts 203 .name(name() + ".Insts") 204 .desc("Number of instructions fetch has processed") 205 .prereq(fetchedInsts); 206 207 fetchedBranches 208 .name(name() + ".Branches") 209 .desc("Number of branches that fetch encountered") 210 .prereq(fetchedBranches); 211 212 predictedBranches 213 .name(name() + ".predictedBranches") 214 .desc("Number of branches that fetch has predicted taken") 215 .prereq(predictedBranches); 216 217 fetchCycles 218 .name(name() + ".Cycles") 219 .desc("Number of cycles fetch has run and was not squashing or" 220 " blocked") 221 .prereq(fetchCycles); 222 223 fetchSquashCycles 224 .name(name() + ".SquashCycles") 225 .desc("Number of cycles fetch has spent squashing") 226 .prereq(fetchSquashCycles); 227 228 fetchIdleCycles 229 .name(name() + ".IdleCycles") 230 .desc("Number of cycles fetch was idle") 231 .prereq(fetchIdleCycles); 232 233 fetchBlockedCycles 234 .name(name() + ".BlockedCycles") 235 .desc("Number of cycles fetch has spent blocked") 236 .prereq(fetchBlockedCycles); 237 238 fetchedCacheLines 239 .name(name() + ".CacheLines") 240 .desc("Number of cache lines fetched") 241 .prereq(fetchedCacheLines); 242 243 fetchMiscStallCycles 244 .name(name() + ".MiscStallCycles") 245 .desc("Number of cycles fetch has spent waiting on interrupts, or " 246 "bad addresses, or out of MSHRs") 247 .prereq(fetchMiscStallCycles); 248 249 fetchIcacheSquashes 250 .name(name() + ".IcacheSquashes") 251 .desc("Number of outstanding Icache misses that were squashed") 252 .prereq(fetchIcacheSquashes); 253 254 fetchNisnDist 255 .init(/* base value */ 0, 256 /* last value */ fetchWidth, 257 /* bucket size */ 1) 258 .name(name() + ".rateDist") 259 .desc("Number of instructions fetched each cycle (Total)") 260 .flags(Stats::pdf); 261 262 idleRate 263 .name(name() + ".idleRate") 264 .desc("Percent of cycles fetch was idle") 265 .prereq(idleRate); 266 idleRate = fetchIdleCycles * 100 / cpu->numCycles; 267 268 branchRate 269 .name(name() + ".branchRate") 270 .desc("Number of branch fetches per cycle") 271 .flags(Stats::total); 272 branchRate = fetchedBranches / cpu->numCycles; 273 274 fetchRate 275 .name(name() + ".rate") 276 .desc("Number of inst fetches per cycle") 277 .flags(Stats::total); 278 fetchRate = fetchedInsts / cpu->numCycles; 279 280 branchPred.regStats(); 281} 282 283template<class Impl> 284void 285DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer) 286{ 287 timeBuffer = time_buffer; 288 289 // Create wires to get information from proper places in time buffer. 290 fromDecode = timeBuffer->getWire(-decodeToFetchDelay); 291 fromRename = timeBuffer->getWire(-renameToFetchDelay); 292 fromIEW = timeBuffer->getWire(-iewToFetchDelay); 293 fromCommit = timeBuffer->getWire(-commitToFetchDelay); 294} 295 296template<class Impl> 297void 298DefaultFetch<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr) 299{ 300 activeThreads = at_ptr; 301} 302 303template<class Impl> 304void 305DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 306{ 307 fetchQueue = fq_ptr; 308 309 // Create wire to write information to proper place in fetch queue. 310 toDecode = fetchQueue->getWire(0); 311} 312 313template<class Impl> 314void 315DefaultFetch<Impl>::initStage() 316{ 317 // Setup PC and nextPC with initial state. 318 for (ThreadID tid = 0; tid < numThreads; tid++) { 319 pc[tid] = cpu->pcState(tid); 320 fetchOffset[tid] = 0; 321 macroop[tid] = NULL; 322 } 323 324 for (ThreadID tid = 0; tid < numThreads; tid++) { 325 326 fetchStatus[tid] = Running; 327 328 priorityList.push_back(tid); 329 330 memReq[tid] = NULL; 331 332 stalls[tid].decode = false; 333 stalls[tid].rename = false; 334 stalls[tid].iew = false; 335 stalls[tid].commit = false; 336 } 337 338 // Schedule fetch to get the correct PC from the CPU 339 // scheduleFetchStartupEvent(1); 340 341 // Fetch needs to start fetching instructions at the very beginning, 342 // so it must start up in active state. 343 switchToActive(); 344} 345 346template<class Impl> 347void 348DefaultFetch<Impl>::setIcache() 349{ 350 // Size of cache block. 351 cacheBlkSize = icachePort->peerBlockSize(); 352 353 // Create mask to get rid of offset bits. 354 cacheBlkMask = (cacheBlkSize - 1); 355 356 for (ThreadID tid = 0; tid < numThreads; tid++) { 357 // Create space to store a cache line. 358 cacheData[tid] = new uint8_t[cacheBlkSize]; 359 cacheDataPC[tid] = 0; 360 cacheDataValid[tid] = false; 361 } 362} 363 364template<class Impl> 365void 366DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt) 367{ 368 ThreadID tid = pkt->req->threadId(); 369 370 DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid); 371 372 assert(!pkt->wasNacked()); 373 374 // Only change the status if it's still waiting on the icache access 375 // to return. 376 if (fetchStatus[tid] != IcacheWaitResponse || 377 pkt->req != memReq[tid] || 378 isSwitchedOut()) { 379 ++fetchIcacheSquashes; 380 delete pkt->req; 381 delete pkt; 382 return; 383 } 384 385 memcpy(cacheData[tid], pkt->getPtr<uint8_t>(), cacheBlkSize); 386 cacheDataValid[tid] = true; 387 388 if (!drainPending) { 389 // Wake up the CPU (if it went to sleep and was waiting on 390 // this completion event). 391 cpu->wakeCPU(); 392 393 DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n", 394 tid); 395 396 switchToActive(); 397 } 398 399 // Only switch to IcacheAccessComplete if we're not stalled as well. 400 if (checkStall(tid)) { 401 fetchStatus[tid] = Blocked; 402 } else { 403 fetchStatus[tid] = IcacheAccessComplete; 404 } 405 406 // Reset the mem req to NULL. 407 delete pkt->req; 408 delete pkt; 409 memReq[tid] = NULL; 410} 411 412template <class Impl> 413bool 414DefaultFetch<Impl>::drain() 415{ 416 // Fetch is ready to drain at any time. 417 cpu->signalDrained(); 418 drainPending = true; 419 return true; 420} 421 422template <class Impl> 423void 424DefaultFetch<Impl>::resume() 425{ 426 drainPending = false; 427} 428 429template <class Impl> 430void 431DefaultFetch<Impl>::switchOut() 432{ 433 switchedOut = true; 434 // Branch predictor needs to have its state cleared. 435 branchPred.switchOut(); 436} 437 438template <class Impl> 439void 440DefaultFetch<Impl>::takeOverFrom() 441{ 442 // Reset all state 443 for (ThreadID i = 0; i < Impl::MaxThreads; ++i) { 444 stalls[i].decode = 0; 445 stalls[i].rename = 0; 446 stalls[i].iew = 0; 447 stalls[i].commit = 0; 448 pc[i] = cpu->pcState(i); 449 fetchStatus[i] = Running; 450 } 451 numInst = 0; 452 wroteToTimeBuffer = false; 453 _status = Inactive; 454 switchedOut = false; 455 interruptPending = false; 456 branchPred.takeOverFrom(); 457} 458 459template <class Impl> 460void 461DefaultFetch<Impl>::wakeFromQuiesce() 462{ 463 DPRINTF(Fetch, "Waking up from quiesce\n"); 464 // Hopefully this is safe 465 // @todo: Allow other threads to wake from quiesce. 466 fetchStatus[0] = Running; 467} 468 469template <class Impl> 470inline void 471DefaultFetch<Impl>::switchToActive() 472{ 473 if (_status == Inactive) { 474 DPRINTF(Activity, "Activating stage.\n"); 475 476 cpu->activateStage(O3CPU::FetchIdx); 477 478 _status = Active; 479 } 480} 481 482template <class Impl> 483inline void 484DefaultFetch<Impl>::switchToInactive() 485{ 486 if (_status == Active) { 487 DPRINTF(Activity, "Deactivating stage.\n"); 488 489 cpu->deactivateStage(O3CPU::FetchIdx); 490 491 _status = Inactive; 492 } 493} 494 495template <class Impl> 496bool 497DefaultFetch<Impl>::lookupAndUpdateNextPC( 498 DynInstPtr &inst, TheISA::PCState &nextPC) 499{ 500 // Do branch prediction check here. 501 // A bit of a misnomer...next_PC is actually the current PC until 502 // this function updates it. 503 bool predict_taken; 504 505 if (!inst->isControl()) { 506 TheISA::advancePC(nextPC, inst->staticInst); 507 inst->setPredTarg(nextPC); 508 inst->setPredTaken(false); 509 return false; 510 } 511 512 ThreadID tid = inst->threadNumber; 513 predict_taken = branchPred.predict(inst, nextPC, tid); 514 515 if (predict_taken) { 516 DPRINTF(Fetch, "[tid:%i]: [sn:%i]: Branch predicted to be taken to %s.\n", 517 tid, inst->seqNum, nextPC); 518 } else { 519 DPRINTF(Fetch, "[tid:%i]: [sn:%i]:Branch predicted to be not taken.\n", 520 tid, inst->seqNum); 521 } 522 523 DPRINTF(Fetch, "[tid:%i]: [sn:%i] Branch predicted to go to %s.\n", 524 tid, inst->seqNum, nextPC); 525 inst->setPredTarg(nextPC); 526 inst->setPredTaken(predict_taken); 527 528 ++fetchedBranches; 529 530 if (predict_taken) { 531 ++predictedBranches; 532 } 533 534 return predict_taken; 535} 536 537template <class Impl> 538bool 539DefaultFetch<Impl>::fetchCacheLine(Addr vaddr, Fault &ret_fault, ThreadID tid, 540 Addr pc) 541{ 542 Fault fault = NoFault; 543 544 //AlphaDep 545 if (cacheBlocked) { 546 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n", 547 tid); 548 return false; 549 } else if (isSwitchedOut()) { 550 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, switched out\n", 551 tid); 552 return false; 553 } else if (interruptPending && !(pc & 0x3)) { 554 // Hold off fetch from getting new instructions when: 555 // Cache is blocked, or 556 // while an interrupt is pending and we're not in PAL mode, or 557 // fetch is switched out. 558 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n", 559 tid); 560 return false; 561 } 562 563 // Align the fetch address so it's at the start of a cache block. 564 Addr block_PC = icacheBlockAlignPC(vaddr); 565 566 // If we've already got the block, no need to try to fetch it again. 567 if (cacheDataValid[tid] && block_PC == cacheDataPC[tid]) { 568 return true; 569 } 570 571 // Setup the memReq to do a read of the first instruction's address. 572 // Set the appropriate read size and flags as well. 573 // Build request here. 574 RequestPtr mem_req = 575 new Request(tid, block_PC, cacheBlkSize, Request::INST_FETCH, 576 pc, cpu->thread[tid]->contextId(), tid); 577 578 memReq[tid] = mem_req; 579 580 // Translate the instruction request. 581 fault = cpu->itb->translateAtomic(mem_req, cpu->thread[tid]->getTC(), 582 BaseTLB::Execute); 583 584 // In the case of faults, the fetch stage may need to stall and wait 585 // for the ITB miss to be handled. 586 587 // If translation was successful, attempt to read the first 588 // instruction. 589 if (fault == NoFault) { 590#if 0 591 if (cpu->system->memctrl->badaddr(memReq[tid]->paddr) || 592 memReq[tid]->isUncacheable()) { 593 DPRINTF(Fetch, "Fetch: Bad address %#x (hopefully on a " 594 "misspeculating path)!", 595 memReq[tid]->paddr); 596 ret_fault = TheISA::genMachineCheckFault(); 597 return false; 598 } 599#endif 600 601 // Build packet here. 602 PacketPtr data_pkt = new Packet(mem_req, 603 MemCmd::ReadReq, Packet::Broadcast); 604 data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]); 605 606 cacheDataPC[tid] = block_PC; 607 cacheDataValid[tid] = false; 608 609 DPRINTF(Fetch, "Fetch: Doing instruction read.\n"); 610 611 fetchedCacheLines++; 612 613 // Now do the timing access to see whether or not the instruction 614 // exists within the cache. 615 if (!icachePort->sendTiming(data_pkt)) { 616 assert(retryPkt == NULL); 617 assert(retryTid == InvalidThreadID); 618 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid); 619 fetchStatus[tid] = IcacheWaitRetry; 620 retryPkt = data_pkt; 621 retryTid = tid; 622 cacheBlocked = true; 623 return false; 624 } 625 626 DPRINTF(Fetch, "[tid:%i]: Doing cache access.\n", tid); 627 628 lastIcacheStall[tid] = curTick; 629 630 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache " 631 "response.\n", tid); 632 633 fetchStatus[tid] = IcacheWaitResponse; 634 } else { 635 delete mem_req; 636 memReq[tid] = NULL; 637 } 638 639 ret_fault = fault; 640 return true; 641} 642 643template <class Impl> 644inline void 645DefaultFetch<Impl>::doSquash(const TheISA::PCState &newPC, ThreadID tid) 646{ 647 DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %s.\n", 648 tid, newPC); 649 650 pc[tid] = newPC; 651 fetchOffset[tid] = 0; 652 macroop[tid] = NULL; 653 predecoder.reset(); 654 655 // Clear the icache miss if it's outstanding. 656 if (fetchStatus[tid] == IcacheWaitResponse) { 657 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n", 658 tid); 659 memReq[tid] = NULL; 660 } 661 662 // Get rid of the retrying packet if it was from this thread. 663 if (retryTid == tid) { 664 assert(cacheBlocked); 665 if (retryPkt) { 666 delete retryPkt->req; 667 delete retryPkt; 668 } 669 retryPkt = NULL; 670 retryTid = InvalidThreadID; 671 } 672 673 fetchStatus[tid] = Squashing; 674 675 ++fetchSquashCycles; 676} 677 678template<class Impl> 679void 680DefaultFetch<Impl>::squashFromDecode(const TheISA::PCState &newPC, 681 const InstSeqNum &seq_num, ThreadID tid) 682{ 683 DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n", tid); 684 685 doSquash(newPC, tid); 686 687 // Tell the CPU to remove any instructions that are in flight between 688 // fetch and decode. 689 cpu->removeInstsUntil(seq_num, tid); 690} 691 692template<class Impl> 693bool 694DefaultFetch<Impl>::checkStall(ThreadID tid) const 695{ 696 bool ret_val = false; 697 698 if (cpu->contextSwitch) { 699 DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid); 700 ret_val = true; 701 } else if (stalls[tid].decode) { 702 DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid); 703 ret_val = true; 704 } else if (stalls[tid].rename) { 705 DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid); 706 ret_val = true; 707 } else if (stalls[tid].iew) { 708 DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid); 709 ret_val = true; 710 } else if (stalls[tid].commit) { 711 DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid); 712 ret_val = true; 713 } 714 715 return ret_val; 716} 717 718template<class Impl> 719typename DefaultFetch<Impl>::FetchStatus 720DefaultFetch<Impl>::updateFetchStatus() 721{ 722 //Check Running 723 list<ThreadID>::iterator threads = activeThreads->begin(); 724 list<ThreadID>::iterator end = activeThreads->end(); 725 726 while (threads != end) { 727 ThreadID tid = *threads++; 728 729 if (fetchStatus[tid] == Running || 730 fetchStatus[tid] == Squashing || 731 fetchStatus[tid] == IcacheAccessComplete) { 732 733 if (_status == Inactive) { 734 DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid); 735 736 if (fetchStatus[tid] == IcacheAccessComplete) { 737 DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache" 738 "completion\n",tid); 739 } 740 741 cpu->activateStage(O3CPU::FetchIdx); 742 } 743 744 return Active; 745 } 746 } 747 748 // Stage is switching from active to inactive, notify CPU of it. 749 if (_status == Active) { 750 DPRINTF(Activity, "Deactivating stage.\n"); 751 752 cpu->deactivateStage(O3CPU::FetchIdx); 753 } 754 755 return Inactive; 756} 757 758template <class Impl> 759void 760DefaultFetch<Impl>::squash(const TheISA::PCState &newPC, 761 const InstSeqNum &seq_num, ThreadID tid) 762{ 763 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n", tid); 764 765 doSquash(newPC, tid); 766 767 // Tell the CPU to remove any instructions that are not in the ROB. 768 cpu->removeInstsNotInROB(tid); 769} 770 771template <class Impl> 772void 773DefaultFetch<Impl>::tick() 774{ 775 list<ThreadID>::iterator threads = activeThreads->begin(); 776 list<ThreadID>::iterator end = activeThreads->end(); 777 bool status_change = false; 778 779 wroteToTimeBuffer = false; 780 781 while (threads != end) { 782 ThreadID tid = *threads++; 783 784 // Check the signals for each thread to determine the proper status 785 // for each thread. 786 bool updated_status = checkSignalsAndUpdate(tid); 787 status_change = status_change || updated_status; 788 } 789 790 DPRINTF(Fetch, "Running stage.\n"); 791 792 // Reset the number of the instruction we're fetching. 793 numInst = 0; 794 795#if FULL_SYSTEM 796 if (fromCommit->commitInfo[0].interruptPending) { 797 interruptPending = true; 798 } 799 800 if (fromCommit->commitInfo[0].clearInterrupt) { 801 interruptPending = false; 802 } 803#endif 804 805 for (threadFetched = 0; threadFetched < numFetchingThreads; 806 threadFetched++) { 807 // Fetch each of the actively fetching threads. 808 fetch(status_change); 809 } 810 811 // Record number of instructions fetched this cycle for distribution. 812 fetchNisnDist.sample(numInst); 813 814 if (status_change) { 815 // Change the fetch stage status if there was a status change. 816 _status = updateFetchStatus(); 817 } 818 819 // If there was activity this cycle, inform the CPU of it. 820 if (wroteToTimeBuffer || cpu->contextSwitch) { 821 DPRINTF(Activity, "Activity this cycle.\n"); 822 823 cpu->activityThisCycle(); 824 } 825} 826 827template <class Impl> 828bool 829DefaultFetch<Impl>::checkSignalsAndUpdate(ThreadID tid) 830{ 831 // Update the per thread stall statuses. 832 if (fromDecode->decodeBlock[tid]) { 833 stalls[tid].decode = true; 834 } 835 836 if (fromDecode->decodeUnblock[tid]) { 837 assert(stalls[tid].decode); 838 assert(!fromDecode->decodeBlock[tid]); 839 stalls[tid].decode = false; 840 } 841 842 if (fromRename->renameBlock[tid]) { 843 stalls[tid].rename = true; 844 } 845 846 if (fromRename->renameUnblock[tid]) { 847 assert(stalls[tid].rename); 848 assert(!fromRename->renameBlock[tid]); 849 stalls[tid].rename = false; 850 } 851 852 if (fromIEW->iewBlock[tid]) { 853 stalls[tid].iew = true; 854 } 855 856 if (fromIEW->iewUnblock[tid]) { 857 assert(stalls[tid].iew); 858 assert(!fromIEW->iewBlock[tid]); 859 stalls[tid].iew = false; 860 } 861 862 if (fromCommit->commitBlock[tid]) { 863 stalls[tid].commit = true; 864 } 865 866 if (fromCommit->commitUnblock[tid]) { 867 assert(stalls[tid].commit); 868 assert(!fromCommit->commitBlock[tid]); 869 stalls[tid].commit = false; 870 } 871 872 // Check squash signals from commit. 873 if (fromCommit->commitInfo[tid].squash) { 874 875 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash " 876 "from commit.\n",tid); 877 // In any case, squash. 878 squash(fromCommit->commitInfo[tid].pc, 879 fromCommit->commitInfo[tid].doneSeqNum, 880 tid); 881 882 // Also check if there's a mispredict that happened. 883 if (fromCommit->commitInfo[tid].branchMispredict) { 884 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum, 885 fromCommit->commitInfo[tid].pc, 886 fromCommit->commitInfo[tid].branchTaken, 887 tid); 888 } else { 889 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum, 890 tid); 891 } 892 893 return true; 894 } else if (fromCommit->commitInfo[tid].doneSeqNum) { 895 // Update the branch predictor if it wasn't a squashed instruction 896 // that was broadcasted. 897 branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid); 898 } 899 900 // Check ROB squash signals from commit. 901 if (fromCommit->commitInfo[tid].robSquashing) { 902 DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid); 903 904 // Continue to squash. 905 fetchStatus[tid] = Squashing; 906 907 return true; 908 } 909 910 // Check squash signals from decode. 911 if (fromDecode->decodeInfo[tid].squash) { 912 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash " 913 "from decode.\n",tid); 914 915 // Update the branch predictor. 916 if (fromDecode->decodeInfo[tid].branchMispredict) { 917 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum, 918 fromDecode->decodeInfo[tid].nextPC, 919 fromDecode->decodeInfo[tid].branchTaken, 920 tid); 921 } else { 922 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum, 923 tid); 924 } 925 926 if (fetchStatus[tid] != Squashing) { 927 928 TheISA::PCState nextPC = fromDecode->decodeInfo[tid].nextPC; 929 DPRINTF(Fetch, "Squashing from decode with PC = %s\n", nextPC); 930 // Squash unless we're already squashing 931 squashFromDecode(fromDecode->decodeInfo[tid].nextPC, 932 fromDecode->decodeInfo[tid].doneSeqNum, 933 tid); 934 935 return true; 936 } 937 } 938 939 if (checkStall(tid) && 940 fetchStatus[tid] != IcacheWaitResponse && 941 fetchStatus[tid] != IcacheWaitRetry) { 942 DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid); 943 944 fetchStatus[tid] = Blocked; 945 946 return true; 947 } 948 949 if (fetchStatus[tid] == Blocked || 950 fetchStatus[tid] == Squashing) { 951 // Switch status to running if fetch isn't being told to block or 952 // squash this cycle. 953 DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n", 954 tid); 955 956 fetchStatus[tid] = Running; 957 958 return true; 959 } 960 961 // If we've reached this point, we have not gotten any signals that 962 // cause fetch to change its status. Fetch remains the same as before. 963 return false; 964} 965 966template<class Impl> 967typename Impl::DynInstPtr 968DefaultFetch<Impl>::buildInst(ThreadID tid, StaticInstPtr staticInst, 969 StaticInstPtr curMacroop, TheISA::PCState thisPC, 970 TheISA::PCState nextPC, bool trace) 971{ 972 // Get a sequence number. 973 InstSeqNum seq = cpu->getAndIncrementInstSeq(); 974 975 // Create a new DynInst from the instruction fetched. 976 DynInstPtr instruction = 977 new DynInst(staticInst, thisPC, nextPC, seq, cpu); 978 instruction->setTid(tid); 979 980 instruction->setASID(tid); 981 982 instruction->setThreadState(cpu->thread[tid]); 983 984 DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x (%d) created " 985 "[sn:%lli]\n", tid, thisPC.instAddr(), 986 thisPC.microPC(), seq); 987 988 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", tid, 989 instruction->staticInst-> 990 disassemble(thisPC.instAddr())); 991 992#if TRACING_ON 993 if (trace) { 994 instruction->traceData = 995 cpu->getTracer()->getInstRecord(curTick, cpu->tcBase(tid), 996 instruction->staticInst, thisPC, curMacroop); 997 } 998#else 999 instruction->traceData = NULL; 1000#endif 1001 1002 // Add instruction to the CPU's list of instructions. 1003 instruction->setInstListIt(cpu->addInst(instruction)); 1004 1005 // Write the instruction to the first slot in the queue 1006 // that heads to decode. 1007 assert(numInst < fetchWidth); 1008 toDecode->insts[toDecode->size++] = instruction; 1009 1010 return instruction; 1011} 1012 1013template<class Impl> 1014void 1015DefaultFetch<Impl>::fetch(bool &status_change) 1016{ 1017 ////////////////////////////////////////// 1018 // Start actual fetch 1019 ////////////////////////////////////////// 1020 ThreadID tid = getFetchingThread(fetchPolicy); 1021 1022 if (tid == InvalidThreadID || drainPending) { 1023 DPRINTF(Fetch,"There are no more threads available to fetch from.\n"); 1024 1025 // Breaks looping condition in tick() 1026 threadFetched = numFetchingThreads; 1027 return; 1028 } 1029 1030 DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid); 1031 1032 // The current PC. 1033 TheISA::PCState thisPC = pc[tid]; 1034 1035 // Fault code for memory access. 1036 Fault fault = NoFault; 1037 1038 Addr pcOffset = fetchOffset[tid]; 1039 Addr fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask; 1040 1041 // If returning from the delay of a cache miss, then update the status 1042 // to running, otherwise do the cache access. Possibly move this up 1043 // to tick() function. 1044 if (fetchStatus[tid] == IcacheAccessComplete) { 1045 DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n",tid); 1046 1047 fetchStatus[tid] = Running; 1048 status_change = true; 1049 } else if (fetchStatus[tid] == Running) { 1050 DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read " 1051 "instruction, starting at PC %#x.\n", tid, fetchAddr); 1052 1053 bool fetch_success = fetchCacheLine(fetchAddr, fault, tid, 1054 thisPC.instAddr()); 1055 if (!fetch_success) { 1056 if (cacheBlocked) { 1057 ++icacheStallCycles; 1058 } else { 1059 ++fetchMiscStallCycles; 1060 } 1061 return; 1062 } 1063 } else { 1064 if (fetchStatus[tid] == Idle) { 1065 ++fetchIdleCycles; 1066 DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid); 1067 } else if (fetchStatus[tid] == Blocked) { 1068 ++fetchBlockedCycles; 1069 DPRINTF(Fetch, "[tid:%i]: Fetch is blocked!\n", tid); 1070 } else if (fetchStatus[tid] == Squashing) { 1071 ++fetchSquashCycles; 1072 DPRINTF(Fetch, "[tid:%i]: Fetch is squashing!\n", tid); 1073 } else if (fetchStatus[tid] == IcacheWaitResponse) { 1074 ++icacheStallCycles; 1075 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n", tid); 1076 } 1077 1078 // Status is Idle, Squashing, Blocked, or IcacheWaitResponse, so 1079 // fetch should do nothing. 1080 return; 1081 } 1082 1083 ++fetchCycles; 1084 1085 // If we had a stall due to an icache miss, then return. 1086 if (fetchStatus[tid] == IcacheWaitResponse) { 1087 ++icacheStallCycles; 1088 status_change = true; 1089 return; 1090 } 1091 1092 TheISA::PCState nextPC = thisPC; 1093 1094 StaticInstPtr staticInst = NULL; 1095 StaticInstPtr curMacroop = macroop[tid]; 1096 1097 if (fault == NoFault) { 1098 1099 // If the read of the first instruction was successful, then grab the 1100 // instructions from the rest of the cache line and put them into the 1101 // queue heading to decode. 1102 1103 DPRINTF(Fetch, 1104 "[tid:%i]: Adding instructions to queue to decode.\n", tid); 1105 1106 // Need to keep track of whether or not a predicted branch 1107 // ended this fetch block. 1108 bool predictedBranch = false; 1109 1110 TheISA::MachInst *cacheInsts = 1111 reinterpret_cast<TheISA::MachInst *>(cacheData[tid]); 1112 1113 const unsigned numInsts = cacheBlkSize / instSize; 1114 unsigned blkOffset = (fetchAddr - cacheDataPC[tid]) / instSize; 1115 1116 // Loop through instruction memory from the cache. 1117 while (blkOffset < numInsts && 1118 numInst < fetchWidth && 1119 !predictedBranch) { 1120 1121 // If we need to process more memory, do it now. 1122 if (!curMacroop && !predecoder.extMachInstReady()) { 1123 if (ISA_HAS_DELAY_SLOT && pcOffset == 0) { 1124 // Walk past any annulled delay slot instructions. 1125 Addr pcAddr = thisPC.instAddr() & BaseCPU::PCMask; 1126 while (fetchAddr != pcAddr && blkOffset < numInsts) { 1127 blkOffset++; 1128 fetchAddr += instSize; 1129 } 1130 if (blkOffset >= numInsts) 1131 break; 1132 } 1133 MachInst inst = TheISA::gtoh(cacheInsts[blkOffset]); 1134 1135 predecoder.setTC(cpu->thread[tid]->getTC()); 1136 predecoder.moreBytes(thisPC, fetchAddr, inst); 1137 1138 if (predecoder.needMoreBytes()) { 1139 blkOffset++; 1140 fetchAddr += instSize; 1141 pcOffset += instSize; 1142 } 1143 } 1144 1145 // Extract as many instructions and/or microops as we can from 1146 // the memory we've processed so far. 1147 do { 1148 if (!curMacroop) { 1149 if (predecoder.extMachInstReady()) { 1150 ExtMachInst extMachInst; 1151 1152 extMachInst = predecoder.getExtMachInst(thisPC); 1153 pcOffset = 0; 1154 staticInst = StaticInstPtr(extMachInst, 1155 thisPC.instAddr()); 1156 1157 // Increment stat of fetched instructions. 1158 ++fetchedInsts; 1159 1160 if (staticInst->isMacroop()) 1161 curMacroop = staticInst; 1162 } else { 1163 // We need more bytes for this instruction. 1164 break; 1165 } 1166 } 1167 if (curMacroop) { 1168 staticInst = curMacroop->fetchMicroop(thisPC.microPC()); 1169 if (staticInst->isLastMicroop()) 1170 curMacroop = NULL; 1171 } 1172 1173 DynInstPtr instruction = 1174 buildInst(tid, staticInst, curMacroop, 1175 thisPC, nextPC, true); 1176 1177 numInst++; 1178 1179 nextPC = thisPC; 1180 1181 // If we're branching after this instruction, quite fetching 1182 // from the same block then. 1183 predictedBranch |= thisPC.branching(); 1184 predictedBranch |= 1185 lookupAndUpdateNextPC(instruction, nextPC); 1186 if (predictedBranch) { 1187 DPRINTF(Fetch, "Branch detected with PC = %s\n", thisPC); 1188 } 1189 1190 // Move to the next instruction, unless we have a branch. 1191 thisPC = nextPC; 1192 1193 if (instruction->isQuiesce()) { 1194 DPRINTF(Fetch, 1195 "Quiesce instruction encountered, halting fetch!"); 1196 fetchStatus[tid] = QuiescePending; 1197 status_change = true; 1198 break; 1199 } 1200 } while ((curMacroop || predecoder.extMachInstReady()) && 1201 numInst < fetchWidth); 1202 } 1203 1204 if (predictedBranch) { 1205 DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch " 1206 "instruction encountered.\n", tid); 1207 } else if (numInst >= fetchWidth) { 1208 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth " 1209 "for this cycle.\n", tid); 1210 } else if (blkOffset >= cacheBlkSize) { 1211 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache " 1212 "block.\n", tid); 1213 } 1214 } 1215 1216 macroop[tid] = curMacroop; 1217 fetchOffset[tid] = pcOffset; 1218 1219 if (numInst > 0) { 1220 wroteToTimeBuffer = true; 1221 } 1222 1223 // Now that fetching is completed, update the PC to signify what the next 1224 // cycle will be. 1225 if (fault == NoFault) { 1226 pc[tid] = nextPC; 1227 DPRINTF(Fetch, "[tid:%i]: Setting PC to %s.\n", tid, nextPC); 1228 } else { 1229 // We shouldn't be in an icache miss and also have a fault (an ITB 1230 // miss) 1231 if (fetchStatus[tid] == IcacheWaitResponse) { 1232 panic("Fetch should have exited prior to this!"); 1233 } 1234 1235 // Send the fault to commit. This thread will not do anything 1236 // until commit handles the fault. The only other way it can 1237 // wake up is if a squash comes along and changes the PC. Send the 1238 // fault on a dummy nop. 1239 staticInst = StaticInstPtr(TheISA::NoopMachInst, thisPC.instAddr()); 1240 1241 DynInstPtr instruction = 1242 buildInst(tid, staticInst, NULL, thisPC, nextPC, false); 1243 1244 TheISA::advancePC(nextPC, staticInst); 1245 instruction->setPredTarg(nextPC); 1246 instruction->fault = fault; 1247 1248 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid); 1249 1250 fetchStatus[tid] = TrapPending; 1251 status_change = true; 1252 1253 DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %s", 1254 tid, fault->name(), thisPC); 1255 } 1256} 1257 1258template<class Impl> 1259void 1260DefaultFetch<Impl>::recvRetry() 1261{ 1262 if (retryPkt != NULL) { 1263 assert(cacheBlocked); 1264 assert(retryTid != InvalidThreadID); 1265 assert(fetchStatus[retryTid] == IcacheWaitRetry); 1266 1267 if (icachePort->sendTiming(retryPkt)) { 1268 fetchStatus[retryTid] = IcacheWaitResponse; 1269 retryPkt = NULL; 1270 retryTid = InvalidThreadID; 1271 cacheBlocked = false; 1272 } 1273 } else { 1274 assert(retryTid == InvalidThreadID); 1275 // Access has been squashed since it was sent out. Just clear 1276 // the cache being blocked. 1277 cacheBlocked = false; 1278 } 1279} 1280 1281/////////////////////////////////////// 1282// // 1283// SMT FETCH POLICY MAINTAINED HERE // 1284// // 1285/////////////////////////////////////// 1286template<class Impl> 1287ThreadID 1288DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority) 1289{ 1290 if (numThreads > 1) { 1291 switch (fetch_priority) { 1292 1293 case SingleThread: 1294 return 0; 1295 1296 case RoundRobin: 1297 return roundRobin(); 1298 1299 case IQ: 1300 return iqCount(); 1301 1302 case LSQ: 1303 return lsqCount(); 1304 1305 case Branch: 1306 return branchCount(); 1307 1308 default: 1309 return InvalidThreadID; 1310 } 1311 } else { 1312 list<ThreadID>::iterator thread = activeThreads->begin(); 1313 if (thread == activeThreads->end()) { 1314 return InvalidThreadID; 1315 } 1316 1317 ThreadID tid = *thread; 1318 1319 if (fetchStatus[tid] == Running || 1320 fetchStatus[tid] == IcacheAccessComplete || 1321 fetchStatus[tid] == Idle) { 1322 return tid; 1323 } else { 1324 return InvalidThreadID; 1325 } 1326 } 1327} 1328 1329 1330template<class Impl> 1331ThreadID 1332DefaultFetch<Impl>::roundRobin() 1333{ 1334 list<ThreadID>::iterator pri_iter = priorityList.begin(); 1335 list<ThreadID>::iterator end = priorityList.end(); 1336 1337 ThreadID high_pri; 1338 1339 while (pri_iter != end) { 1340 high_pri = *pri_iter; 1341 1342 assert(high_pri <= numThreads); 1343 1344 if (fetchStatus[high_pri] == Running || 1345 fetchStatus[high_pri] == IcacheAccessComplete || 1346 fetchStatus[high_pri] == Idle) { 1347 1348 priorityList.erase(pri_iter); 1349 priorityList.push_back(high_pri); 1350 1351 return high_pri; 1352 } 1353 1354 pri_iter++; 1355 } 1356 1357 return InvalidThreadID; 1358} 1359 1360template<class Impl> 1361ThreadID 1362DefaultFetch<Impl>::iqCount() 1363{ 1364 std::priority_queue<ThreadID> PQ; 1365 1366 list<ThreadID>::iterator threads = activeThreads->begin(); 1367 list<ThreadID>::iterator end = activeThreads->end(); 1368 1369 while (threads != end) { 1370 ThreadID tid = *threads++; 1371 1372 PQ.push(fromIEW->iewInfo[tid].iqCount); 1373 } 1374 1375 while (!PQ.empty()) { 1376 ThreadID high_pri = PQ.top(); 1377 1378 if (fetchStatus[high_pri] == Running || 1379 fetchStatus[high_pri] == IcacheAccessComplete || 1380 fetchStatus[high_pri] == Idle) 1381 return high_pri; 1382 else 1383 PQ.pop(); 1384 1385 } 1386 1387 return InvalidThreadID; 1388} 1389 1390template<class Impl> 1391ThreadID 1392DefaultFetch<Impl>::lsqCount() 1393{ 1394 std::priority_queue<ThreadID> PQ; 1395 1396 list<ThreadID>::iterator threads = activeThreads->begin(); 1397 list<ThreadID>::iterator end = activeThreads->end(); 1398 1399 while (threads != end) { 1400 ThreadID tid = *threads++; 1401 1402 PQ.push(fromIEW->iewInfo[tid].ldstqCount); 1403 } 1404 1405 while (!PQ.empty()) { 1406 ThreadID high_pri = PQ.top(); 1407 1408 if (fetchStatus[high_pri] == Running || 1409 fetchStatus[high_pri] == IcacheAccessComplete || 1410 fetchStatus[high_pri] == Idle) 1411 return high_pri; 1412 else 1413 PQ.pop(); 1414 } 1415 1416 return InvalidThreadID; 1417} 1418 1419template<class Impl> 1420ThreadID 1421DefaultFetch<Impl>::branchCount() 1422{ 1423#if 0 1424 list<ThreadID>::iterator thread = activeThreads->begin(); 1425 assert(thread != activeThreads->end()); 1426 ThreadID tid = *thread; 1427#endif 1428 1429 panic("Branch Count Fetch policy unimplemented\n"); 1430 return InvalidThreadID; 1431} 1432