fetch_impl.hh revision 7615:50f6494d9b55 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 *          Korey Sewell
30 */
31
32#include <algorithm>
33#include <cstring>
34
35#include "arch/isa_traits.hh"
36#include "arch/utility.hh"
37#include "base/types.hh"
38#include "config/the_isa.hh"
39#include "config/use_checker.hh"
40#include "cpu/checker/cpu.hh"
41#include "cpu/exetrace.hh"
42#include "cpu/o3/fetch.hh"
43#include "mem/packet.hh"
44#include "mem/request.hh"
45#include "params/DerivO3CPU.hh"
46#include "sim/byteswap.hh"
47#include "sim/core.hh"
48
49#if FULL_SYSTEM
50#include "arch/tlb.hh"
51#include "arch/vtophys.hh"
52#include "sim/system.hh"
53#endif // FULL_SYSTEM
54
55using namespace std;
56
57template<class Impl>
58void
59DefaultFetch<Impl>::IcachePort::setPeer(Port *port)
60{
61    Port::setPeer(port);
62
63    fetch->setIcache();
64}
65
66template<class Impl>
67Tick
68DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt)
69{
70    panic("DefaultFetch doesn't expect recvAtomic callback!");
71    return curTick;
72}
73
74template<class Impl>
75void
76DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
77{
78    DPRINTF(Fetch, "DefaultFetch doesn't update its state from a "
79            "functional call.");
80}
81
82template<class Impl>
83void
84DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status)
85{
86    if (status == RangeChange) {
87        if (!snoopRangeSent) {
88            snoopRangeSent = true;
89            sendStatusChange(Port::RangeChange);
90        }
91        return;
92    }
93
94    panic("DefaultFetch doesn't expect recvStatusChange callback!");
95}
96
97template<class Impl>
98bool
99DefaultFetch<Impl>::IcachePort::recvTiming(PacketPtr pkt)
100{
101    DPRINTF(Fetch, "Received timing\n");
102    if (pkt->isResponse()) {
103        fetch->processCacheCompletion(pkt);
104    }
105    //else Snooped a coherence request, just return
106    return true;
107}
108
109template<class Impl>
110void
111DefaultFetch<Impl>::IcachePort::recvRetry()
112{
113    fetch->recvRetry();
114}
115
116template<class Impl>
117DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params)
118    : cpu(_cpu),
119      branchPred(params),
120      predecoder(NULL),
121      decodeToFetchDelay(params->decodeToFetchDelay),
122      renameToFetchDelay(params->renameToFetchDelay),
123      iewToFetchDelay(params->iewToFetchDelay),
124      commitToFetchDelay(params->commitToFetchDelay),
125      fetchWidth(params->fetchWidth),
126      cacheBlocked(false),
127      retryPkt(NULL),
128      retryTid(InvalidThreadID),
129      numThreads(params->numThreads),
130      numFetchingThreads(params->smtNumFetchingThreads),
131      interruptPending(false),
132      drainPending(false),
133      switchedOut(false)
134{
135    if (numThreads > Impl::MaxThreads)
136        fatal("numThreads (%d) is larger than compiled limit (%d),\n"
137              "\tincrease MaxThreads in src/cpu/o3/impl.hh\n",
138              numThreads, static_cast<int>(Impl::MaxThreads));
139
140    // Set fetch stage's status to inactive.
141    _status = Inactive;
142
143    std::string policy = params->smtFetchPolicy;
144
145    // Convert string to lowercase
146    std::transform(policy.begin(), policy.end(), policy.begin(),
147                   (int(*)(int)) tolower);
148
149    // Figure out fetch policy
150    if (policy == "singlethread") {
151        fetchPolicy = SingleThread;
152        if (numThreads > 1)
153            panic("Invalid Fetch Policy for a SMT workload.");
154    } else if (policy == "roundrobin") {
155        fetchPolicy = RoundRobin;
156        DPRINTF(Fetch, "Fetch policy set to Round Robin\n");
157    } else if (policy == "branch") {
158        fetchPolicy = Branch;
159        DPRINTF(Fetch, "Fetch policy set to Branch Count\n");
160    } else if (policy == "iqcount") {
161        fetchPolicy = IQ;
162        DPRINTF(Fetch, "Fetch policy set to IQ count\n");
163    } else if (policy == "lsqcount") {
164        fetchPolicy = LSQ;
165        DPRINTF(Fetch, "Fetch policy set to LSQ count\n");
166    } else {
167        fatal("Invalid Fetch Policy. Options Are: {SingleThread,"
168              " RoundRobin,LSQcount,IQcount}\n");
169    }
170
171    // Get the size of an instruction.
172    instSize = sizeof(TheISA::MachInst);
173
174    // Name is finally available, so create the port.
175    icachePort = new IcachePort(this);
176
177    icachePort->snoopRangeSent = false;
178
179#if USE_CHECKER
180    if (cpu->checker) {
181        cpu->checker->setIcachePort(icachePort);
182    }
183#endif
184}
185
186template <class Impl>
187std::string
188DefaultFetch<Impl>::name() const
189{
190    return cpu->name() + ".fetch";
191}
192
193template <class Impl>
194void
195DefaultFetch<Impl>::regStats()
196{
197    icacheStallCycles
198        .name(name() + ".icacheStallCycles")
199        .desc("Number of cycles fetch is stalled on an Icache miss")
200        .prereq(icacheStallCycles);
201
202    fetchedInsts
203        .name(name() + ".Insts")
204        .desc("Number of instructions fetch has processed")
205        .prereq(fetchedInsts);
206
207    fetchedBranches
208        .name(name() + ".Branches")
209        .desc("Number of branches that fetch encountered")
210        .prereq(fetchedBranches);
211
212    predictedBranches
213        .name(name() + ".predictedBranches")
214        .desc("Number of branches that fetch has predicted taken")
215        .prereq(predictedBranches);
216
217    fetchCycles
218        .name(name() + ".Cycles")
219        .desc("Number of cycles fetch has run and was not squashing or"
220              " blocked")
221        .prereq(fetchCycles);
222
223    fetchSquashCycles
224        .name(name() + ".SquashCycles")
225        .desc("Number of cycles fetch has spent squashing")
226        .prereq(fetchSquashCycles);
227
228    fetchIdleCycles
229        .name(name() + ".IdleCycles")
230        .desc("Number of cycles fetch was idle")
231        .prereq(fetchIdleCycles);
232
233    fetchBlockedCycles
234        .name(name() + ".BlockedCycles")
235        .desc("Number of cycles fetch has spent blocked")
236        .prereq(fetchBlockedCycles);
237
238    fetchedCacheLines
239        .name(name() + ".CacheLines")
240        .desc("Number of cache lines fetched")
241        .prereq(fetchedCacheLines);
242
243    fetchMiscStallCycles
244        .name(name() + ".MiscStallCycles")
245        .desc("Number of cycles fetch has spent waiting on interrupts, or "
246              "bad addresses, or out of MSHRs")
247        .prereq(fetchMiscStallCycles);
248
249    fetchIcacheSquashes
250        .name(name() + ".IcacheSquashes")
251        .desc("Number of outstanding Icache misses that were squashed")
252        .prereq(fetchIcacheSquashes);
253
254    fetchNisnDist
255        .init(/* base value */ 0,
256              /* last value */ fetchWidth,
257              /* bucket size */ 1)
258        .name(name() + ".rateDist")
259        .desc("Number of instructions fetched each cycle (Total)")
260        .flags(Stats::pdf);
261
262    idleRate
263        .name(name() + ".idleRate")
264        .desc("Percent of cycles fetch was idle")
265        .prereq(idleRate);
266    idleRate = fetchIdleCycles * 100 / cpu->numCycles;
267
268    branchRate
269        .name(name() + ".branchRate")
270        .desc("Number of branch fetches per cycle")
271        .flags(Stats::total);
272    branchRate = fetchedBranches / cpu->numCycles;
273
274    fetchRate
275        .name(name() + ".rate")
276        .desc("Number of inst fetches per cycle")
277        .flags(Stats::total);
278    fetchRate = fetchedInsts / cpu->numCycles;
279
280    branchPred.regStats();
281}
282
283template<class Impl>
284void
285DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
286{
287    timeBuffer = time_buffer;
288
289    // Create wires to get information from proper places in time buffer.
290    fromDecode = timeBuffer->getWire(-decodeToFetchDelay);
291    fromRename = timeBuffer->getWire(-renameToFetchDelay);
292    fromIEW = timeBuffer->getWire(-iewToFetchDelay);
293    fromCommit = timeBuffer->getWire(-commitToFetchDelay);
294}
295
296template<class Impl>
297void
298DefaultFetch<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr)
299{
300    activeThreads = at_ptr;
301}
302
303template<class Impl>
304void
305DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
306{
307    fetchQueue = fq_ptr;
308
309    // Create wire to write information to proper place in fetch queue.
310    toDecode = fetchQueue->getWire(0);
311}
312
313template<class Impl>
314void
315DefaultFetch<Impl>::initStage()
316{
317    // Setup PC and nextPC with initial state.
318    for (ThreadID tid = 0; tid < numThreads; tid++) {
319        PC[tid] = cpu->readPC(tid);
320        nextPC[tid] = cpu->readNextPC(tid);
321        microPC[tid] = cpu->readMicroPC(tid);
322    }
323
324    for (ThreadID tid = 0; tid < numThreads; tid++) {
325
326        fetchStatus[tid] = Running;
327
328        priorityList.push_back(tid);
329
330        memReq[tid] = NULL;
331
332        stalls[tid].decode = false;
333        stalls[tid].rename = false;
334        stalls[tid].iew = false;
335        stalls[tid].commit = false;
336    }
337
338    // Schedule fetch to get the correct PC from the CPU
339    // scheduleFetchStartupEvent(1);
340
341    // Fetch needs to start fetching instructions at the very beginning,
342    // so it must start up in active state.
343    switchToActive();
344}
345
346template<class Impl>
347void
348DefaultFetch<Impl>::setIcache()
349{
350    // Size of cache block.
351    cacheBlkSize = icachePort->peerBlockSize();
352
353    // Create mask to get rid of offset bits.
354    cacheBlkMask = (cacheBlkSize - 1);
355
356    for (ThreadID tid = 0; tid < numThreads; tid++) {
357        // Create space to store a cache line.
358        cacheData[tid] = new uint8_t[cacheBlkSize];
359        cacheDataPC[tid] = 0;
360        cacheDataValid[tid] = false;
361    }
362}
363
364template<class Impl>
365void
366DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
367{
368    ThreadID tid = pkt->req->threadId();
369
370    DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid);
371
372    assert(!pkt->wasNacked());
373
374    // Only change the status if it's still waiting on the icache access
375    // to return.
376    if (fetchStatus[tid] != IcacheWaitResponse ||
377        pkt->req != memReq[tid] ||
378        isSwitchedOut()) {
379        ++fetchIcacheSquashes;
380        delete pkt->req;
381        delete pkt;
382        return;
383    }
384
385    memcpy(cacheData[tid], pkt->getPtr<uint8_t>(), cacheBlkSize);
386    cacheDataValid[tid] = true;
387
388    if (!drainPending) {
389        // Wake up the CPU (if it went to sleep and was waiting on
390        // this completion event).
391        cpu->wakeCPU();
392
393        DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",
394                tid);
395
396        switchToActive();
397    }
398
399    // Only switch to IcacheAccessComplete if we're not stalled as well.
400    if (checkStall(tid)) {
401        fetchStatus[tid] = Blocked;
402    } else {
403        fetchStatus[tid] = IcacheAccessComplete;
404    }
405
406    // Reset the mem req to NULL.
407    delete pkt->req;
408    delete pkt;
409    memReq[tid] = NULL;
410}
411
412template <class Impl>
413bool
414DefaultFetch<Impl>::drain()
415{
416    // Fetch is ready to drain at any time.
417    cpu->signalDrained();
418    drainPending = true;
419    return true;
420}
421
422template <class Impl>
423void
424DefaultFetch<Impl>::resume()
425{
426    drainPending = false;
427}
428
429template <class Impl>
430void
431DefaultFetch<Impl>::switchOut()
432{
433    switchedOut = true;
434    // Branch predictor needs to have its state cleared.
435    branchPred.switchOut();
436}
437
438template <class Impl>
439void
440DefaultFetch<Impl>::takeOverFrom()
441{
442    // Reset all state
443    for (ThreadID i = 0; i < Impl::MaxThreads; ++i) {
444        stalls[i].decode = 0;
445        stalls[i].rename = 0;
446        stalls[i].iew = 0;
447        stalls[i].commit = 0;
448        PC[i] = cpu->readPC(i);
449        nextPC[i] = cpu->readNextPC(i);
450        microPC[i] = cpu->readMicroPC(i);
451        fetchStatus[i] = Running;
452    }
453    numInst = 0;
454    wroteToTimeBuffer = false;
455    _status = Inactive;
456    switchedOut = false;
457    interruptPending = false;
458    branchPred.takeOverFrom();
459}
460
461template <class Impl>
462void
463DefaultFetch<Impl>::wakeFromQuiesce()
464{
465    DPRINTF(Fetch, "Waking up from quiesce\n");
466    // Hopefully this is safe
467    // @todo: Allow other threads to wake from quiesce.
468    fetchStatus[0] = Running;
469}
470
471template <class Impl>
472inline void
473DefaultFetch<Impl>::switchToActive()
474{
475    if (_status == Inactive) {
476        DPRINTF(Activity, "Activating stage.\n");
477
478        cpu->activateStage(O3CPU::FetchIdx);
479
480        _status = Active;
481    }
482}
483
484template <class Impl>
485inline void
486DefaultFetch<Impl>::switchToInactive()
487{
488    if (_status == Active) {
489        DPRINTF(Activity, "Deactivating stage.\n");
490
491        cpu->deactivateStage(O3CPU::FetchIdx);
492
493        _status = Inactive;
494    }
495}
496
497template <class Impl>
498bool
499DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC,
500                                          Addr &next_NPC, Addr &next_MicroPC)
501{
502    // Do branch prediction check here.
503    // A bit of a misnomer...next_PC is actually the current PC until
504    // this function updates it.
505    bool predict_taken;
506
507    if (!inst->isControl()) {
508        if (inst->isMicroop() && !inst->isLastMicroop()) {
509            next_MicroPC++;
510        } else {
511            next_PC  = next_NPC;
512            next_NPC = next_NPC + instSize;
513            next_MicroPC = 0;
514        }
515        inst->setPredTarg(next_PC, next_NPC, next_MicroPC);
516        inst->setPredTaken(false);
517        return false;
518    }
519
520    //Assume for now that all control flow is to a different macroop which
521    //would reset the micro pc to 0.
522    next_MicroPC = 0;
523
524    ThreadID tid = inst->threadNumber;
525    Addr pred_PC = next_PC;
526    predict_taken = branchPred.predict(inst, pred_PC, tid);
527
528    if (predict_taken) {
529        DPRINTF(Fetch, "[tid:%i]: [sn:%i]:  Branch predicted to be taken to %#x.\n",
530                tid, inst->seqNum, pred_PC);
531    } else {
532        DPRINTF(Fetch, "[tid:%i]: [sn:%i]:Branch predicted to be not taken.\n",
533                tid, inst->seqNum);
534    }
535
536#if ISA_HAS_DELAY_SLOT
537    next_PC = next_NPC;
538    if (predict_taken)
539        next_NPC = pred_PC;
540    else
541        next_NPC += instSize;
542#else
543    if (predict_taken)
544        next_PC = pred_PC;
545    else
546        next_PC += instSize;
547    next_NPC = next_PC + instSize;
548#endif
549
550    DPRINTF(Fetch, "[tid:%i]: [sn:%i] Branch predicted to go to %#x and then %#x.\n",
551            tid, inst->seqNum, next_PC, next_NPC);
552    inst->setPredTarg(next_PC, next_NPC, next_MicroPC);
553    inst->setPredTaken(predict_taken);
554
555    ++fetchedBranches;
556
557    if (predict_taken) {
558        ++predictedBranches;
559    }
560
561    return predict_taken;
562}
563
564template <class Impl>
565bool
566DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, ThreadID tid)
567{
568    Fault fault = NoFault;
569
570    //AlphaDep
571    if (cacheBlocked) {
572        DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n",
573                tid);
574        return false;
575    } else if (isSwitchedOut()) {
576        DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, switched out\n",
577                tid);
578        return false;
579    } else if (interruptPending && !(fetch_PC & 0x3)) {
580        // Hold off fetch from getting new instructions when:
581        // Cache is blocked, or
582        // while an interrupt is pending and we're not in PAL mode, or
583        // fetch is switched out.
584        DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n",
585                tid);
586        return false;
587    }
588
589    // Align the fetch PC so it's at the start of a cache block.
590    Addr block_PC = icacheBlockAlignPC(fetch_PC);
591
592    // If we've already got the block, no need to try to fetch it again.
593    if (cacheDataValid[tid] && block_PC == cacheDataPC[tid]) {
594        return true;
595    }
596
597    // Setup the memReq to do a read of the first instruction's address.
598    // Set the appropriate read size and flags as well.
599    // Build request here.
600    RequestPtr mem_req =
601        new Request(tid, block_PC, cacheBlkSize, Request::INST_FETCH,
602                    fetch_PC, cpu->thread[tid]->contextId(), tid);
603
604    memReq[tid] = mem_req;
605
606    // Translate the instruction request.
607    fault = cpu->itb->translateAtomic(mem_req, cpu->thread[tid]->getTC(),
608                                      BaseTLB::Execute);
609
610    // In the case of faults, the fetch stage may need to stall and wait
611    // for the ITB miss to be handled.
612
613    // If translation was successful, attempt to read the first
614    // instruction.
615    if (fault == NoFault) {
616#if 0
617        if (cpu->system->memctrl->badaddr(memReq[tid]->paddr) ||
618            memReq[tid]->isUncacheable()) {
619            DPRINTF(Fetch, "Fetch: Bad address %#x (hopefully on a "
620                    "misspeculating path)!",
621                    memReq[tid]->paddr);
622            ret_fault = TheISA::genMachineCheckFault();
623            return false;
624        }
625#endif
626
627        // Build packet here.
628        PacketPtr data_pkt = new Packet(mem_req,
629                                        MemCmd::ReadReq, Packet::Broadcast);
630        data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]);
631
632        cacheDataPC[tid] = block_PC;
633        cacheDataValid[tid] = false;
634
635        DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
636
637        fetchedCacheLines++;
638
639        // Now do the timing access to see whether or not the instruction
640        // exists within the cache.
641        if (!icachePort->sendTiming(data_pkt)) {
642            assert(retryPkt == NULL);
643            assert(retryTid == InvalidThreadID);
644            DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
645            fetchStatus[tid] = IcacheWaitRetry;
646            retryPkt = data_pkt;
647            retryTid = tid;
648            cacheBlocked = true;
649            return false;
650        }
651
652        DPRINTF(Fetch, "[tid:%i]: Doing cache access.\n", tid);
653
654        lastIcacheStall[tid] = curTick;
655
656        DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
657                "response.\n", tid);
658
659        fetchStatus[tid] = IcacheWaitResponse;
660    } else {
661        delete mem_req;
662        memReq[tid] = NULL;
663    }
664
665    ret_fault = fault;
666    return true;
667}
668
669template <class Impl>
670inline void
671DefaultFetch<Impl>::doSquash(const Addr &new_PC,
672        const Addr &new_NPC, const Addr &new_microPC, ThreadID tid)
673{
674    DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x, NPC to: %#x.\n",
675            tid, new_PC, new_NPC);
676
677    PC[tid] = new_PC;
678    nextPC[tid] = new_NPC;
679    microPC[tid] = new_microPC;
680
681    // Clear the icache miss if it's outstanding.
682    if (fetchStatus[tid] == IcacheWaitResponse) {
683        DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
684                tid);
685        memReq[tid] = NULL;
686    }
687
688    // Get rid of the retrying packet if it was from this thread.
689    if (retryTid == tid) {
690        assert(cacheBlocked);
691        if (retryPkt) {
692            delete retryPkt->req;
693            delete retryPkt;
694        }
695        retryPkt = NULL;
696        retryTid = InvalidThreadID;
697    }
698
699    fetchStatus[tid] = Squashing;
700
701    ++fetchSquashCycles;
702}
703
704template<class Impl>
705void
706DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC, const Addr &new_NPC,
707                                     const Addr &new_MicroPC,
708                                     const InstSeqNum &seq_num, ThreadID tid)
709{
710    DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid);
711
712    doSquash(new_PC, new_NPC, new_MicroPC, tid);
713
714    // Tell the CPU to remove any instructions that are in flight between
715    // fetch and decode.
716    cpu->removeInstsUntil(seq_num, tid);
717}
718
719template<class Impl>
720bool
721DefaultFetch<Impl>::checkStall(ThreadID tid) const
722{
723    bool ret_val = false;
724
725    if (cpu->contextSwitch) {
726        DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid);
727        ret_val = true;
728    } else if (stalls[tid].decode) {
729        DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid);
730        ret_val = true;
731    } else if (stalls[tid].rename) {
732        DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid);
733        ret_val = true;
734    } else if (stalls[tid].iew) {
735        DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid);
736        ret_val = true;
737    } else if (stalls[tid].commit) {
738        DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid);
739        ret_val = true;
740    }
741
742    return ret_val;
743}
744
745template<class Impl>
746typename DefaultFetch<Impl>::FetchStatus
747DefaultFetch<Impl>::updateFetchStatus()
748{
749    //Check Running
750    list<ThreadID>::iterator threads = activeThreads->begin();
751    list<ThreadID>::iterator end = activeThreads->end();
752
753    while (threads != end) {
754        ThreadID tid = *threads++;
755
756        if (fetchStatus[tid] == Running ||
757            fetchStatus[tid] == Squashing ||
758            fetchStatus[tid] == IcacheAccessComplete) {
759
760            if (_status == Inactive) {
761                DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid);
762
763                if (fetchStatus[tid] == IcacheAccessComplete) {
764                    DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache"
765                            "completion\n",tid);
766                }
767
768                cpu->activateStage(O3CPU::FetchIdx);
769            }
770
771            return Active;
772        }
773    }
774
775    // Stage is switching from active to inactive, notify CPU of it.
776    if (_status == Active) {
777        DPRINTF(Activity, "Deactivating stage.\n");
778
779        cpu->deactivateStage(O3CPU::FetchIdx);
780    }
781
782    return Inactive;
783}
784
785template <class Impl>
786void
787DefaultFetch<Impl>::squash(const Addr &new_PC, const Addr &new_NPC,
788                           const Addr &new_MicroPC,
789                           const InstSeqNum &seq_num, ThreadID tid)
790{
791    DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid);
792
793    doSquash(new_PC, new_NPC, new_MicroPC, tid);
794
795    // Tell the CPU to remove any instructions that are not in the ROB.
796    cpu->removeInstsNotInROB(tid);
797}
798
799template <class Impl>
800void
801DefaultFetch<Impl>::tick()
802{
803    list<ThreadID>::iterator threads = activeThreads->begin();
804    list<ThreadID>::iterator end = activeThreads->end();
805    bool status_change = false;
806
807    wroteToTimeBuffer = false;
808
809    while (threads != end) {
810        ThreadID tid = *threads++;
811
812        // Check the signals for each thread to determine the proper status
813        // for each thread.
814        bool updated_status = checkSignalsAndUpdate(tid);
815        status_change =  status_change || updated_status;
816    }
817
818    DPRINTF(Fetch, "Running stage.\n");
819
820    // Reset the number of the instruction we're fetching.
821    numInst = 0;
822
823#if FULL_SYSTEM
824    if (fromCommit->commitInfo[0].interruptPending) {
825        interruptPending = true;
826    }
827
828    if (fromCommit->commitInfo[0].clearInterrupt) {
829        interruptPending = false;
830    }
831#endif
832
833    for (threadFetched = 0; threadFetched < numFetchingThreads;
834         threadFetched++) {
835        // Fetch each of the actively fetching threads.
836        fetch(status_change);
837    }
838
839    // Record number of instructions fetched this cycle for distribution.
840    fetchNisnDist.sample(numInst);
841
842    if (status_change) {
843        // Change the fetch stage status if there was a status change.
844        _status = updateFetchStatus();
845    }
846
847    // If there was activity this cycle, inform the CPU of it.
848    if (wroteToTimeBuffer || cpu->contextSwitch) {
849        DPRINTF(Activity, "Activity this cycle.\n");
850
851        cpu->activityThisCycle();
852    }
853}
854
855template <class Impl>
856bool
857DefaultFetch<Impl>::checkSignalsAndUpdate(ThreadID tid)
858{
859    // Update the per thread stall statuses.
860    if (fromDecode->decodeBlock[tid]) {
861        stalls[tid].decode = true;
862    }
863
864    if (fromDecode->decodeUnblock[tid]) {
865        assert(stalls[tid].decode);
866        assert(!fromDecode->decodeBlock[tid]);
867        stalls[tid].decode = false;
868    }
869
870    if (fromRename->renameBlock[tid]) {
871        stalls[tid].rename = true;
872    }
873
874    if (fromRename->renameUnblock[tid]) {
875        assert(stalls[tid].rename);
876        assert(!fromRename->renameBlock[tid]);
877        stalls[tid].rename = false;
878    }
879
880    if (fromIEW->iewBlock[tid]) {
881        stalls[tid].iew = true;
882    }
883
884    if (fromIEW->iewUnblock[tid]) {
885        assert(stalls[tid].iew);
886        assert(!fromIEW->iewBlock[tid]);
887        stalls[tid].iew = false;
888    }
889
890    if (fromCommit->commitBlock[tid]) {
891        stalls[tid].commit = true;
892    }
893
894    if (fromCommit->commitUnblock[tid]) {
895        assert(stalls[tid].commit);
896        assert(!fromCommit->commitBlock[tid]);
897        stalls[tid].commit = false;
898    }
899
900    // Check squash signals from commit.
901    if (fromCommit->commitInfo[tid].squash) {
902
903        DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
904                "from commit.\n",tid);
905        // In any case, squash.
906        squash(fromCommit->commitInfo[tid].nextPC,
907               fromCommit->commitInfo[tid].nextNPC,
908               fromCommit->commitInfo[tid].nextMicroPC,
909               fromCommit->commitInfo[tid].doneSeqNum,
910               tid);
911
912        // Also check if there's a mispredict that happened.
913        if (fromCommit->commitInfo[tid].branchMispredict) {
914            branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
915                              fromCommit->commitInfo[tid].nextPC,
916                              fromCommit->commitInfo[tid].branchTaken,
917                              tid);
918        } else {
919            branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
920                              tid);
921        }
922
923        return true;
924    } else if (fromCommit->commitInfo[tid].doneSeqNum) {
925        // Update the branch predictor if it wasn't a squashed instruction
926        // that was broadcasted.
927        branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid);
928    }
929
930    // Check ROB squash signals from commit.
931    if (fromCommit->commitInfo[tid].robSquashing) {
932        DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid);
933
934        // Continue to squash.
935        fetchStatus[tid] = Squashing;
936
937        return true;
938    }
939
940    // Check squash signals from decode.
941    if (fromDecode->decodeInfo[tid].squash) {
942        DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
943                "from decode.\n",tid);
944
945        // Update the branch predictor.
946        if (fromDecode->decodeInfo[tid].branchMispredict) {
947            branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
948                              fromDecode->decodeInfo[tid].nextPC,
949                              fromDecode->decodeInfo[tid].branchTaken,
950                              tid);
951        } else {
952            branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
953                              tid);
954        }
955
956        if (fetchStatus[tid] != Squashing) {
957
958            DPRINTF(Fetch, "Squashing from decode with PC = %#x, NPC = %#x\n",
959                    fromDecode->decodeInfo[tid].nextPC,
960                    fromDecode->decodeInfo[tid].nextNPC);
961            // Squash unless we're already squashing
962            squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
963                             fromDecode->decodeInfo[tid].nextNPC,
964                             fromDecode->decodeInfo[tid].nextMicroPC,
965                             fromDecode->decodeInfo[tid].doneSeqNum,
966                             tid);
967
968            return true;
969        }
970    }
971
972    if (checkStall(tid) &&
973        fetchStatus[tid] != IcacheWaitResponse &&
974        fetchStatus[tid] != IcacheWaitRetry) {
975        DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid);
976
977        fetchStatus[tid] = Blocked;
978
979        return true;
980    }
981
982    if (fetchStatus[tid] == Blocked ||
983        fetchStatus[tid] == Squashing) {
984        // Switch status to running if fetch isn't being told to block or
985        // squash this cycle.
986        DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n",
987                tid);
988
989        fetchStatus[tid] = Running;
990
991        return true;
992    }
993
994    // If we've reached this point, we have not gotten any signals that
995    // cause fetch to change its status.  Fetch remains the same as before.
996    return false;
997}
998
999template<class Impl>
1000void
1001DefaultFetch<Impl>::fetch(bool &status_change)
1002{
1003    //////////////////////////////////////////
1004    // Start actual fetch
1005    //////////////////////////////////////////
1006    ThreadID tid = getFetchingThread(fetchPolicy);
1007
1008    if (tid == InvalidThreadID || drainPending) {
1009        DPRINTF(Fetch,"There are no more threads available to fetch from.\n");
1010
1011        // Breaks looping condition in tick()
1012        threadFetched = numFetchingThreads;
1013        return;
1014    }
1015
1016    DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
1017
1018    // The current PC.
1019    Addr fetch_PC = PC[tid];
1020    Addr fetch_NPC = nextPC[tid];
1021    Addr fetch_MicroPC = microPC[tid];
1022
1023    // Fault code for memory access.
1024    Fault fault = NoFault;
1025
1026    // If returning from the delay of a cache miss, then update the status
1027    // to running, otherwise do the cache access.  Possibly move this up
1028    // to tick() function.
1029    if (fetchStatus[tid] == IcacheAccessComplete) {
1030        DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n",
1031                tid);
1032
1033        fetchStatus[tid] = Running;
1034        status_change = true;
1035    } else if (fetchStatus[tid] == Running) {
1036        DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
1037                "instruction, starting at PC %08p.\n",
1038                tid, fetch_PC);
1039
1040        bool fetch_success = fetchCacheLine(fetch_PC, fault, tid);
1041        if (!fetch_success) {
1042            if (cacheBlocked) {
1043                ++icacheStallCycles;
1044            } else {
1045                ++fetchMiscStallCycles;
1046            }
1047            return;
1048        }
1049    } else {
1050        if (fetchStatus[tid] == Idle) {
1051            ++fetchIdleCycles;
1052            DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid);
1053        } else if (fetchStatus[tid] == Blocked) {
1054            ++fetchBlockedCycles;
1055            DPRINTF(Fetch, "[tid:%i]: Fetch is blocked!\n", tid);
1056        } else if (fetchStatus[tid] == Squashing) {
1057            ++fetchSquashCycles;
1058            DPRINTF(Fetch, "[tid:%i]: Fetch is squashing!\n", tid);
1059        } else if (fetchStatus[tid] == IcacheWaitResponse) {
1060            ++icacheStallCycles;
1061            DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n", tid);
1062        }
1063
1064        // Status is Idle, Squashing, Blocked, or IcacheWaitResponse, so
1065        // fetch should do nothing.
1066        return;
1067    }
1068
1069    ++fetchCycles;
1070
1071    // If we had a stall due to an icache miss, then return.
1072    if (fetchStatus[tid] == IcacheWaitResponse) {
1073        ++icacheStallCycles;
1074        status_change = true;
1075        return;
1076    }
1077
1078    Addr next_PC = fetch_PC;
1079    Addr next_NPC = fetch_NPC;
1080    Addr next_MicroPC = fetch_MicroPC;
1081
1082    InstSeqNum inst_seq;
1083    MachInst inst;
1084    ExtMachInst ext_inst;
1085    // @todo: Fix this hack.
1086    unsigned offset = (fetch_PC & cacheBlkMask) & ~3;
1087
1088    StaticInstPtr staticInst = NULL;
1089    StaticInstPtr macroop = NULL;
1090
1091    if (fault == NoFault) {
1092        // If the read of the first instruction was successful, then grab the
1093        // instructions from the rest of the cache line and put them into the
1094        // queue heading to decode.
1095
1096        DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
1097                "decode.\n",tid);
1098
1099        // Need to keep track of whether or not a predicted branch
1100        // ended this fetch block.
1101        bool predicted_branch = false;
1102
1103        while (offset < cacheBlkSize &&
1104               numInst < fetchWidth &&
1105               !predicted_branch) {
1106
1107            // If we're branching after this instruction, quite fetching
1108            // from the same block then.
1109            predicted_branch =
1110                (fetch_PC + sizeof(TheISA::MachInst) != fetch_NPC);
1111            if (predicted_branch) {
1112                DPRINTF(Fetch, "Branch detected with PC = %#x, NPC = %#x\n",
1113                        fetch_PC, fetch_NPC);
1114            }
1115
1116            // Make sure this is a valid index.
1117            assert(offset <= cacheBlkSize - instSize);
1118
1119            if (!macroop) {
1120                // Get the instruction from the array of the cache line.
1121                inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
1122                            (&cacheData[tid][offset]));
1123
1124                predecoder.setTC(cpu->thread[tid]->getTC());
1125                predecoder.moreBytes(fetch_PC, fetch_PC, inst);
1126
1127                ext_inst = predecoder.getExtMachInst();
1128                staticInst = StaticInstPtr(ext_inst, fetch_PC);
1129                if (staticInst->isMacroop())
1130                    macroop = staticInst;
1131            }
1132            do {
1133                if (macroop) {
1134                    staticInst = macroop->fetchMicroop(fetch_MicroPC);
1135                    if (staticInst->isLastMicroop())
1136                        macroop = NULL;
1137                }
1138
1139                // Get a sequence number.
1140                inst_seq = cpu->getAndIncrementInstSeq();
1141
1142                // Create a new DynInst from the instruction fetched.
1143                DynInstPtr instruction = new DynInst(staticInst,
1144                                                     fetch_PC, fetch_NPC, fetch_MicroPC,
1145                                                     next_PC, next_NPC, next_MicroPC,
1146                                                     inst_seq, cpu);
1147                instruction->setTid(tid);
1148
1149                instruction->setASID(tid);
1150
1151                instruction->setThreadState(cpu->thread[tid]);
1152
1153                DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created "
1154                        "[sn:%lli]\n",
1155                        tid, instruction->readPC(), inst_seq);
1156
1157                //DPRINTF(Fetch, "[tid:%i]: MachInst is %#x\n", tid, ext_inst);
1158
1159                DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n",
1160                        tid, instruction->staticInst->disassemble(fetch_PC));
1161
1162#if TRACING_ON
1163                instruction->traceData =
1164                    cpu->getTracer()->getInstRecord(curTick, cpu->tcBase(tid),
1165                            instruction->staticInst, instruction->readPC(),
1166                            macroop, instruction->readMicroPC());
1167#else
1168                instruction->traceData = NULL;
1169#endif
1170
1171                ///FIXME This needs to be more robust in dealing with delay slots
1172                predicted_branch |=
1173                    lookupAndUpdateNextPC(instruction, next_PC, next_NPC, next_MicroPC);
1174
1175                // Add instruction to the CPU's list of instructions.
1176                instruction->setInstListIt(cpu->addInst(instruction));
1177
1178                // Write the instruction to the first slot in the queue
1179                // that heads to decode.
1180                toDecode->insts[numInst] = instruction;
1181
1182                toDecode->size++;
1183
1184                // Increment stat of fetched instructions.
1185                ++fetchedInsts;
1186
1187                // Move to the next instruction, unless we have a branch.
1188                fetch_PC = next_PC;
1189                fetch_NPC = next_NPC;
1190                fetch_MicroPC = next_MicroPC;
1191
1192                if (instruction->isQuiesce()) {
1193                    DPRINTF(Fetch, "Quiesce instruction encountered, halting fetch!",
1194                            curTick);
1195                    fetchStatus[tid] = QuiescePending;
1196                    ++numInst;
1197                    status_change = true;
1198                    break;
1199                }
1200
1201                ++numInst;
1202            } while (staticInst->isMicroop() &&
1203                     !staticInst->isLastMicroop() &&
1204                     numInst < fetchWidth);
1205            offset += instSize;
1206        }
1207
1208        if (predicted_branch) {
1209            DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch "
1210                    "instruction encountered.\n", tid);
1211        } else if (numInst >= fetchWidth) {
1212            DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth "
1213                    "for this cycle.\n", tid);
1214        } else if (offset >= cacheBlkSize) {
1215            DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache "
1216                    "block.\n", tid);
1217        }
1218    }
1219
1220    if (numInst > 0) {
1221        wroteToTimeBuffer = true;
1222    }
1223
1224    // Now that fetching is completed, update the PC to signify what the next
1225    // cycle will be.
1226    if (fault == NoFault) {
1227        PC[tid] = next_PC;
1228        nextPC[tid] = next_NPC;
1229        microPC[tid] = next_MicroPC;
1230        DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, next_PC);
1231    } else {
1232        // We shouldn't be in an icache miss and also have a fault (an ITB
1233        // miss)
1234        if (fetchStatus[tid] == IcacheWaitResponse) {
1235            panic("Fetch should have exited prior to this!");
1236        }
1237
1238        // Send the fault to commit.  This thread will not do anything
1239        // until commit handles the fault.  The only other way it can
1240        // wake up is if a squash comes along and changes the PC.
1241        assert(numInst < fetchWidth);
1242        // Get a sequence number.
1243        inst_seq = cpu->getAndIncrementInstSeq();
1244        // We will use a nop in order to carry the fault.
1245        ext_inst = TheISA::NoopMachInst;
1246
1247        // Create a new DynInst from the dummy nop.
1248        DynInstPtr instruction = new DynInst(ext_inst,
1249                                             fetch_PC, fetch_NPC, fetch_MicroPC,
1250                                             next_PC, next_NPC, next_MicroPC,
1251                                             inst_seq, cpu);
1252        instruction->setPredTarg(next_NPC, next_NPC + instSize, 0);
1253        instruction->setTid(tid);
1254
1255        instruction->setASID(tid);
1256
1257        instruction->setThreadState(cpu->thread[tid]);
1258
1259        instruction->traceData = NULL;
1260
1261        instruction->setInstListIt(cpu->addInst(instruction));
1262
1263        instruction->fault = fault;
1264
1265        toDecode->insts[numInst] = instruction;
1266        toDecode->size++;
1267
1268        wroteToTimeBuffer = true;
1269
1270        DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid);
1271
1272        fetchStatus[tid] = TrapPending;
1273        status_change = true;
1274
1275        DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %08p",
1276                tid, fault->name(), PC[tid]);
1277    }
1278}
1279
1280template<class Impl>
1281void
1282DefaultFetch<Impl>::recvRetry()
1283{
1284    if (retryPkt != NULL) {
1285        assert(cacheBlocked);
1286        assert(retryTid != InvalidThreadID);
1287        assert(fetchStatus[retryTid] == IcacheWaitRetry);
1288
1289        if (icachePort->sendTiming(retryPkt)) {
1290            fetchStatus[retryTid] = IcacheWaitResponse;
1291            retryPkt = NULL;
1292            retryTid = InvalidThreadID;
1293            cacheBlocked = false;
1294        }
1295    } else {
1296        assert(retryTid == InvalidThreadID);
1297        // Access has been squashed since it was sent out.  Just clear
1298        // the cache being blocked.
1299        cacheBlocked = false;
1300    }
1301}
1302
1303///////////////////////////////////////
1304//                                   //
1305//  SMT FETCH POLICY MAINTAINED HERE //
1306//                                   //
1307///////////////////////////////////////
1308template<class Impl>
1309ThreadID
1310DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority)
1311{
1312    if (numThreads > 1) {
1313        switch (fetch_priority) {
1314
1315          case SingleThread:
1316            return 0;
1317
1318          case RoundRobin:
1319            return roundRobin();
1320
1321          case IQ:
1322            return iqCount();
1323
1324          case LSQ:
1325            return lsqCount();
1326
1327          case Branch:
1328            return branchCount();
1329
1330          default:
1331            return InvalidThreadID;
1332        }
1333    } else {
1334        list<ThreadID>::iterator thread = activeThreads->begin();
1335        if (thread == activeThreads->end()) {
1336            return InvalidThreadID;
1337        }
1338
1339        ThreadID tid = *thread;
1340
1341        if (fetchStatus[tid] == Running ||
1342            fetchStatus[tid] == IcacheAccessComplete ||
1343            fetchStatus[tid] == Idle) {
1344            return tid;
1345        } else {
1346            return InvalidThreadID;
1347        }
1348    }
1349}
1350
1351
1352template<class Impl>
1353ThreadID
1354DefaultFetch<Impl>::roundRobin()
1355{
1356    list<ThreadID>::iterator pri_iter = priorityList.begin();
1357    list<ThreadID>::iterator end      = priorityList.end();
1358
1359    ThreadID high_pri;
1360
1361    while (pri_iter != end) {
1362        high_pri = *pri_iter;
1363
1364        assert(high_pri <= numThreads);
1365
1366        if (fetchStatus[high_pri] == Running ||
1367            fetchStatus[high_pri] == IcacheAccessComplete ||
1368            fetchStatus[high_pri] == Idle) {
1369
1370            priorityList.erase(pri_iter);
1371            priorityList.push_back(high_pri);
1372
1373            return high_pri;
1374        }
1375
1376        pri_iter++;
1377    }
1378
1379    return InvalidThreadID;
1380}
1381
1382template<class Impl>
1383ThreadID
1384DefaultFetch<Impl>::iqCount()
1385{
1386    std::priority_queue<ThreadID> PQ;
1387
1388    list<ThreadID>::iterator threads = activeThreads->begin();
1389    list<ThreadID>::iterator end = activeThreads->end();
1390
1391    while (threads != end) {
1392        ThreadID tid = *threads++;
1393
1394        PQ.push(fromIEW->iewInfo[tid].iqCount);
1395    }
1396
1397    while (!PQ.empty()) {
1398        ThreadID high_pri = PQ.top();
1399
1400        if (fetchStatus[high_pri] == Running ||
1401            fetchStatus[high_pri] == IcacheAccessComplete ||
1402            fetchStatus[high_pri] == Idle)
1403            return high_pri;
1404        else
1405            PQ.pop();
1406
1407    }
1408
1409    return InvalidThreadID;
1410}
1411
1412template<class Impl>
1413ThreadID
1414DefaultFetch<Impl>::lsqCount()
1415{
1416    std::priority_queue<ThreadID> PQ;
1417
1418    list<ThreadID>::iterator threads = activeThreads->begin();
1419    list<ThreadID>::iterator end = activeThreads->end();
1420
1421    while (threads != end) {
1422        ThreadID tid = *threads++;
1423
1424        PQ.push(fromIEW->iewInfo[tid].ldstqCount);
1425    }
1426
1427    while (!PQ.empty()) {
1428        ThreadID high_pri = PQ.top();
1429
1430        if (fetchStatus[high_pri] == Running ||
1431            fetchStatus[high_pri] == IcacheAccessComplete ||
1432            fetchStatus[high_pri] == Idle)
1433            return high_pri;
1434        else
1435            PQ.pop();
1436    }
1437
1438    return InvalidThreadID;
1439}
1440
1441template<class Impl>
1442ThreadID
1443DefaultFetch<Impl>::branchCount()
1444{
1445#if 0
1446    list<ThreadID>::iterator thread = activeThreads->begin();
1447    assert(thread != activeThreads->end());
1448    ThreadID tid = *thread;
1449#endif
1450
1451    panic("Branch Count Fetch policy unimplemented\n");
1452    return InvalidThreadID;
1453}
1454