fetch_impl.hh revision 5982:de47df436ace
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#include <algorithm> 33#include <cstring> 34 35#include "config/use_checker.hh" 36 37#include "arch/isa_traits.hh" 38#include "arch/utility.hh" 39#include "cpu/checker/cpu.hh" 40#include "cpu/exetrace.hh" 41#include "cpu/o3/fetch.hh" 42#include "mem/packet.hh" 43#include "mem/request.hh" 44#include "sim/byteswap.hh" 45#include "sim/host.hh" 46#include "sim/core.hh" 47 48#if FULL_SYSTEM 49#include "arch/tlb.hh" 50#include "arch/vtophys.hh" 51#include "sim/system.hh" 52#endif // FULL_SYSTEM 53 54#include "params/DerivO3CPU.hh" 55 56template<class Impl> 57void 58DefaultFetch<Impl>::IcachePort::setPeer(Port *port) 59{ 60 Port::setPeer(port); 61 62 fetch->setIcache(); 63} 64 65template<class Impl> 66Tick 67DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt) 68{ 69 panic("DefaultFetch doesn't expect recvAtomic callback!"); 70 return curTick; 71} 72 73template<class Impl> 74void 75DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt) 76{ 77 DPRINTF(Fetch, "DefaultFetch doesn't update its state from a " 78 "functional call."); 79} 80 81template<class Impl> 82void 83DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status) 84{ 85 if (status == RangeChange) { 86 if (!snoopRangeSent) { 87 snoopRangeSent = true; 88 sendStatusChange(Port::RangeChange); 89 } 90 return; 91 } 92 93 panic("DefaultFetch doesn't expect recvStatusChange callback!"); 94} 95 96template<class Impl> 97bool 98DefaultFetch<Impl>::IcachePort::recvTiming(PacketPtr pkt) 99{ 100 DPRINTF(Fetch, "Received timing\n"); 101 if (pkt->isResponse()) { 102 fetch->processCacheCompletion(pkt); 103 } 104 //else Snooped a coherence request, just return 105 return true; 106} 107 108template<class Impl> 109void 110DefaultFetch<Impl>::IcachePort::recvRetry() 111{ 112 fetch->recvRetry(); 113} 114 115template<class Impl> 116DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params) 117 : cpu(_cpu), 118 branchPred(params), 119 predecoder(NULL), 120 decodeToFetchDelay(params->decodeToFetchDelay), 121 renameToFetchDelay(params->renameToFetchDelay), 122 iewToFetchDelay(params->iewToFetchDelay), 123 commitToFetchDelay(params->commitToFetchDelay), 124 fetchWidth(params->fetchWidth), 125 cacheBlocked(false), 126 retryPkt(NULL), 127 retryTid(-1), 128 numThreads(params->numThreads), 129 numFetchingThreads(params->smtNumFetchingThreads), 130 interruptPending(false), 131 drainPending(false), 132 switchedOut(false) 133{ 134 if (numThreads > Impl::MaxThreads) 135 fatal("numThreads (%d) is larger than compiled limit (%d),\n" 136 "\tincrease MaxThreads in src/cpu/o3/impl.hh\n", 137 numThreads, static_cast<int>(Impl::MaxThreads)); 138 139 // Set fetch stage's status to inactive. 140 _status = Inactive; 141 142 std::string policy = params->smtFetchPolicy; 143 144 // Convert string to lowercase 145 std::transform(policy.begin(), policy.end(), policy.begin(), 146 (int(*)(int)) tolower); 147 148 // Figure out fetch policy 149 if (policy == "singlethread") { 150 fetchPolicy = SingleThread; 151 if (numThreads > 1) 152 panic("Invalid Fetch Policy for a SMT workload."); 153 } else if (policy == "roundrobin") { 154 fetchPolicy = RoundRobin; 155 DPRINTF(Fetch, "Fetch policy set to Round Robin\n"); 156 } else if (policy == "branch") { 157 fetchPolicy = Branch; 158 DPRINTF(Fetch, "Fetch policy set to Branch Count\n"); 159 } else if (policy == "iqcount") { 160 fetchPolicy = IQ; 161 DPRINTF(Fetch, "Fetch policy set to IQ count\n"); 162 } else if (policy == "lsqcount") { 163 fetchPolicy = LSQ; 164 DPRINTF(Fetch, "Fetch policy set to LSQ count\n"); 165 } else { 166 fatal("Invalid Fetch Policy. Options Are: {SingleThread," 167 " RoundRobin,LSQcount,IQcount}\n"); 168 } 169 170 // Get the size of an instruction. 171 instSize = sizeof(TheISA::MachInst); 172 173 // Name is finally available, so create the port. 174 icachePort = new IcachePort(this); 175 176 icachePort->snoopRangeSent = false; 177 178#if USE_CHECKER 179 if (cpu->checker) { 180 cpu->checker->setIcachePort(icachePort); 181 } 182#endif 183} 184 185template <class Impl> 186std::string 187DefaultFetch<Impl>::name() const 188{ 189 return cpu->name() + ".fetch"; 190} 191 192template <class Impl> 193void 194DefaultFetch<Impl>::regStats() 195{ 196 icacheStallCycles 197 .name(name() + ".icacheStallCycles") 198 .desc("Number of cycles fetch is stalled on an Icache miss") 199 .prereq(icacheStallCycles); 200 201 fetchedInsts 202 .name(name() + ".Insts") 203 .desc("Number of instructions fetch has processed") 204 .prereq(fetchedInsts); 205 206 fetchedBranches 207 .name(name() + ".Branches") 208 .desc("Number of branches that fetch encountered") 209 .prereq(fetchedBranches); 210 211 predictedBranches 212 .name(name() + ".predictedBranches") 213 .desc("Number of branches that fetch has predicted taken") 214 .prereq(predictedBranches); 215 216 fetchCycles 217 .name(name() + ".Cycles") 218 .desc("Number of cycles fetch has run and was not squashing or" 219 " blocked") 220 .prereq(fetchCycles); 221 222 fetchSquashCycles 223 .name(name() + ".SquashCycles") 224 .desc("Number of cycles fetch has spent squashing") 225 .prereq(fetchSquashCycles); 226 227 fetchIdleCycles 228 .name(name() + ".IdleCycles") 229 .desc("Number of cycles fetch was idle") 230 .prereq(fetchIdleCycles); 231 232 fetchBlockedCycles 233 .name(name() + ".BlockedCycles") 234 .desc("Number of cycles fetch has spent blocked") 235 .prereq(fetchBlockedCycles); 236 237 fetchedCacheLines 238 .name(name() + ".CacheLines") 239 .desc("Number of cache lines fetched") 240 .prereq(fetchedCacheLines); 241 242 fetchMiscStallCycles 243 .name(name() + ".MiscStallCycles") 244 .desc("Number of cycles fetch has spent waiting on interrupts, or " 245 "bad addresses, or out of MSHRs") 246 .prereq(fetchMiscStallCycles); 247 248 fetchIcacheSquashes 249 .name(name() + ".IcacheSquashes") 250 .desc("Number of outstanding Icache misses that were squashed") 251 .prereq(fetchIcacheSquashes); 252 253 fetchNisnDist 254 .init(/* base value */ 0, 255 /* last value */ fetchWidth, 256 /* bucket size */ 1) 257 .name(name() + ".rateDist") 258 .desc("Number of instructions fetched each cycle (Total)") 259 .flags(Stats::pdf); 260 261 idleRate 262 .name(name() + ".idleRate") 263 .desc("Percent of cycles fetch was idle") 264 .prereq(idleRate); 265 idleRate = fetchIdleCycles * 100 / cpu->numCycles; 266 267 branchRate 268 .name(name() + ".branchRate") 269 .desc("Number of branch fetches per cycle") 270 .flags(Stats::total); 271 branchRate = fetchedBranches / cpu->numCycles; 272 273 fetchRate 274 .name(name() + ".rate") 275 .desc("Number of inst fetches per cycle") 276 .flags(Stats::total); 277 fetchRate = fetchedInsts / cpu->numCycles; 278 279 branchPred.regStats(); 280} 281 282template<class Impl> 283void 284DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer) 285{ 286 timeBuffer = time_buffer; 287 288 // Create wires to get information from proper places in time buffer. 289 fromDecode = timeBuffer->getWire(-decodeToFetchDelay); 290 fromRename = timeBuffer->getWire(-renameToFetchDelay); 291 fromIEW = timeBuffer->getWire(-iewToFetchDelay); 292 fromCommit = timeBuffer->getWire(-commitToFetchDelay); 293} 294 295template<class Impl> 296void 297DefaultFetch<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) 298{ 299 activeThreads = at_ptr; 300} 301 302template<class Impl> 303void 304DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 305{ 306 fetchQueue = fq_ptr; 307 308 // Create wire to write information to proper place in fetch queue. 309 toDecode = fetchQueue->getWire(0); 310} 311 312template<class Impl> 313void 314DefaultFetch<Impl>::initStage() 315{ 316 // Setup PC and nextPC with initial state. 317 for (int tid = 0; tid < numThreads; tid++) { 318 PC[tid] = cpu->readPC(tid); 319 nextPC[tid] = cpu->readNextPC(tid); 320 microPC[tid] = cpu->readMicroPC(tid); 321 } 322 323 for (int tid=0; tid < numThreads; tid++) { 324 325 fetchStatus[tid] = Running; 326 327 priorityList.push_back(tid); 328 329 memReq[tid] = NULL; 330 331 stalls[tid].decode = false; 332 stalls[tid].rename = false; 333 stalls[tid].iew = false; 334 stalls[tid].commit = false; 335 } 336 337 // Schedule fetch to get the correct PC from the CPU 338 // scheduleFetchStartupEvent(1); 339 340 // Fetch needs to start fetching instructions at the very beginning, 341 // so it must start up in active state. 342 switchToActive(); 343} 344 345template<class Impl> 346void 347DefaultFetch<Impl>::setIcache() 348{ 349 // Size of cache block. 350 cacheBlkSize = icachePort->peerBlockSize(); 351 352 // Create mask to get rid of offset bits. 353 cacheBlkMask = (cacheBlkSize - 1); 354 355 for (int tid=0; tid < numThreads; tid++) { 356 // Create space to store a cache line. 357 cacheData[tid] = new uint8_t[cacheBlkSize]; 358 cacheDataPC[tid] = 0; 359 cacheDataValid[tid] = false; 360 } 361} 362 363template<class Impl> 364void 365DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt) 366{ 367 unsigned tid = pkt->req->threadId(); 368 369 DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid); 370 371 assert(!pkt->wasNacked()); 372 373 // Only change the status if it's still waiting on the icache access 374 // to return. 375 if (fetchStatus[tid] != IcacheWaitResponse || 376 pkt->req != memReq[tid] || 377 isSwitchedOut()) { 378 ++fetchIcacheSquashes; 379 delete pkt->req; 380 delete pkt; 381 return; 382 } 383 384 memcpy(cacheData[tid], pkt->getPtr<uint8_t>(), cacheBlkSize); 385 cacheDataValid[tid] = true; 386 387 if (!drainPending) { 388 // Wake up the CPU (if it went to sleep and was waiting on 389 // this completion event). 390 cpu->wakeCPU(); 391 392 DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n", 393 tid); 394 395 switchToActive(); 396 } 397 398 // Only switch to IcacheAccessComplete if we're not stalled as well. 399 if (checkStall(tid)) { 400 fetchStatus[tid] = Blocked; 401 } else { 402 fetchStatus[tid] = IcacheAccessComplete; 403 } 404 405 // Reset the mem req to NULL. 406 delete pkt->req; 407 delete pkt; 408 memReq[tid] = NULL; 409} 410 411template <class Impl> 412bool 413DefaultFetch<Impl>::drain() 414{ 415 // Fetch is ready to drain at any time. 416 cpu->signalDrained(); 417 drainPending = true; 418 return true; 419} 420 421template <class Impl> 422void 423DefaultFetch<Impl>::resume() 424{ 425 drainPending = false; 426} 427 428template <class Impl> 429void 430DefaultFetch<Impl>::switchOut() 431{ 432 switchedOut = true; 433 // Branch predictor needs to have its state cleared. 434 branchPred.switchOut(); 435} 436 437template <class Impl> 438void 439DefaultFetch<Impl>::takeOverFrom() 440{ 441 // Reset all state 442 for (int i = 0; i < Impl::MaxThreads; ++i) { 443 stalls[i].decode = 0; 444 stalls[i].rename = 0; 445 stalls[i].iew = 0; 446 stalls[i].commit = 0; 447 PC[i] = cpu->readPC(i); 448 nextPC[i] = cpu->readNextPC(i); 449 microPC[i] = cpu->readMicroPC(i); 450 fetchStatus[i] = Running; 451 } 452 numInst = 0; 453 wroteToTimeBuffer = false; 454 _status = Inactive; 455 switchedOut = false; 456 interruptPending = false; 457 branchPred.takeOverFrom(); 458} 459 460template <class Impl> 461void 462DefaultFetch<Impl>::wakeFromQuiesce() 463{ 464 DPRINTF(Fetch, "Waking up from quiesce\n"); 465 // Hopefully this is safe 466 // @todo: Allow other threads to wake from quiesce. 467 fetchStatus[0] = Running; 468} 469 470template <class Impl> 471inline void 472DefaultFetch<Impl>::switchToActive() 473{ 474 if (_status == Inactive) { 475 DPRINTF(Activity, "Activating stage.\n"); 476 477 cpu->activateStage(O3CPU::FetchIdx); 478 479 _status = Active; 480 } 481} 482 483template <class Impl> 484inline void 485DefaultFetch<Impl>::switchToInactive() 486{ 487 if (_status == Active) { 488 DPRINTF(Activity, "Deactivating stage.\n"); 489 490 cpu->deactivateStage(O3CPU::FetchIdx); 491 492 _status = Inactive; 493 } 494} 495 496template <class Impl> 497bool 498DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC, 499 Addr &next_NPC, Addr &next_MicroPC) 500{ 501 // Do branch prediction check here. 502 // A bit of a misnomer...next_PC is actually the current PC until 503 // this function updates it. 504 bool predict_taken; 505 506 if (!inst->isControl()) { 507 if (inst->isMicroop() && !inst->isLastMicroop()) { 508 next_MicroPC++; 509 } else { 510 next_PC = next_NPC; 511 next_NPC = next_NPC + instSize; 512 next_MicroPC = 0; 513 } 514 inst->setPredTarg(next_PC, next_NPC, next_MicroPC); 515 inst->setPredTaken(false); 516 return false; 517 } 518 519 //Assume for now that all control flow is to a different macroop which 520 //would reset the micro pc to 0. 521 next_MicroPC = 0; 522 523 int tid = inst->threadNumber; 524 Addr pred_PC = next_PC; 525 predict_taken = branchPred.predict(inst, pred_PC, tid); 526 527/* if (predict_taken) { 528 DPRINTF(Fetch, "[tid:%i]: Branch predicted to be taken to %#x.\n", 529 tid, pred_PC); 530 } else { 531 DPRINTF(Fetch, "[tid:%i]: Branch predicted to be not taken.\n", tid); 532 }*/ 533 534#if ISA_HAS_DELAY_SLOT 535 next_PC = next_NPC; 536 if (predict_taken) 537 next_NPC = pred_PC; 538 else 539 next_NPC += instSize; 540#else 541 if (predict_taken) 542 next_PC = pred_PC; 543 else 544 next_PC += instSize; 545 next_NPC = next_PC + instSize; 546#endif 547/* DPRINTF(Fetch, "[tid:%i]: Branch predicted to go to %#x and then %#x.\n", 548 tid, next_PC, next_NPC);*/ 549 inst->setPredTarg(next_PC, next_NPC, next_MicroPC); 550 inst->setPredTaken(predict_taken); 551 552 ++fetchedBranches; 553 554 if (predict_taken) { 555 ++predictedBranches; 556 } 557 558 return predict_taken; 559} 560 561template <class Impl> 562bool 563DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid) 564{ 565 Fault fault = NoFault; 566 567 //AlphaDep 568 if (cacheBlocked) { 569 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n", 570 tid); 571 return false; 572 } else if (isSwitchedOut()) { 573 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, switched out\n", 574 tid); 575 return false; 576 } else if (interruptPending && !(fetch_PC & 0x3)) { 577 // Hold off fetch from getting new instructions when: 578 // Cache is blocked, or 579 // while an interrupt is pending and we're not in PAL mode, or 580 // fetch is switched out. 581 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n", 582 tid); 583 return false; 584 } 585 586 // Align the fetch PC so it's at the start of a cache block. 587 Addr block_PC = icacheBlockAlignPC(fetch_PC); 588 589 // If we've already got the block, no need to try to fetch it again. 590 if (cacheDataValid[tid] && block_PC == cacheDataPC[tid]) { 591 return true; 592 } 593 594 // Setup the memReq to do a read of the first instruction's address. 595 // Set the appropriate read size and flags as well. 596 // Build request here. 597 RequestPtr mem_req = new Request(tid, block_PC, cacheBlkSize, 0, 598 fetch_PC, cpu->thread[tid]->contextId(), 599 tid); 600 601 memReq[tid] = mem_req; 602 603 // Translate the instruction request. 604 fault = cpu->itb->translateAtomic(mem_req, cpu->thread[tid]->getTC()); 605 606 // In the case of faults, the fetch stage may need to stall and wait 607 // for the ITB miss to be handled. 608 609 // If translation was successful, attempt to read the first 610 // instruction. 611 if (fault == NoFault) { 612#if 0 613 if (cpu->system->memctrl->badaddr(memReq[tid]->paddr) || 614 memReq[tid]->isUncacheable()) { 615 DPRINTF(Fetch, "Fetch: Bad address %#x (hopefully on a " 616 "misspeculating path)!", 617 memReq[tid]->paddr); 618 ret_fault = TheISA::genMachineCheckFault(); 619 return false; 620 } 621#endif 622 623 // Build packet here. 624 PacketPtr data_pkt = new Packet(mem_req, 625 MemCmd::ReadReq, Packet::Broadcast); 626 data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]); 627 628 cacheDataPC[tid] = block_PC; 629 cacheDataValid[tid] = false; 630 631 DPRINTF(Fetch, "Fetch: Doing instruction read.\n"); 632 633 fetchedCacheLines++; 634 635 // Now do the timing access to see whether or not the instruction 636 // exists within the cache. 637 if (!icachePort->sendTiming(data_pkt)) { 638 assert(retryPkt == NULL); 639 assert(retryTid == -1); 640 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid); 641 fetchStatus[tid] = IcacheWaitRetry; 642 retryPkt = data_pkt; 643 retryTid = tid; 644 cacheBlocked = true; 645 return false; 646 } 647 648 DPRINTF(Fetch, "[tid:%i]: Doing cache access.\n", tid); 649 650 lastIcacheStall[tid] = curTick; 651 652 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache " 653 "response.\n", tid); 654 655 fetchStatus[tid] = IcacheWaitResponse; 656 } else { 657 delete mem_req; 658 memReq[tid] = NULL; 659 } 660 661 ret_fault = fault; 662 return true; 663} 664 665template <class Impl> 666inline void 667DefaultFetch<Impl>::doSquash(const Addr &new_PC, 668 const Addr &new_NPC, const Addr &new_microPC, unsigned tid) 669{ 670 DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x, NPC to: %#x.\n", 671 tid, new_PC, new_NPC); 672 673 PC[tid] = new_PC; 674 nextPC[tid] = new_NPC; 675 microPC[tid] = new_microPC; 676 677 // Clear the icache miss if it's outstanding. 678 if (fetchStatus[tid] == IcacheWaitResponse) { 679 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n", 680 tid); 681 memReq[tid] = NULL; 682 } 683 684 // Get rid of the retrying packet if it was from this thread. 685 if (retryTid == tid) { 686 assert(cacheBlocked); 687 if (retryPkt) { 688 delete retryPkt->req; 689 delete retryPkt; 690 } 691 retryPkt = NULL; 692 retryTid = -1; 693 } 694 695 fetchStatus[tid] = Squashing; 696 697 ++fetchSquashCycles; 698} 699 700template<class Impl> 701void 702DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC, const Addr &new_NPC, 703 const Addr &new_MicroPC, 704 const InstSeqNum &seq_num, unsigned tid) 705{ 706 DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid); 707 708 doSquash(new_PC, new_NPC, new_MicroPC, tid); 709 710 // Tell the CPU to remove any instructions that are in flight between 711 // fetch and decode. 712 cpu->removeInstsUntil(seq_num, tid); 713} 714 715template<class Impl> 716bool 717DefaultFetch<Impl>::checkStall(unsigned tid) const 718{ 719 bool ret_val = false; 720 721 if (cpu->contextSwitch) { 722 DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid); 723 ret_val = true; 724 } else if (stalls[tid].decode) { 725 DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid); 726 ret_val = true; 727 } else if (stalls[tid].rename) { 728 DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid); 729 ret_val = true; 730 } else if (stalls[tid].iew) { 731 DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid); 732 ret_val = true; 733 } else if (stalls[tid].commit) { 734 DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid); 735 ret_val = true; 736 } 737 738 return ret_val; 739} 740 741template<class Impl> 742typename DefaultFetch<Impl>::FetchStatus 743DefaultFetch<Impl>::updateFetchStatus() 744{ 745 //Check Running 746 std::list<unsigned>::iterator threads = activeThreads->begin(); 747 std::list<unsigned>::iterator end = activeThreads->end(); 748 749 while (threads != end) { 750 unsigned tid = *threads++; 751 752 if (fetchStatus[tid] == Running || 753 fetchStatus[tid] == Squashing || 754 fetchStatus[tid] == IcacheAccessComplete) { 755 756 if (_status == Inactive) { 757 DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid); 758 759 if (fetchStatus[tid] == IcacheAccessComplete) { 760 DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache" 761 "completion\n",tid); 762 } 763 764 cpu->activateStage(O3CPU::FetchIdx); 765 } 766 767 return Active; 768 } 769 } 770 771 // Stage is switching from active to inactive, notify CPU of it. 772 if (_status == Active) { 773 DPRINTF(Activity, "Deactivating stage.\n"); 774 775 cpu->deactivateStage(O3CPU::FetchIdx); 776 } 777 778 return Inactive; 779} 780 781template <class Impl> 782void 783DefaultFetch<Impl>::squash(const Addr &new_PC, const Addr &new_NPC, 784 const Addr &new_MicroPC, 785 const InstSeqNum &seq_num, unsigned tid) 786{ 787 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid); 788 789 doSquash(new_PC, new_NPC, new_MicroPC, tid); 790 791 // Tell the CPU to remove any instructions that are not in the ROB. 792 cpu->removeInstsNotInROB(tid); 793} 794 795template <class Impl> 796void 797DefaultFetch<Impl>::tick() 798{ 799 std::list<unsigned>::iterator threads = activeThreads->begin(); 800 std::list<unsigned>::iterator end = activeThreads->end(); 801 bool status_change = false; 802 803 wroteToTimeBuffer = false; 804 805 while (threads != end) { 806 unsigned tid = *threads++; 807 808 // Check the signals for each thread to determine the proper status 809 // for each thread. 810 bool updated_status = checkSignalsAndUpdate(tid); 811 status_change = status_change || updated_status; 812 } 813 814 DPRINTF(Fetch, "Running stage.\n"); 815 816 // Reset the number of the instruction we're fetching. 817 numInst = 0; 818 819#if FULL_SYSTEM 820 if (fromCommit->commitInfo[0].interruptPending) { 821 interruptPending = true; 822 } 823 824 if (fromCommit->commitInfo[0].clearInterrupt) { 825 interruptPending = false; 826 } 827#endif 828 829 for (threadFetched = 0; threadFetched < numFetchingThreads; 830 threadFetched++) { 831 // Fetch each of the actively fetching threads. 832 fetch(status_change); 833 } 834 835 // Record number of instructions fetched this cycle for distribution. 836 fetchNisnDist.sample(numInst); 837 838 if (status_change) { 839 // Change the fetch stage status if there was a status change. 840 _status = updateFetchStatus(); 841 } 842 843 // If there was activity this cycle, inform the CPU of it. 844 if (wroteToTimeBuffer || cpu->contextSwitch) { 845 DPRINTF(Activity, "Activity this cycle.\n"); 846 847 cpu->activityThisCycle(); 848 } 849} 850 851template <class Impl> 852bool 853DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid) 854{ 855 // Update the per thread stall statuses. 856 if (fromDecode->decodeBlock[tid]) { 857 stalls[tid].decode = true; 858 } 859 860 if (fromDecode->decodeUnblock[tid]) { 861 assert(stalls[tid].decode); 862 assert(!fromDecode->decodeBlock[tid]); 863 stalls[tid].decode = false; 864 } 865 866 if (fromRename->renameBlock[tid]) { 867 stalls[tid].rename = true; 868 } 869 870 if (fromRename->renameUnblock[tid]) { 871 assert(stalls[tid].rename); 872 assert(!fromRename->renameBlock[tid]); 873 stalls[tid].rename = false; 874 } 875 876 if (fromIEW->iewBlock[tid]) { 877 stalls[tid].iew = true; 878 } 879 880 if (fromIEW->iewUnblock[tid]) { 881 assert(stalls[tid].iew); 882 assert(!fromIEW->iewBlock[tid]); 883 stalls[tid].iew = false; 884 } 885 886 if (fromCommit->commitBlock[tid]) { 887 stalls[tid].commit = true; 888 } 889 890 if (fromCommit->commitUnblock[tid]) { 891 assert(stalls[tid].commit); 892 assert(!fromCommit->commitBlock[tid]); 893 stalls[tid].commit = false; 894 } 895 896 // Check squash signals from commit. 897 if (fromCommit->commitInfo[tid].squash) { 898 899 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash " 900 "from commit.\n",tid); 901 // In any case, squash. 902 squash(fromCommit->commitInfo[tid].nextPC, 903 fromCommit->commitInfo[tid].nextNPC, 904 fromCommit->commitInfo[tid].nextMicroPC, 905 fromCommit->commitInfo[tid].doneSeqNum, 906 tid); 907 908 // Also check if there's a mispredict that happened. 909 if (fromCommit->commitInfo[tid].branchMispredict) { 910 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum, 911 fromCommit->commitInfo[tid].nextPC, 912 fromCommit->commitInfo[tid].branchTaken, 913 tid); 914 } else { 915 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum, 916 tid); 917 } 918 919 return true; 920 } else if (fromCommit->commitInfo[tid].doneSeqNum) { 921 // Update the branch predictor if it wasn't a squashed instruction 922 // that was broadcasted. 923 branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid); 924 } 925 926 // Check ROB squash signals from commit. 927 if (fromCommit->commitInfo[tid].robSquashing) { 928 DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid); 929 930 // Continue to squash. 931 fetchStatus[tid] = Squashing; 932 933 return true; 934 } 935 936 // Check squash signals from decode. 937 if (fromDecode->decodeInfo[tid].squash) { 938 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash " 939 "from decode.\n",tid); 940 941 // Update the branch predictor. 942 if (fromDecode->decodeInfo[tid].branchMispredict) { 943 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum, 944 fromDecode->decodeInfo[tid].nextPC, 945 fromDecode->decodeInfo[tid].branchTaken, 946 tid); 947 } else { 948 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum, 949 tid); 950 } 951 952 if (fetchStatus[tid] != Squashing) { 953 954 DPRINTF(Fetch, "Squashing from decode with PC = %#x, NPC = %#x\n", 955 fromDecode->decodeInfo[tid].nextPC, 956 fromDecode->decodeInfo[tid].nextNPC); 957 // Squash unless we're already squashing 958 squashFromDecode(fromDecode->decodeInfo[tid].nextPC, 959 fromDecode->decodeInfo[tid].nextNPC, 960 fromDecode->decodeInfo[tid].nextMicroPC, 961 fromDecode->decodeInfo[tid].doneSeqNum, 962 tid); 963 964 return true; 965 } 966 } 967 968 if (checkStall(tid) && 969 fetchStatus[tid] != IcacheWaitResponse && 970 fetchStatus[tid] != IcacheWaitRetry) { 971 DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid); 972 973 fetchStatus[tid] = Blocked; 974 975 return true; 976 } 977 978 if (fetchStatus[tid] == Blocked || 979 fetchStatus[tid] == Squashing) { 980 // Switch status to running if fetch isn't being told to block or 981 // squash this cycle. 982 DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n", 983 tid); 984 985 fetchStatus[tid] = Running; 986 987 return true; 988 } 989 990 // If we've reached this point, we have not gotten any signals that 991 // cause fetch to change its status. Fetch remains the same as before. 992 return false; 993} 994 995template<class Impl> 996void 997DefaultFetch<Impl>::fetch(bool &status_change) 998{ 999 ////////////////////////////////////////// 1000 // Start actual fetch 1001 ////////////////////////////////////////// 1002 int tid = getFetchingThread(fetchPolicy); 1003 1004 if (tid == -1 || drainPending) { 1005 DPRINTF(Fetch,"There are no more threads available to fetch from.\n"); 1006 1007 // Breaks looping condition in tick() 1008 threadFetched = numFetchingThreads; 1009 return; 1010 } 1011 1012 DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid); 1013 1014 // The current PC. 1015 Addr fetch_PC = PC[tid]; 1016 Addr fetch_NPC = nextPC[tid]; 1017 Addr fetch_MicroPC = microPC[tid]; 1018 1019 // Fault code for memory access. 1020 Fault fault = NoFault; 1021 1022 // If returning from the delay of a cache miss, then update the status 1023 // to running, otherwise do the cache access. Possibly move this up 1024 // to tick() function. 1025 if (fetchStatus[tid] == IcacheAccessComplete) { 1026 DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n", 1027 tid); 1028 1029 fetchStatus[tid] = Running; 1030 status_change = true; 1031 } else if (fetchStatus[tid] == Running) { 1032 DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read " 1033 "instruction, starting at PC %08p.\n", 1034 tid, fetch_PC); 1035 1036 bool fetch_success = fetchCacheLine(fetch_PC, fault, tid); 1037 if (!fetch_success) { 1038 if (cacheBlocked) { 1039 ++icacheStallCycles; 1040 } else { 1041 ++fetchMiscStallCycles; 1042 } 1043 return; 1044 } 1045 } else { 1046 if (fetchStatus[tid] == Idle) { 1047 ++fetchIdleCycles; 1048 DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid); 1049 } else if (fetchStatus[tid] == Blocked) { 1050 ++fetchBlockedCycles; 1051 DPRINTF(Fetch, "[tid:%i]: Fetch is blocked!\n", tid); 1052 } else if (fetchStatus[tid] == Squashing) { 1053 ++fetchSquashCycles; 1054 DPRINTF(Fetch, "[tid:%i]: Fetch is squashing!\n", tid); 1055 } else if (fetchStatus[tid] == IcacheWaitResponse) { 1056 ++icacheStallCycles; 1057 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n", tid); 1058 } 1059 1060 // Status is Idle, Squashing, Blocked, or IcacheWaitResponse, so 1061 // fetch should do nothing. 1062 return; 1063 } 1064 1065 ++fetchCycles; 1066 1067 // If we had a stall due to an icache miss, then return. 1068 if (fetchStatus[tid] == IcacheWaitResponse) { 1069 ++icacheStallCycles; 1070 status_change = true; 1071 return; 1072 } 1073 1074 Addr next_PC = fetch_PC; 1075 Addr next_NPC = fetch_NPC; 1076 Addr next_MicroPC = fetch_MicroPC; 1077 1078 InstSeqNum inst_seq; 1079 MachInst inst; 1080 ExtMachInst ext_inst; 1081 // @todo: Fix this hack. 1082 unsigned offset = (fetch_PC & cacheBlkMask) & ~3; 1083 1084 StaticInstPtr staticInst = NULL; 1085 StaticInstPtr macroop = NULL; 1086 1087 if (fault == NoFault) { 1088 // If the read of the first instruction was successful, then grab the 1089 // instructions from the rest of the cache line and put them into the 1090 // queue heading to decode. 1091 1092 DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to " 1093 "decode.\n",tid); 1094 1095 // Need to keep track of whether or not a predicted branch 1096 // ended this fetch block. 1097 bool predicted_branch = false; 1098 1099 while (offset < cacheBlkSize && 1100 numInst < fetchWidth && 1101 !predicted_branch) { 1102 1103 // If we're branching after this instruction, quite fetching 1104 // from the same block then. 1105 predicted_branch = 1106 (fetch_PC + sizeof(TheISA::MachInst) != fetch_NPC); 1107 if (predicted_branch) { 1108 DPRINTF(Fetch, "Branch detected with PC = %#x, NPC = %#x\n", 1109 fetch_PC, fetch_NPC); 1110 } 1111 1112 // Make sure this is a valid index. 1113 assert(offset <= cacheBlkSize - instSize); 1114 1115 if (!macroop) { 1116 // Get the instruction from the array of the cache line. 1117 inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *> 1118 (&cacheData[tid][offset])); 1119 1120 predecoder.setTC(cpu->thread[tid]->getTC()); 1121 predecoder.moreBytes(fetch_PC, fetch_PC, inst); 1122 1123 ext_inst = predecoder.getExtMachInst(); 1124 staticInst = StaticInstPtr(ext_inst, fetch_PC); 1125 if (staticInst->isMacroop()) 1126 macroop = staticInst; 1127 } 1128 do { 1129 if (macroop) { 1130 staticInst = macroop->fetchMicroop(fetch_MicroPC); 1131 if (staticInst->isLastMicroop()) 1132 macroop = NULL; 1133 } 1134 1135 // Get a sequence number. 1136 inst_seq = cpu->getAndIncrementInstSeq(); 1137 1138 // Create a new DynInst from the instruction fetched. 1139 DynInstPtr instruction = new DynInst(staticInst, 1140 fetch_PC, fetch_NPC, fetch_MicroPC, 1141 next_PC, next_NPC, next_MicroPC, 1142 inst_seq, cpu); 1143 instruction->setTid(tid); 1144 1145 instruction->setASID(tid); 1146 1147 instruction->setThreadState(cpu->thread[tid]); 1148 1149 DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created " 1150 "[sn:%lli]\n", 1151 tid, instruction->readPC(), inst_seq); 1152 1153 //DPRINTF(Fetch, "[tid:%i]: MachInst is %#x\n", tid, ext_inst); 1154 1155 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", 1156 tid, instruction->staticInst->disassemble(fetch_PC)); 1157 1158#if TRACING_ON 1159 instruction->traceData = 1160 cpu->getTracer()->getInstRecord(curTick, cpu->tcBase(tid), 1161 instruction->staticInst, instruction->readPC()); 1162#else 1163 instruction->traceData = NULL; 1164#endif 1165 1166 ///FIXME This needs to be more robust in dealing with delay slots 1167 predicted_branch |= 1168 lookupAndUpdateNextPC(instruction, next_PC, next_NPC, next_MicroPC); 1169 1170 // Add instruction to the CPU's list of instructions. 1171 instruction->setInstListIt(cpu->addInst(instruction)); 1172 1173 // Write the instruction to the first slot in the queue 1174 // that heads to decode. 1175 toDecode->insts[numInst] = instruction; 1176 1177 toDecode->size++; 1178 1179 // Increment stat of fetched instructions. 1180 ++fetchedInsts; 1181 1182 // Move to the next instruction, unless we have a branch. 1183 fetch_PC = next_PC; 1184 fetch_NPC = next_NPC; 1185 fetch_MicroPC = next_MicroPC; 1186 1187 if (instruction->isQuiesce()) { 1188 DPRINTF(Fetch, "Quiesce instruction encountered, halting fetch!", 1189 curTick); 1190 fetchStatus[tid] = QuiescePending; 1191 ++numInst; 1192 status_change = true; 1193 break; 1194 } 1195 1196 ++numInst; 1197 } while (staticInst->isMicroop() && 1198 !staticInst->isLastMicroop() && 1199 numInst < fetchWidth); 1200 offset += instSize; 1201 } 1202 1203 if (predicted_branch) { 1204 DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch " 1205 "instruction encountered.\n", tid); 1206 } else if (numInst >= fetchWidth) { 1207 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth " 1208 "for this cycle.\n", tid); 1209 } else if (offset >= cacheBlkSize) { 1210 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache " 1211 "block.\n", tid); 1212 } 1213 } 1214 1215 if (numInst > 0) { 1216 wroteToTimeBuffer = true; 1217 } 1218 1219 // Now that fetching is completed, update the PC to signify what the next 1220 // cycle will be. 1221 if (fault == NoFault) { 1222 PC[tid] = next_PC; 1223 nextPC[tid] = next_NPC; 1224 microPC[tid] = next_MicroPC; 1225 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, next_PC); 1226 } else { 1227 // We shouldn't be in an icache miss and also have a fault (an ITB 1228 // miss) 1229 if (fetchStatus[tid] == IcacheWaitResponse) { 1230 panic("Fetch should have exited prior to this!"); 1231 } 1232 1233 // Send the fault to commit. This thread will not do anything 1234 // until commit handles the fault. The only other way it can 1235 // wake up is if a squash comes along and changes the PC. 1236 assert(numInst < fetchWidth); 1237 // Get a sequence number. 1238 inst_seq = cpu->getAndIncrementInstSeq(); 1239 // We will use a nop in order to carry the fault. 1240 ext_inst = TheISA::NoopMachInst; 1241 1242 // Create a new DynInst from the dummy nop. 1243 DynInstPtr instruction = new DynInst(ext_inst, 1244 fetch_PC, fetch_NPC, fetch_MicroPC, 1245 next_PC, next_NPC, next_MicroPC, 1246 inst_seq, cpu); 1247 instruction->setPredTarg(next_NPC, next_NPC + instSize, 0); 1248 instruction->setTid(tid); 1249 1250 instruction->setASID(tid); 1251 1252 instruction->setThreadState(cpu->thread[tid]); 1253 1254 instruction->traceData = NULL; 1255 1256 instruction->setInstListIt(cpu->addInst(instruction)); 1257 1258 instruction->fault = fault; 1259 1260 toDecode->insts[numInst] = instruction; 1261 toDecode->size++; 1262 1263 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid); 1264 1265 fetchStatus[tid] = TrapPending; 1266 status_change = true; 1267 1268 DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %08p", 1269 tid, fault->name(), PC[tid]); 1270 } 1271} 1272 1273template<class Impl> 1274void 1275DefaultFetch<Impl>::recvRetry() 1276{ 1277 if (retryPkt != NULL) { 1278 assert(cacheBlocked); 1279 assert(retryTid != -1); 1280 assert(fetchStatus[retryTid] == IcacheWaitRetry); 1281 1282 if (icachePort->sendTiming(retryPkt)) { 1283 fetchStatus[retryTid] = IcacheWaitResponse; 1284 retryPkt = NULL; 1285 retryTid = -1; 1286 cacheBlocked = false; 1287 } 1288 } else { 1289 assert(retryTid == -1); 1290 // Access has been squashed since it was sent out. Just clear 1291 // the cache being blocked. 1292 cacheBlocked = false; 1293 } 1294} 1295 1296/////////////////////////////////////// 1297// // 1298// SMT FETCH POLICY MAINTAINED HERE // 1299// // 1300/////////////////////////////////////// 1301template<class Impl> 1302int 1303DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority) 1304{ 1305 if (numThreads > 1) { 1306 switch (fetch_priority) { 1307 1308 case SingleThread: 1309 return 0; 1310 1311 case RoundRobin: 1312 return roundRobin(); 1313 1314 case IQ: 1315 return iqCount(); 1316 1317 case LSQ: 1318 return lsqCount(); 1319 1320 case Branch: 1321 return branchCount(); 1322 1323 default: 1324 return -1; 1325 } 1326 } else { 1327 std::list<unsigned>::iterator thread = activeThreads->begin(); 1328 assert(thread != activeThreads->end()); 1329 int tid = *thread; 1330 1331 if (fetchStatus[tid] == Running || 1332 fetchStatus[tid] == IcacheAccessComplete || 1333 fetchStatus[tid] == Idle) { 1334 return tid; 1335 } else { 1336 return -1; 1337 } 1338 } 1339 1340} 1341 1342 1343template<class Impl> 1344int 1345DefaultFetch<Impl>::roundRobin() 1346{ 1347 std::list<unsigned>::iterator pri_iter = priorityList.begin(); 1348 std::list<unsigned>::iterator end = priorityList.end(); 1349 1350 int high_pri; 1351 1352 while (pri_iter != end) { 1353 high_pri = *pri_iter; 1354 1355 assert(high_pri <= numThreads); 1356 1357 if (fetchStatus[high_pri] == Running || 1358 fetchStatus[high_pri] == IcacheAccessComplete || 1359 fetchStatus[high_pri] == Idle) { 1360 1361 priorityList.erase(pri_iter); 1362 priorityList.push_back(high_pri); 1363 1364 return high_pri; 1365 } 1366 1367 pri_iter++; 1368 } 1369 1370 return -1; 1371} 1372 1373template<class Impl> 1374int 1375DefaultFetch<Impl>::iqCount() 1376{ 1377 std::priority_queue<unsigned> PQ; 1378 1379 std::list<unsigned>::iterator threads = activeThreads->begin(); 1380 std::list<unsigned>::iterator end = activeThreads->end(); 1381 1382 while (threads != end) { 1383 unsigned tid = *threads++; 1384 1385 PQ.push(fromIEW->iewInfo[tid].iqCount); 1386 } 1387 1388 while (!PQ.empty()) { 1389 1390 unsigned high_pri = PQ.top(); 1391 1392 if (fetchStatus[high_pri] == Running || 1393 fetchStatus[high_pri] == IcacheAccessComplete || 1394 fetchStatus[high_pri] == Idle) 1395 return high_pri; 1396 else 1397 PQ.pop(); 1398 1399 } 1400 1401 return -1; 1402} 1403 1404template<class Impl> 1405int 1406DefaultFetch<Impl>::lsqCount() 1407{ 1408 std::priority_queue<unsigned> PQ; 1409 1410 std::list<unsigned>::iterator threads = activeThreads->begin(); 1411 std::list<unsigned>::iterator end = activeThreads->end(); 1412 1413 while (threads != end) { 1414 unsigned tid = *threads++; 1415 1416 PQ.push(fromIEW->iewInfo[tid].ldstqCount); 1417 } 1418 1419 while (!PQ.empty()) { 1420 1421 unsigned high_pri = PQ.top(); 1422 1423 if (fetchStatus[high_pri] == Running || 1424 fetchStatus[high_pri] == IcacheAccessComplete || 1425 fetchStatus[high_pri] == Idle) 1426 return high_pri; 1427 else 1428 PQ.pop(); 1429 1430 } 1431 1432 return -1; 1433} 1434 1435template<class Impl> 1436int 1437DefaultFetch<Impl>::branchCount() 1438{ 1439 std::list<unsigned>::iterator thread = activeThreads->begin(); 1440 assert(thread != activeThreads->end()); 1441 unsigned tid = *thread; 1442 1443 panic("Branch Count Fetch policy unimplemented\n"); 1444 return 0 * tid; 1445} 1446