fetch_impl.hh revision 5012:c0a28154d002
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#include <algorithm> 33#include <cstring> 34 35#include "config/use_checker.hh" 36 37#include "arch/isa_traits.hh" 38#include "arch/utility.hh" 39#include "cpu/checker/cpu.hh" 40#include "cpu/exetrace.hh" 41#include "cpu/o3/fetch.hh" 42#include "mem/packet.hh" 43#include "mem/request.hh" 44#include "sim/byteswap.hh" 45#include "sim/host.hh" 46#include "sim/core.hh" 47 48#if FULL_SYSTEM 49#include "arch/tlb.hh" 50#include "arch/vtophys.hh" 51#include "sim/system.hh" 52#endif // FULL_SYSTEM 53 54template<class Impl> 55void 56DefaultFetch<Impl>::IcachePort::setPeer(Port *port) 57{ 58 Port::setPeer(port); 59 60 fetch->setIcache(); 61} 62 63template<class Impl> 64Tick 65DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt) 66{ 67 panic("DefaultFetch doesn't expect recvAtomic callback!"); 68 return curTick; 69} 70 71template<class Impl> 72void 73DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt) 74{ 75 DPRINTF(Fetch, "DefaultFetch doesn't update its state from a " 76 "functional call."); 77} 78 79template<class Impl> 80void 81DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status) 82{ 83 if (status == RangeChange) { 84 if (!snoopRangeSent) { 85 snoopRangeSent = true; 86 sendStatusChange(Port::RangeChange); 87 } 88 return; 89 } 90 91 panic("DefaultFetch doesn't expect recvStatusChange callback!"); 92} 93 94template<class Impl> 95bool 96DefaultFetch<Impl>::IcachePort::recvTiming(PacketPtr pkt) 97{ 98 DPRINTF(Fetch, "Received timing\n"); 99 if (pkt->isResponse()) { 100 fetch->processCacheCompletion(pkt); 101 } 102 //else Snooped a coherence request, just return 103 return true; 104} 105 106template<class Impl> 107void 108DefaultFetch<Impl>::IcachePort::recvRetry() 109{ 110 fetch->recvRetry(); 111} 112 113template<class Impl> 114DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, Params *params) 115 : cpu(_cpu), 116 branchPred(params), 117 predecoder(NULL), 118 decodeToFetchDelay(params->decodeToFetchDelay), 119 renameToFetchDelay(params->renameToFetchDelay), 120 iewToFetchDelay(params->iewToFetchDelay), 121 commitToFetchDelay(params->commitToFetchDelay), 122 fetchWidth(params->fetchWidth), 123 cacheBlocked(false), 124 retryPkt(NULL), 125 retryTid(-1), 126 numThreads(params->numberOfThreads), 127 numFetchingThreads(params->smtNumFetchingThreads), 128 interruptPending(false), 129 drainPending(false), 130 switchedOut(false) 131{ 132 if (numThreads > Impl::MaxThreads) 133 fatal("numThreads is not a valid value\n"); 134 135 // Set fetch stage's status to inactive. 136 _status = Inactive; 137 138 std::string policy = params->smtFetchPolicy; 139 140 // Convert string to lowercase 141 std::transform(policy.begin(), policy.end(), policy.begin(), 142 (int(*)(int)) tolower); 143 144 // Figure out fetch policy 145 if (policy == "singlethread") { 146 fetchPolicy = SingleThread; 147 if (numThreads > 1) 148 panic("Invalid Fetch Policy for a SMT workload."); 149 } else if (policy == "roundrobin") { 150 fetchPolicy = RoundRobin; 151 DPRINTF(Fetch, "Fetch policy set to Round Robin\n"); 152 } else if (policy == "branch") { 153 fetchPolicy = Branch; 154 DPRINTF(Fetch, "Fetch policy set to Branch Count\n"); 155 } else if (policy == "iqcount") { 156 fetchPolicy = IQ; 157 DPRINTF(Fetch, "Fetch policy set to IQ count\n"); 158 } else if (policy == "lsqcount") { 159 fetchPolicy = LSQ; 160 DPRINTF(Fetch, "Fetch policy set to LSQ count\n"); 161 } else { 162 fatal("Invalid Fetch Policy. Options Are: {SingleThread," 163 " RoundRobin,LSQcount,IQcount}\n"); 164 } 165 166 // Get the size of an instruction. 167 instSize = sizeof(TheISA::MachInst); 168 169 // Name is finally available, so create the port. 170 icachePort = new IcachePort(this); 171 172 icachePort->snoopRangeSent = false; 173 174#if USE_CHECKER 175 if (cpu->checker) { 176 cpu->checker->setIcachePort(icachePort); 177 } 178#endif 179} 180 181template <class Impl> 182std::string 183DefaultFetch<Impl>::name() const 184{ 185 return cpu->name() + ".fetch"; 186} 187 188template <class Impl> 189void 190DefaultFetch<Impl>::regStats() 191{ 192 icacheStallCycles 193 .name(name() + ".icacheStallCycles") 194 .desc("Number of cycles fetch is stalled on an Icache miss") 195 .prereq(icacheStallCycles); 196 197 fetchedInsts 198 .name(name() + ".Insts") 199 .desc("Number of instructions fetch has processed") 200 .prereq(fetchedInsts); 201 202 fetchedBranches 203 .name(name() + ".Branches") 204 .desc("Number of branches that fetch encountered") 205 .prereq(fetchedBranches); 206 207 predictedBranches 208 .name(name() + ".predictedBranches") 209 .desc("Number of branches that fetch has predicted taken") 210 .prereq(predictedBranches); 211 212 fetchCycles 213 .name(name() + ".Cycles") 214 .desc("Number of cycles fetch has run and was not squashing or" 215 " blocked") 216 .prereq(fetchCycles); 217 218 fetchSquashCycles 219 .name(name() + ".SquashCycles") 220 .desc("Number of cycles fetch has spent squashing") 221 .prereq(fetchSquashCycles); 222 223 fetchIdleCycles 224 .name(name() + ".IdleCycles") 225 .desc("Number of cycles fetch was idle") 226 .prereq(fetchIdleCycles); 227 228 fetchBlockedCycles 229 .name(name() + ".BlockedCycles") 230 .desc("Number of cycles fetch has spent blocked") 231 .prereq(fetchBlockedCycles); 232 233 fetchedCacheLines 234 .name(name() + ".CacheLines") 235 .desc("Number of cache lines fetched") 236 .prereq(fetchedCacheLines); 237 238 fetchMiscStallCycles 239 .name(name() + ".MiscStallCycles") 240 .desc("Number of cycles fetch has spent waiting on interrupts, or " 241 "bad addresses, or out of MSHRs") 242 .prereq(fetchMiscStallCycles); 243 244 fetchIcacheSquashes 245 .name(name() + ".IcacheSquashes") 246 .desc("Number of outstanding Icache misses that were squashed") 247 .prereq(fetchIcacheSquashes); 248 249 fetchNisnDist 250 .init(/* base value */ 0, 251 /* last value */ fetchWidth, 252 /* bucket size */ 1) 253 .name(name() + ".rateDist") 254 .desc("Number of instructions fetched each cycle (Total)") 255 .flags(Stats::pdf); 256 257 idleRate 258 .name(name() + ".idleRate") 259 .desc("Percent of cycles fetch was idle") 260 .prereq(idleRate); 261 idleRate = fetchIdleCycles * 100 / cpu->numCycles; 262 263 branchRate 264 .name(name() + ".branchRate") 265 .desc("Number of branch fetches per cycle") 266 .flags(Stats::total); 267 branchRate = fetchedBranches / cpu->numCycles; 268 269 fetchRate 270 .name(name() + ".rate") 271 .desc("Number of inst fetches per cycle") 272 .flags(Stats::total); 273 fetchRate = fetchedInsts / cpu->numCycles; 274 275 branchPred.regStats(); 276} 277 278template<class Impl> 279void 280DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer) 281{ 282 timeBuffer = time_buffer; 283 284 // Create wires to get information from proper places in time buffer. 285 fromDecode = timeBuffer->getWire(-decodeToFetchDelay); 286 fromRename = timeBuffer->getWire(-renameToFetchDelay); 287 fromIEW = timeBuffer->getWire(-iewToFetchDelay); 288 fromCommit = timeBuffer->getWire(-commitToFetchDelay); 289} 290 291template<class Impl> 292void 293DefaultFetch<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) 294{ 295 activeThreads = at_ptr; 296} 297 298template<class Impl> 299void 300DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 301{ 302 fetchQueue = fq_ptr; 303 304 // Create wire to write information to proper place in fetch queue. 305 toDecode = fetchQueue->getWire(0); 306} 307 308template<class Impl> 309void 310DefaultFetch<Impl>::initStage() 311{ 312 // Setup PC and nextPC with initial state. 313 for (int tid = 0; tid < numThreads; tid++) { 314 PC[tid] = cpu->readPC(tid); 315 nextPC[tid] = cpu->readNextPC(tid); 316 microPC[tid] = cpu->readMicroPC(tid); 317 } 318 319 for (int tid=0; tid < numThreads; tid++) { 320 321 fetchStatus[tid] = Running; 322 323 priorityList.push_back(tid); 324 325 memReq[tid] = NULL; 326 327 stalls[tid].decode = false; 328 stalls[tid].rename = false; 329 stalls[tid].iew = false; 330 stalls[tid].commit = false; 331 } 332 333 // Schedule fetch to get the correct PC from the CPU 334 // scheduleFetchStartupEvent(1); 335 336 // Fetch needs to start fetching instructions at the very beginning, 337 // so it must start up in active state. 338 switchToActive(); 339} 340 341template<class Impl> 342void 343DefaultFetch<Impl>::setIcache() 344{ 345 // Size of cache block. 346 cacheBlkSize = icachePort->peerBlockSize(); 347 348 // Create mask to get rid of offset bits. 349 cacheBlkMask = (cacheBlkSize - 1); 350 351 for (int tid=0; tid < numThreads; tid++) { 352 // Create space to store a cache line. 353 cacheData[tid] = new uint8_t[cacheBlkSize]; 354 cacheDataPC[tid] = 0; 355 cacheDataValid[tid] = false; 356 } 357} 358 359template<class Impl> 360void 361DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt) 362{ 363 unsigned tid = pkt->req->getThreadNum(); 364 365 DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid); 366 367 assert(!pkt->wasNacked()); 368 369 // Only change the status if it's still waiting on the icache access 370 // to return. 371 if (fetchStatus[tid] != IcacheWaitResponse || 372 pkt->req != memReq[tid] || 373 isSwitchedOut()) { 374 ++fetchIcacheSquashes; 375 delete pkt->req; 376 delete pkt; 377 return; 378 } 379 380 memcpy(cacheData[tid], pkt->getPtr<uint8_t>(), cacheBlkSize); 381 cacheDataValid[tid] = true; 382 383 if (!drainPending) { 384 // Wake up the CPU (if it went to sleep and was waiting on 385 // this completion event). 386 cpu->wakeCPU(); 387 388 DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n", 389 tid); 390 391 switchToActive(); 392 } 393 394 // Only switch to IcacheAccessComplete if we're not stalled as well. 395 if (checkStall(tid)) { 396 fetchStatus[tid] = Blocked; 397 } else { 398 fetchStatus[tid] = IcacheAccessComplete; 399 } 400 401 // Reset the mem req to NULL. 402 delete pkt->req; 403 delete pkt; 404 memReq[tid] = NULL; 405} 406 407template <class Impl> 408bool 409DefaultFetch<Impl>::drain() 410{ 411 // Fetch is ready to drain at any time. 412 cpu->signalDrained(); 413 drainPending = true; 414 return true; 415} 416 417template <class Impl> 418void 419DefaultFetch<Impl>::resume() 420{ 421 drainPending = false; 422} 423 424template <class Impl> 425void 426DefaultFetch<Impl>::switchOut() 427{ 428 switchedOut = true; 429 // Branch predictor needs to have its state cleared. 430 branchPred.switchOut(); 431} 432 433template <class Impl> 434void 435DefaultFetch<Impl>::takeOverFrom() 436{ 437 // Reset all state 438 for (int i = 0; i < Impl::MaxThreads; ++i) { 439 stalls[i].decode = 0; 440 stalls[i].rename = 0; 441 stalls[i].iew = 0; 442 stalls[i].commit = 0; 443 PC[i] = cpu->readPC(i); 444 nextPC[i] = cpu->readNextPC(i); 445 microPC[i] = cpu->readMicroPC(i); 446 fetchStatus[i] = Running; 447 } 448 numInst = 0; 449 wroteToTimeBuffer = false; 450 _status = Inactive; 451 switchedOut = false; 452 interruptPending = false; 453 branchPred.takeOverFrom(); 454} 455 456template <class Impl> 457void 458DefaultFetch<Impl>::wakeFromQuiesce() 459{ 460 DPRINTF(Fetch, "Waking up from quiesce\n"); 461 // Hopefully this is safe 462 // @todo: Allow other threads to wake from quiesce. 463 fetchStatus[0] = Running; 464} 465 466template <class Impl> 467inline void 468DefaultFetch<Impl>::switchToActive() 469{ 470 if (_status == Inactive) { 471 DPRINTF(Activity, "Activating stage.\n"); 472 473 cpu->activateStage(O3CPU::FetchIdx); 474 475 _status = Active; 476 } 477} 478 479template <class Impl> 480inline void 481DefaultFetch<Impl>::switchToInactive() 482{ 483 if (_status == Active) { 484 DPRINTF(Activity, "Deactivating stage.\n"); 485 486 cpu->deactivateStage(O3CPU::FetchIdx); 487 488 _status = Inactive; 489 } 490} 491 492template <class Impl> 493bool 494DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC, 495 Addr &next_NPC, Addr &next_MicroPC) 496{ 497 // Do branch prediction check here. 498 // A bit of a misnomer...next_PC is actually the current PC until 499 // this function updates it. 500 bool predict_taken; 501 502 if (!inst->isControl()) { 503 if (inst->isMicroop() && !inst->isLastMicroop()) { 504 next_MicroPC++; 505 } else { 506 next_PC = next_NPC; 507 next_NPC = next_NPC + instSize; 508 next_MicroPC = 0; 509 } 510 inst->setPredTarg(next_PC, next_NPC, next_MicroPC); 511 inst->setPredTaken(false); 512 return false; 513 } 514 515 //Assume for now that all control flow is to a different macroop which 516 //would reset the micro pc to 0. 517 next_MicroPC = 0; 518 519 int tid = inst->threadNumber; 520 Addr pred_PC = next_PC; 521 predict_taken = branchPred.predict(inst, pred_PC, tid); 522 523/* if (predict_taken) { 524 DPRINTF(Fetch, "[tid:%i]: Branch predicted to be taken to %#x.\n", 525 tid, pred_PC); 526 } else { 527 DPRINTF(Fetch, "[tid:%i]: Branch predicted to be not taken.\n", tid); 528 }*/ 529 530#if ISA_HAS_DELAY_SLOT 531 next_PC = next_NPC; 532 if (predict_taken) 533 next_NPC = pred_PC; 534 else 535 next_NPC += instSize; 536#else 537 if (predict_taken) 538 next_PC = pred_PC; 539 else 540 next_PC += instSize; 541 next_NPC = next_PC + instSize; 542#endif 543/* DPRINTF(Fetch, "[tid:%i]: Branch predicted to go to %#x and then %#x.\n", 544 tid, next_PC, next_NPC);*/ 545 inst->setPredTarg(next_PC, next_NPC, next_MicroPC); 546 inst->setPredTaken(predict_taken); 547 548 ++fetchedBranches; 549 550 if (predict_taken) { 551 ++predictedBranches; 552 } 553 554 return predict_taken; 555} 556 557template <class Impl> 558bool 559DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid) 560{ 561 Fault fault = NoFault; 562 563 //AlphaDep 564 if (cacheBlocked) { 565 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n", 566 tid); 567 return false; 568 } else if (isSwitchedOut()) { 569 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, switched out\n", 570 tid); 571 return false; 572 } else if (interruptPending && !(fetch_PC & 0x3)) { 573 // Hold off fetch from getting new instructions when: 574 // Cache is blocked, or 575 // while an interrupt is pending and we're not in PAL mode, or 576 // fetch is switched out. 577 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n", 578 tid); 579 return false; 580 } 581 582 // Align the fetch PC so it's at the start of a cache block. 583 Addr block_PC = icacheBlockAlignPC(fetch_PC); 584 585 // If we've already got the block, no need to try to fetch it again. 586 if (cacheDataValid[tid] && block_PC == cacheDataPC[tid]) { 587 return true; 588 } 589 590 // Setup the memReq to do a read of the first instruction's address. 591 // Set the appropriate read size and flags as well. 592 // Build request here. 593 RequestPtr mem_req = new Request(tid, block_PC, cacheBlkSize, 0, 594 fetch_PC, cpu->readCpuId(), tid); 595 596 memReq[tid] = mem_req; 597 598 // Translate the instruction request. 599 fault = cpu->translateInstReq(mem_req, cpu->thread[tid]); 600 601 // In the case of faults, the fetch stage may need to stall and wait 602 // for the ITB miss to be handled. 603 604 // If translation was successful, attempt to read the first 605 // instruction. 606 if (fault == NoFault) { 607#if 0 608 if (cpu->system->memctrl->badaddr(memReq[tid]->paddr) || 609 memReq[tid]->isUncacheable()) { 610 DPRINTF(Fetch, "Fetch: Bad address %#x (hopefully on a " 611 "misspeculating path)!", 612 memReq[tid]->paddr); 613 ret_fault = TheISA::genMachineCheckFault(); 614 return false; 615 } 616#endif 617 618 // Build packet here. 619 PacketPtr data_pkt = new Packet(mem_req, 620 MemCmd::ReadReq, Packet::Broadcast); 621 data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]); 622 623 cacheDataPC[tid] = block_PC; 624 cacheDataValid[tid] = false; 625 626 DPRINTF(Fetch, "Fetch: Doing instruction read.\n"); 627 628 fetchedCacheLines++; 629 630 // Now do the timing access to see whether or not the instruction 631 // exists within the cache. 632 if (!icachePort->sendTiming(data_pkt)) { 633 assert(retryPkt == NULL); 634 assert(retryTid == -1); 635 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid); 636 fetchStatus[tid] = IcacheWaitRetry; 637 retryPkt = data_pkt; 638 retryTid = tid; 639 cacheBlocked = true; 640 return false; 641 } 642 643 DPRINTF(Fetch, "[tid:%i]: Doing cache access.\n", tid); 644 645 lastIcacheStall[tid] = curTick; 646 647 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache " 648 "response.\n", tid); 649 650 fetchStatus[tid] = IcacheWaitResponse; 651 } else { 652 delete mem_req; 653 memReq[tid] = NULL; 654 } 655 656 ret_fault = fault; 657 return true; 658} 659 660template <class Impl> 661inline void 662DefaultFetch<Impl>::doSquash(const Addr &new_PC, 663 const Addr &new_NPC, const Addr &new_microPC, unsigned tid) 664{ 665 DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x, NPC to: %#x.\n", 666 tid, new_PC, new_NPC); 667 668 PC[tid] = new_PC; 669 nextPC[tid] = new_NPC; 670 microPC[tid] = new_microPC; 671 672 // Clear the icache miss if it's outstanding. 673 if (fetchStatus[tid] == IcacheWaitResponse) { 674 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n", 675 tid); 676 memReq[tid] = NULL; 677 } 678 679 // Get rid of the retrying packet if it was from this thread. 680 if (retryTid == tid) { 681 assert(cacheBlocked); 682 if (retryPkt) { 683 delete retryPkt->req; 684 delete retryPkt; 685 } 686 retryPkt = NULL; 687 retryTid = -1; 688 } 689 690 fetchStatus[tid] = Squashing; 691 692 ++fetchSquashCycles; 693} 694 695template<class Impl> 696void 697DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC, const Addr &new_NPC, 698 const Addr &new_MicroPC, 699 const InstSeqNum &seq_num, unsigned tid) 700{ 701 DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid); 702 703 doSquash(new_PC, new_NPC, new_MicroPC, tid); 704 705 // Tell the CPU to remove any instructions that are in flight between 706 // fetch and decode. 707 cpu->removeInstsUntil(seq_num, tid); 708} 709 710template<class Impl> 711bool 712DefaultFetch<Impl>::checkStall(unsigned tid) const 713{ 714 bool ret_val = false; 715 716 if (cpu->contextSwitch) { 717 DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid); 718 ret_val = true; 719 } else if (stalls[tid].decode) { 720 DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid); 721 ret_val = true; 722 } else if (stalls[tid].rename) { 723 DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid); 724 ret_val = true; 725 } else if (stalls[tid].iew) { 726 DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid); 727 ret_val = true; 728 } else if (stalls[tid].commit) { 729 DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid); 730 ret_val = true; 731 } 732 733 return ret_val; 734} 735 736template<class Impl> 737typename DefaultFetch<Impl>::FetchStatus 738DefaultFetch<Impl>::updateFetchStatus() 739{ 740 //Check Running 741 std::list<unsigned>::iterator threads = activeThreads->begin(); 742 std::list<unsigned>::iterator end = activeThreads->end(); 743 744 while (threads != end) { 745 unsigned tid = *threads++; 746 747 if (fetchStatus[tid] == Running || 748 fetchStatus[tid] == Squashing || 749 fetchStatus[tid] == IcacheAccessComplete) { 750 751 if (_status == Inactive) { 752 DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid); 753 754 if (fetchStatus[tid] == IcacheAccessComplete) { 755 DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache" 756 "completion\n",tid); 757 } 758 759 cpu->activateStage(O3CPU::FetchIdx); 760 } 761 762 return Active; 763 } 764 } 765 766 // Stage is switching from active to inactive, notify CPU of it. 767 if (_status == Active) { 768 DPRINTF(Activity, "Deactivating stage.\n"); 769 770 cpu->deactivateStage(O3CPU::FetchIdx); 771 } 772 773 return Inactive; 774} 775 776template <class Impl> 777void 778DefaultFetch<Impl>::squash(const Addr &new_PC, const Addr &new_NPC, 779 const Addr &new_MicroPC, 780 const InstSeqNum &seq_num, unsigned tid) 781{ 782 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid); 783 784 doSquash(new_PC, new_NPC, new_MicroPC, tid); 785 786 // Tell the CPU to remove any instructions that are not in the ROB. 787 cpu->removeInstsNotInROB(tid); 788} 789 790template <class Impl> 791void 792DefaultFetch<Impl>::tick() 793{ 794 std::list<unsigned>::iterator threads = activeThreads->begin(); 795 std::list<unsigned>::iterator end = activeThreads->end(); 796 bool status_change = false; 797 798 wroteToTimeBuffer = false; 799 800 while (threads != end) { 801 unsigned tid = *threads++; 802 803 // Check the signals for each thread to determine the proper status 804 // for each thread. 805 bool updated_status = checkSignalsAndUpdate(tid); 806 status_change = status_change || updated_status; 807 } 808 809 DPRINTF(Fetch, "Running stage.\n"); 810 811 // Reset the number of the instruction we're fetching. 812 numInst = 0; 813 814#if FULL_SYSTEM 815 if (fromCommit->commitInfo[0].interruptPending) { 816 interruptPending = true; 817 } 818 819 if (fromCommit->commitInfo[0].clearInterrupt) { 820 interruptPending = false; 821 } 822#endif 823 824 for (threadFetched = 0; threadFetched < numFetchingThreads; 825 threadFetched++) { 826 // Fetch each of the actively fetching threads. 827 fetch(status_change); 828 } 829 830 // Record number of instructions fetched this cycle for distribution. 831 fetchNisnDist.sample(numInst); 832 833 if (status_change) { 834 // Change the fetch stage status if there was a status change. 835 _status = updateFetchStatus(); 836 } 837 838 // If there was activity this cycle, inform the CPU of it. 839 if (wroteToTimeBuffer || cpu->contextSwitch) { 840 DPRINTF(Activity, "Activity this cycle.\n"); 841 842 cpu->activityThisCycle(); 843 } 844} 845 846template <class Impl> 847bool 848DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid) 849{ 850 // Update the per thread stall statuses. 851 if (fromDecode->decodeBlock[tid]) { 852 stalls[tid].decode = true; 853 } 854 855 if (fromDecode->decodeUnblock[tid]) { 856 assert(stalls[tid].decode); 857 assert(!fromDecode->decodeBlock[tid]); 858 stalls[tid].decode = false; 859 } 860 861 if (fromRename->renameBlock[tid]) { 862 stalls[tid].rename = true; 863 } 864 865 if (fromRename->renameUnblock[tid]) { 866 assert(stalls[tid].rename); 867 assert(!fromRename->renameBlock[tid]); 868 stalls[tid].rename = false; 869 } 870 871 if (fromIEW->iewBlock[tid]) { 872 stalls[tid].iew = true; 873 } 874 875 if (fromIEW->iewUnblock[tid]) { 876 assert(stalls[tid].iew); 877 assert(!fromIEW->iewBlock[tid]); 878 stalls[tid].iew = false; 879 } 880 881 if (fromCommit->commitBlock[tid]) { 882 stalls[tid].commit = true; 883 } 884 885 if (fromCommit->commitUnblock[tid]) { 886 assert(stalls[tid].commit); 887 assert(!fromCommit->commitBlock[tid]); 888 stalls[tid].commit = false; 889 } 890 891 // Check squash signals from commit. 892 if (fromCommit->commitInfo[tid].squash) { 893 894 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash " 895 "from commit.\n",tid); 896 // In any case, squash. 897 squash(fromCommit->commitInfo[tid].nextPC, 898 fromCommit->commitInfo[tid].nextNPC, 899 fromCommit->commitInfo[tid].nextMicroPC, 900 fromCommit->commitInfo[tid].doneSeqNum, 901 tid); 902 903 // Also check if there's a mispredict that happened. 904 if (fromCommit->commitInfo[tid].branchMispredict) { 905 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum, 906 fromCommit->commitInfo[tid].nextPC, 907 fromCommit->commitInfo[tid].branchTaken, 908 tid); 909 } else { 910 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum, 911 tid); 912 } 913 914 return true; 915 } else if (fromCommit->commitInfo[tid].doneSeqNum) { 916 // Update the branch predictor if it wasn't a squashed instruction 917 // that was broadcasted. 918 branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid); 919 } 920 921 // Check ROB squash signals from commit. 922 if (fromCommit->commitInfo[tid].robSquashing) { 923 DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid); 924 925 // Continue to squash. 926 fetchStatus[tid] = Squashing; 927 928 return true; 929 } 930 931 // Check squash signals from decode. 932 if (fromDecode->decodeInfo[tid].squash) { 933 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash " 934 "from decode.\n",tid); 935 936 // Update the branch predictor. 937 if (fromDecode->decodeInfo[tid].branchMispredict) { 938 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum, 939 fromDecode->decodeInfo[tid].nextPC, 940 fromDecode->decodeInfo[tid].branchTaken, 941 tid); 942 } else { 943 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum, 944 tid); 945 } 946 947 if (fetchStatus[tid] != Squashing) { 948 949 DPRINTF(Fetch, "Squashing from decode with PC = %#x, NPC = %#x\n", 950 fromDecode->decodeInfo[tid].nextPC, 951 fromDecode->decodeInfo[tid].nextNPC); 952 // Squash unless we're already squashing 953 squashFromDecode(fromDecode->decodeInfo[tid].nextPC, 954 fromDecode->decodeInfo[tid].nextNPC, 955 fromDecode->decodeInfo[tid].nextMicroPC, 956 fromDecode->decodeInfo[tid].doneSeqNum, 957 tid); 958 959 return true; 960 } 961 } 962 963 if (checkStall(tid) && 964 fetchStatus[tid] != IcacheWaitResponse && 965 fetchStatus[tid] != IcacheWaitRetry) { 966 DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid); 967 968 fetchStatus[tid] = Blocked; 969 970 return true; 971 } 972 973 if (fetchStatus[tid] == Blocked || 974 fetchStatus[tid] == Squashing) { 975 // Switch status to running if fetch isn't being told to block or 976 // squash this cycle. 977 DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n", 978 tid); 979 980 fetchStatus[tid] = Running; 981 982 return true; 983 } 984 985 // If we've reached this point, we have not gotten any signals that 986 // cause fetch to change its status. Fetch remains the same as before. 987 return false; 988} 989 990template<class Impl> 991void 992DefaultFetch<Impl>::fetch(bool &status_change) 993{ 994 ////////////////////////////////////////// 995 // Start actual fetch 996 ////////////////////////////////////////// 997 int tid = getFetchingThread(fetchPolicy); 998 999 if (tid == -1 || drainPending) { 1000 DPRINTF(Fetch,"There are no more threads available to fetch from.\n"); 1001 1002 // Breaks looping condition in tick() 1003 threadFetched = numFetchingThreads; 1004 return; 1005 } 1006 1007 DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid); 1008 1009 // The current PC. 1010 Addr fetch_PC = PC[tid]; 1011 Addr fetch_NPC = nextPC[tid]; 1012 Addr fetch_MicroPC = microPC[tid]; 1013 1014 // Fault code for memory access. 1015 Fault fault = NoFault; 1016 1017 // If returning from the delay of a cache miss, then update the status 1018 // to running, otherwise do the cache access. Possibly move this up 1019 // to tick() function. 1020 if (fetchStatus[tid] == IcacheAccessComplete) { 1021 DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n", 1022 tid); 1023 1024 fetchStatus[tid] = Running; 1025 status_change = true; 1026 } else if (fetchStatus[tid] == Running) { 1027 DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read " 1028 "instruction, starting at PC %08p.\n", 1029 tid, fetch_PC); 1030 1031 bool fetch_success = fetchCacheLine(fetch_PC, fault, tid); 1032 if (!fetch_success) { 1033 if (cacheBlocked) { 1034 ++icacheStallCycles; 1035 } else { 1036 ++fetchMiscStallCycles; 1037 } 1038 return; 1039 } 1040 } else { 1041 if (fetchStatus[tid] == Idle) { 1042 ++fetchIdleCycles; 1043 DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid); 1044 } else if (fetchStatus[tid] == Blocked) { 1045 ++fetchBlockedCycles; 1046 DPRINTF(Fetch, "[tid:%i]: Fetch is blocked!\n", tid); 1047 } else if (fetchStatus[tid] == Squashing) { 1048 ++fetchSquashCycles; 1049 DPRINTF(Fetch, "[tid:%i]: Fetch is squashing!\n", tid); 1050 } else if (fetchStatus[tid] == IcacheWaitResponse) { 1051 ++icacheStallCycles; 1052 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n", tid); 1053 } 1054 1055 // Status is Idle, Squashing, Blocked, or IcacheWaitResponse, so 1056 // fetch should do nothing. 1057 return; 1058 } 1059 1060 ++fetchCycles; 1061 1062 // If we had a stall due to an icache miss, then return. 1063 if (fetchStatus[tid] == IcacheWaitResponse) { 1064 ++icacheStallCycles; 1065 status_change = true; 1066 return; 1067 } 1068 1069 Addr next_PC = fetch_PC; 1070 Addr next_NPC = fetch_NPC; 1071 Addr next_MicroPC = fetch_MicroPC; 1072 1073 InstSeqNum inst_seq; 1074 MachInst inst; 1075 ExtMachInst ext_inst; 1076 // @todo: Fix this hack. 1077 unsigned offset = (fetch_PC & cacheBlkMask) & ~3; 1078 1079 StaticInstPtr staticInst = NULL; 1080 StaticInstPtr macroop = NULL; 1081 1082 if (fault == NoFault) { 1083 // If the read of the first instruction was successful, then grab the 1084 // instructions from the rest of the cache line and put them into the 1085 // queue heading to decode. 1086 1087 DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to " 1088 "decode.\n",tid); 1089 1090 // Need to keep track of whether or not a predicted branch 1091 // ended this fetch block. 1092 bool predicted_branch = false; 1093 1094 while (offset < cacheBlkSize && 1095 numInst < fetchWidth && 1096 !predicted_branch) { 1097 1098 // If we're branching after this instruction, quite fetching 1099 // from the same block then. 1100 predicted_branch = 1101 (fetch_PC + sizeof(TheISA::MachInst) != fetch_NPC); 1102 if (predicted_branch) { 1103 DPRINTF(Fetch, "Branch detected with PC = %#x, NPC = %#x\n", 1104 fetch_PC, fetch_NPC); 1105 } 1106 1107 // Make sure this is a valid index. 1108 assert(offset <= cacheBlkSize - instSize); 1109 1110 if (!macroop) { 1111 // Get the instruction from the array of the cache line. 1112 inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *> 1113 (&cacheData[tid][offset])); 1114 1115 predecoder.setTC(cpu->thread[tid]->getTC()); 1116 predecoder.moreBytes(fetch_PC, fetch_PC, inst); 1117 1118 ext_inst = predecoder.getExtMachInst(); 1119 staticInst = StaticInstPtr(ext_inst, fetch_PC); 1120 if (staticInst->isMacroop()) 1121 macroop = staticInst; 1122 } 1123 do { 1124 if (macroop) { 1125 staticInst = macroop->fetchMicroop(fetch_MicroPC); 1126 if (staticInst->isLastMicroop()) 1127 macroop = NULL; 1128 } 1129 1130 // Get a sequence number. 1131 inst_seq = cpu->getAndIncrementInstSeq(); 1132 1133 // Create a new DynInst from the instruction fetched. 1134 DynInstPtr instruction = new DynInst(staticInst, 1135 fetch_PC, fetch_NPC, fetch_MicroPC, 1136 next_PC, next_NPC, next_MicroPC, 1137 inst_seq, cpu); 1138 instruction->setTid(tid); 1139 1140 instruction->setASID(tid); 1141 1142 instruction->setThreadState(cpu->thread[tid]); 1143 1144 DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created " 1145 "[sn:%lli]\n", 1146 tid, instruction->readPC(), inst_seq); 1147 1148 //DPRINTF(Fetch, "[tid:%i]: MachInst is %#x\n", tid, ext_inst); 1149 1150 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", 1151 tid, instruction->staticInst->disassemble(fetch_PC)); 1152 1153#if TRACING_ON 1154 instruction->traceData = 1155 cpu->getTracer()->getInstRecord(curTick, cpu->tcBase(tid), 1156 instruction->staticInst, instruction->readPC()); 1157#else 1158 instruction->traceData = NULL; 1159#endif 1160 1161 ///FIXME This needs to be more robust in dealing with delay slots 1162 predicted_branch |= 1163 lookupAndUpdateNextPC(instruction, next_PC, next_NPC, next_MicroPC); 1164 1165 // Add instruction to the CPU's list of instructions. 1166 instruction->setInstListIt(cpu->addInst(instruction)); 1167 1168 // Write the instruction to the first slot in the queue 1169 // that heads to decode. 1170 toDecode->insts[numInst] = instruction; 1171 1172 toDecode->size++; 1173 1174 // Increment stat of fetched instructions. 1175 ++fetchedInsts; 1176 1177 // Move to the next instruction, unless we have a branch. 1178 fetch_PC = next_PC; 1179 fetch_NPC = next_NPC; 1180 fetch_MicroPC = next_MicroPC; 1181 1182 if (instruction->isQuiesce()) { 1183 DPRINTF(Fetch, "Quiesce instruction encountered, halting fetch!", 1184 curTick); 1185 fetchStatus[tid] = QuiescePending; 1186 ++numInst; 1187 status_change = true; 1188 break; 1189 } 1190 1191 ++numInst; 1192 } while (staticInst->isMicroop() && 1193 !staticInst->isLastMicroop() && 1194 numInst < fetchWidth); 1195 offset += instSize; 1196 } 1197 1198 if (predicted_branch) { 1199 DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch " 1200 "instruction encountered.\n", tid); 1201 } else if (numInst >= fetchWidth) { 1202 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth " 1203 "for this cycle.\n", tid); 1204 } else if (offset >= cacheBlkSize) { 1205 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache " 1206 "block.\n", tid); 1207 } 1208 } 1209 1210 if (numInst > 0) { 1211 wroteToTimeBuffer = true; 1212 } 1213 1214 // Now that fetching is completed, update the PC to signify what the next 1215 // cycle will be. 1216 if (fault == NoFault) { 1217 PC[tid] = next_PC; 1218 nextPC[tid] = next_NPC; 1219 microPC[tid] = next_MicroPC; 1220 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, next_PC); 1221 } else { 1222 // We shouldn't be in an icache miss and also have a fault (an ITB 1223 // miss) 1224 if (fetchStatus[tid] == IcacheWaitResponse) { 1225 panic("Fetch should have exited prior to this!"); 1226 } 1227 1228 // Send the fault to commit. This thread will not do anything 1229 // until commit handles the fault. The only other way it can 1230 // wake up is if a squash comes along and changes the PC. 1231 assert(numInst < fetchWidth); 1232 // Get a sequence number. 1233 inst_seq = cpu->getAndIncrementInstSeq(); 1234 // We will use a nop in order to carry the fault. 1235 ext_inst = TheISA::NoopMachInst; 1236 1237 // Create a new DynInst from the dummy nop. 1238 DynInstPtr instruction = new DynInst(ext_inst, 1239 fetch_PC, fetch_NPC, fetch_MicroPC, 1240 next_PC, next_NPC, next_MicroPC, 1241 inst_seq, cpu); 1242 instruction->setPredTarg(next_NPC, next_NPC + instSize, 0); 1243 instruction->setTid(tid); 1244 1245 instruction->setASID(tid); 1246 1247 instruction->setThreadState(cpu->thread[tid]); 1248 1249 instruction->traceData = NULL; 1250 1251 instruction->setInstListIt(cpu->addInst(instruction)); 1252 1253 instruction->fault = fault; 1254 1255 toDecode->insts[numInst] = instruction; 1256 toDecode->size++; 1257 1258 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid); 1259 1260 fetchStatus[tid] = TrapPending; 1261 status_change = true; 1262 1263 DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %08p", 1264 tid, fault->name(), PC[tid]); 1265 } 1266} 1267 1268template<class Impl> 1269void 1270DefaultFetch<Impl>::recvRetry() 1271{ 1272 if (retryPkt != NULL) { 1273 assert(cacheBlocked); 1274 assert(retryTid != -1); 1275 assert(fetchStatus[retryTid] == IcacheWaitRetry); 1276 1277 if (icachePort->sendTiming(retryPkt)) { 1278 fetchStatus[retryTid] = IcacheWaitResponse; 1279 retryPkt = NULL; 1280 retryTid = -1; 1281 cacheBlocked = false; 1282 } 1283 } else { 1284 assert(retryTid == -1); 1285 // Access has been squashed since it was sent out. Just clear 1286 // the cache being blocked. 1287 cacheBlocked = false; 1288 } 1289} 1290 1291/////////////////////////////////////// 1292// // 1293// SMT FETCH POLICY MAINTAINED HERE // 1294// // 1295/////////////////////////////////////// 1296template<class Impl> 1297int 1298DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority) 1299{ 1300 if (numThreads > 1) { 1301 switch (fetch_priority) { 1302 1303 case SingleThread: 1304 return 0; 1305 1306 case RoundRobin: 1307 return roundRobin(); 1308 1309 case IQ: 1310 return iqCount(); 1311 1312 case LSQ: 1313 return lsqCount(); 1314 1315 case Branch: 1316 return branchCount(); 1317 1318 default: 1319 return -1; 1320 } 1321 } else { 1322 std::list<unsigned>::iterator thread = activeThreads->begin(); 1323 assert(thread != activeThreads->end()); 1324 int tid = *thread; 1325 1326 if (fetchStatus[tid] == Running || 1327 fetchStatus[tid] == IcacheAccessComplete || 1328 fetchStatus[tid] == Idle) { 1329 return tid; 1330 } else { 1331 return -1; 1332 } 1333 } 1334 1335} 1336 1337 1338template<class Impl> 1339int 1340DefaultFetch<Impl>::roundRobin() 1341{ 1342 std::list<unsigned>::iterator pri_iter = priorityList.begin(); 1343 std::list<unsigned>::iterator end = priorityList.end(); 1344 1345 int high_pri; 1346 1347 while (pri_iter != end) { 1348 high_pri = *pri_iter; 1349 1350 assert(high_pri <= numThreads); 1351 1352 if (fetchStatus[high_pri] == Running || 1353 fetchStatus[high_pri] == IcacheAccessComplete || 1354 fetchStatus[high_pri] == Idle) { 1355 1356 priorityList.erase(pri_iter); 1357 priorityList.push_back(high_pri); 1358 1359 return high_pri; 1360 } 1361 1362 pri_iter++; 1363 } 1364 1365 return -1; 1366} 1367 1368template<class Impl> 1369int 1370DefaultFetch<Impl>::iqCount() 1371{ 1372 std::priority_queue<unsigned> PQ; 1373 1374 std::list<unsigned>::iterator threads = activeThreads->begin(); 1375 std::list<unsigned>::iterator end = activeThreads->end(); 1376 1377 while (threads != end) { 1378 unsigned tid = *threads++; 1379 1380 PQ.push(fromIEW->iewInfo[tid].iqCount); 1381 } 1382 1383 while (!PQ.empty()) { 1384 1385 unsigned high_pri = PQ.top(); 1386 1387 if (fetchStatus[high_pri] == Running || 1388 fetchStatus[high_pri] == IcacheAccessComplete || 1389 fetchStatus[high_pri] == Idle) 1390 return high_pri; 1391 else 1392 PQ.pop(); 1393 1394 } 1395 1396 return -1; 1397} 1398 1399template<class Impl> 1400int 1401DefaultFetch<Impl>::lsqCount() 1402{ 1403 std::priority_queue<unsigned> PQ; 1404 1405 std::list<unsigned>::iterator threads = activeThreads->begin(); 1406 std::list<unsigned>::iterator end = activeThreads->end(); 1407 1408 while (threads != end) { 1409 unsigned tid = *threads++; 1410 1411 PQ.push(fromIEW->iewInfo[tid].ldstqCount); 1412 } 1413 1414 while (!PQ.empty()) { 1415 1416 unsigned high_pri = PQ.top(); 1417 1418 if (fetchStatus[high_pri] == Running || 1419 fetchStatus[high_pri] == IcacheAccessComplete || 1420 fetchStatus[high_pri] == Idle) 1421 return high_pri; 1422 else 1423 PQ.pop(); 1424 1425 } 1426 1427 return -1; 1428} 1429 1430template<class Impl> 1431int 1432DefaultFetch<Impl>::branchCount() 1433{ 1434 std::list<unsigned>::iterator thread = activeThreads->begin(); 1435 assert(thread != activeThreads->end()); 1436 unsigned tid = *thread; 1437 1438 panic("Branch Count Fetch policy unimplemented\n"); 1439 return 0 * tid; 1440} 1441