fetch_impl.hh revision 4636:afc8da9f526e 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 *          Korey Sewell
30 */
31
32#include "config/use_checker.hh"
33
34#include "arch/isa_traits.hh"
35#include "arch/utility.hh"
36#include "cpu/checker/cpu.hh"
37#include "cpu/exetrace.hh"
38#include "cpu/o3/fetch.hh"
39#include "mem/packet.hh"
40#include "mem/request.hh"
41#include "sim/byteswap.hh"
42#include "sim/host.hh"
43#include "sim/core.hh"
44
45#if FULL_SYSTEM
46#include "arch/tlb.hh"
47#include "arch/vtophys.hh"
48#include "sim/system.hh"
49#endif // FULL_SYSTEM
50
51#include <algorithm>
52
53template<class Impl>
54void
55DefaultFetch<Impl>::IcachePort::setPeer(Port *port)
56{
57    Port::setPeer(port);
58
59    fetch->setIcache();
60}
61
62template<class Impl>
63Tick
64DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt)
65{
66    panic("DefaultFetch doesn't expect recvAtomic callback!");
67    return curTick;
68}
69
70template<class Impl>
71void
72DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
73{
74    DPRINTF(Fetch, "DefaultFetch doesn't update its state from a "
75            "functional call.");
76}
77
78template<class Impl>
79void
80DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status)
81{
82    if (status == RangeChange) {
83        if (!snoopRangeSent) {
84            snoopRangeSent = true;
85            sendStatusChange(Port::RangeChange);
86        }
87        return;
88    }
89
90    panic("DefaultFetch doesn't expect recvStatusChange callback!");
91}
92
93template<class Impl>
94bool
95DefaultFetch<Impl>::IcachePort::recvTiming(PacketPtr pkt)
96{
97    DPRINTF(Fetch, "Received timing\n");
98    if (pkt->isResponse()) {
99        fetch->processCacheCompletion(pkt);
100    }
101    //else Snooped a coherence request, just return
102    return true;
103}
104
105template<class Impl>
106void
107DefaultFetch<Impl>::IcachePort::recvRetry()
108{
109    fetch->recvRetry();
110}
111
112template<class Impl>
113DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, Params *params)
114    : cpu(_cpu),
115      branchPred(params),
116      predecoder(NULL),
117      decodeToFetchDelay(params->decodeToFetchDelay),
118      renameToFetchDelay(params->renameToFetchDelay),
119      iewToFetchDelay(params->iewToFetchDelay),
120      commitToFetchDelay(params->commitToFetchDelay),
121      fetchWidth(params->fetchWidth),
122      cacheBlocked(false),
123      retryPkt(NULL),
124      retryTid(-1),
125      numThreads(params->numberOfThreads),
126      numFetchingThreads(params->smtNumFetchingThreads),
127      interruptPending(false),
128      drainPending(false),
129      switchedOut(false)
130{
131    if (numThreads > Impl::MaxThreads)
132        fatal("numThreads is not a valid value\n");
133
134    // Set fetch stage's status to inactive.
135    _status = Inactive;
136
137    std::string policy = params->smtFetchPolicy;
138
139    // Convert string to lowercase
140    std::transform(policy.begin(), policy.end(), policy.begin(),
141                   (int(*)(int)) tolower);
142
143    // Figure out fetch policy
144    if (policy == "singlethread") {
145        fetchPolicy = SingleThread;
146        if (numThreads > 1)
147            panic("Invalid Fetch Policy for a SMT workload.");
148    } else if (policy == "roundrobin") {
149        fetchPolicy = RoundRobin;
150        DPRINTF(Fetch, "Fetch policy set to Round Robin\n");
151    } else if (policy == "branch") {
152        fetchPolicy = Branch;
153        DPRINTF(Fetch, "Fetch policy set to Branch Count\n");
154    } else if (policy == "iqcount") {
155        fetchPolicy = IQ;
156        DPRINTF(Fetch, "Fetch policy set to IQ count\n");
157    } else if (policy == "lsqcount") {
158        fetchPolicy = LSQ;
159        DPRINTF(Fetch, "Fetch policy set to LSQ count\n");
160    } else {
161        fatal("Invalid Fetch Policy. Options Are: {SingleThread,"
162              " RoundRobin,LSQcount,IQcount}\n");
163    }
164
165    // Get the size of an instruction.
166    instSize = sizeof(TheISA::MachInst);
167
168    // Name is finally available, so create the port.
169    icachePort = new IcachePort(this);
170
171    icachePort->snoopRangeSent = false;
172
173#if USE_CHECKER
174    if (cpu->checker) {
175        cpu->checker->setIcachePort(icachePort);
176    }
177#endif
178}
179
180template <class Impl>
181std::string
182DefaultFetch<Impl>::name() const
183{
184    return cpu->name() + ".fetch";
185}
186
187template <class Impl>
188void
189DefaultFetch<Impl>::regStats()
190{
191    icacheStallCycles
192        .name(name() + ".icacheStallCycles")
193        .desc("Number of cycles fetch is stalled on an Icache miss")
194        .prereq(icacheStallCycles);
195
196    fetchedInsts
197        .name(name() + ".Insts")
198        .desc("Number of instructions fetch has processed")
199        .prereq(fetchedInsts);
200
201    fetchedBranches
202        .name(name() + ".Branches")
203        .desc("Number of branches that fetch encountered")
204        .prereq(fetchedBranches);
205
206    predictedBranches
207        .name(name() + ".predictedBranches")
208        .desc("Number of branches that fetch has predicted taken")
209        .prereq(predictedBranches);
210
211    fetchCycles
212        .name(name() + ".Cycles")
213        .desc("Number of cycles fetch has run and was not squashing or"
214              " blocked")
215        .prereq(fetchCycles);
216
217    fetchSquashCycles
218        .name(name() + ".SquashCycles")
219        .desc("Number of cycles fetch has spent squashing")
220        .prereq(fetchSquashCycles);
221
222    fetchIdleCycles
223        .name(name() + ".IdleCycles")
224        .desc("Number of cycles fetch was idle")
225        .prereq(fetchIdleCycles);
226
227    fetchBlockedCycles
228        .name(name() + ".BlockedCycles")
229        .desc("Number of cycles fetch has spent blocked")
230        .prereq(fetchBlockedCycles);
231
232    fetchedCacheLines
233        .name(name() + ".CacheLines")
234        .desc("Number of cache lines fetched")
235        .prereq(fetchedCacheLines);
236
237    fetchMiscStallCycles
238        .name(name() + ".MiscStallCycles")
239        .desc("Number of cycles fetch has spent waiting on interrupts, or "
240              "bad addresses, or out of MSHRs")
241        .prereq(fetchMiscStallCycles);
242
243    fetchIcacheSquashes
244        .name(name() + ".IcacheSquashes")
245        .desc("Number of outstanding Icache misses that were squashed")
246        .prereq(fetchIcacheSquashes);
247
248    fetchNisnDist
249        .init(/* base value */ 0,
250              /* last value */ fetchWidth,
251              /* bucket size */ 1)
252        .name(name() + ".rateDist")
253        .desc("Number of instructions fetched each cycle (Total)")
254        .flags(Stats::pdf);
255
256    idleRate
257        .name(name() + ".idleRate")
258        .desc("Percent of cycles fetch was idle")
259        .prereq(idleRate);
260    idleRate = fetchIdleCycles * 100 / cpu->numCycles;
261
262    branchRate
263        .name(name() + ".branchRate")
264        .desc("Number of branch fetches per cycle")
265        .flags(Stats::total);
266    branchRate = fetchedBranches / cpu->numCycles;
267
268    fetchRate
269        .name(name() + ".rate")
270        .desc("Number of inst fetches per cycle")
271        .flags(Stats::total);
272    fetchRate = fetchedInsts / cpu->numCycles;
273
274    branchPred.regStats();
275}
276
277template<class Impl>
278void
279DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
280{
281    timeBuffer = time_buffer;
282
283    // Create wires to get information from proper places in time buffer.
284    fromDecode = timeBuffer->getWire(-decodeToFetchDelay);
285    fromRename = timeBuffer->getWire(-renameToFetchDelay);
286    fromIEW = timeBuffer->getWire(-iewToFetchDelay);
287    fromCommit = timeBuffer->getWire(-commitToFetchDelay);
288}
289
290template<class Impl>
291void
292DefaultFetch<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
293{
294    activeThreads = at_ptr;
295}
296
297template<class Impl>
298void
299DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
300{
301    fetchQueue = fq_ptr;
302
303    // Create wire to write information to proper place in fetch queue.
304    toDecode = fetchQueue->getWire(0);
305}
306
307template<class Impl>
308void
309DefaultFetch<Impl>::initStage()
310{
311    // Setup PC and nextPC with initial state.
312    for (int tid = 0; tid < numThreads; tid++) {
313        PC[tid] = cpu->readPC(tid);
314        nextPC[tid] = cpu->readNextPC(tid);
315        microPC[tid] = cpu->readMicroPC(tid);
316    }
317
318    for (int tid=0; tid < numThreads; tid++) {
319
320        fetchStatus[tid] = Running;
321
322        priorityList.push_back(tid);
323
324        memReq[tid] = NULL;
325
326        stalls[tid].decode = false;
327        stalls[tid].rename = false;
328        stalls[tid].iew = false;
329        stalls[tid].commit = false;
330    }
331
332    // Schedule fetch to get the correct PC from the CPU
333    // scheduleFetchStartupEvent(1);
334
335    // Fetch needs to start fetching instructions at the very beginning,
336    // so it must start up in active state.
337    switchToActive();
338}
339
340template<class Impl>
341void
342DefaultFetch<Impl>::setIcache()
343{
344    // Size of cache block.
345    cacheBlkSize = icachePort->peerBlockSize();
346
347    // Create mask to get rid of offset bits.
348    cacheBlkMask = (cacheBlkSize - 1);
349
350    for (int tid=0; tid < numThreads; tid++) {
351        // Create space to store a cache line.
352        cacheData[tid] = new uint8_t[cacheBlkSize];
353        cacheDataPC[tid] = 0;
354        cacheDataValid[tid] = false;
355    }
356}
357
358template<class Impl>
359void
360DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
361{
362    unsigned tid = pkt->req->getThreadNum();
363
364    DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid);
365
366    // Only change the status if it's still waiting on the icache access
367    // to return.
368    if (fetchStatus[tid] != IcacheWaitResponse ||
369        pkt->req != memReq[tid] ||
370        isSwitchedOut()) {
371        ++fetchIcacheSquashes;
372        delete pkt->req;
373        delete pkt;
374        return;
375    }
376
377    memcpy(cacheData[tid], pkt->getPtr<uint8_t *>(), cacheBlkSize);
378    cacheDataValid[tid] = true;
379
380    if (!drainPending) {
381        // Wake up the CPU (if it went to sleep and was waiting on
382        // this completion event).
383        cpu->wakeCPU();
384
385        DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",
386                tid);
387
388        switchToActive();
389    }
390
391    // Only switch to IcacheAccessComplete if we're not stalled as well.
392    if (checkStall(tid)) {
393        fetchStatus[tid] = Blocked;
394    } else {
395        fetchStatus[tid] = IcacheAccessComplete;
396    }
397
398    // Reset the mem req to NULL.
399    delete pkt->req;
400    delete pkt;
401    memReq[tid] = NULL;
402}
403
404template <class Impl>
405bool
406DefaultFetch<Impl>::drain()
407{
408    // Fetch is ready to drain at any time.
409    cpu->signalDrained();
410    drainPending = true;
411    return true;
412}
413
414template <class Impl>
415void
416DefaultFetch<Impl>::resume()
417{
418    drainPending = false;
419}
420
421template <class Impl>
422void
423DefaultFetch<Impl>::switchOut()
424{
425    switchedOut = true;
426    // Branch predictor needs to have its state cleared.
427    branchPred.switchOut();
428}
429
430template <class Impl>
431void
432DefaultFetch<Impl>::takeOverFrom()
433{
434    // Reset all state
435    for (int i = 0; i < Impl::MaxThreads; ++i) {
436        stalls[i].decode = 0;
437        stalls[i].rename = 0;
438        stalls[i].iew = 0;
439        stalls[i].commit = 0;
440        PC[i] = cpu->readPC(i);
441        nextPC[i] = cpu->readNextPC(i);
442        microPC[i] = cpu->readMicroPC(i);
443        fetchStatus[i] = Running;
444    }
445    numInst = 0;
446    wroteToTimeBuffer = false;
447    _status = Inactive;
448    switchedOut = false;
449    interruptPending = false;
450    branchPred.takeOverFrom();
451}
452
453template <class Impl>
454void
455DefaultFetch<Impl>::wakeFromQuiesce()
456{
457    DPRINTF(Fetch, "Waking up from quiesce\n");
458    // Hopefully this is safe
459    // @todo: Allow other threads to wake from quiesce.
460    fetchStatus[0] = Running;
461}
462
463template <class Impl>
464inline void
465DefaultFetch<Impl>::switchToActive()
466{
467    if (_status == Inactive) {
468        DPRINTF(Activity, "Activating stage.\n");
469
470        cpu->activateStage(O3CPU::FetchIdx);
471
472        _status = Active;
473    }
474}
475
476template <class Impl>
477inline void
478DefaultFetch<Impl>::switchToInactive()
479{
480    if (_status == Active) {
481        DPRINTF(Activity, "Deactivating stage.\n");
482
483        cpu->deactivateStage(O3CPU::FetchIdx);
484
485        _status = Inactive;
486    }
487}
488
489template <class Impl>
490bool
491DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC,
492                                          Addr &next_NPC, Addr &next_MicroPC)
493{
494    // Do branch prediction check here.
495    // A bit of a misnomer...next_PC is actually the current PC until
496    // this function updates it.
497    bool predict_taken;
498
499    if (!inst->isControl()) {
500        if (inst->isMicroOp() && !inst->isLastMicroOp()) {
501            next_MicroPC++;
502        } else {
503            next_PC  = next_NPC;
504            next_NPC = next_NPC + instSize;
505            next_MicroPC = 0;
506        }
507        inst->setPredTarg(next_PC, next_NPC, next_MicroPC);
508        inst->setPredTaken(false);
509        return false;
510    }
511
512    //Assume for now that all control flow is to a different macroop which
513    //would reset the micro pc to 0.
514    next_MicroPC = 0;
515
516    int tid = inst->threadNumber;
517    Addr pred_PC = next_PC;
518    predict_taken = branchPred.predict(inst, pred_PC, tid);
519
520/*    if (predict_taken) {
521        DPRINTF(Fetch, "[tid:%i]: Branch predicted to be taken to %#x.\n",
522                tid, pred_PC);
523    } else {
524        DPRINTF(Fetch, "[tid:%i]: Branch predicted to be not taken.\n", tid);
525    }*/
526
527#if ISA_HAS_DELAY_SLOT
528    next_PC = next_NPC;
529    if (predict_taken)
530        next_NPC = pred_PC;
531    else
532        next_NPC += instSize;
533#else
534    if (predict_taken)
535        next_PC = pred_PC;
536    else
537        next_PC += instSize;
538    next_NPC = next_PC + instSize;
539#endif
540/*    DPRINTF(Fetch, "[tid:%i]: Branch predicted to go to %#x and then %#x.\n",
541            tid, next_PC, next_NPC);*/
542    inst->setPredTarg(next_PC, next_NPC, next_MicroPC);
543    inst->setPredTaken(predict_taken);
544
545    ++fetchedBranches;
546
547    if (predict_taken) {
548        ++predictedBranches;
549    }
550
551    return predict_taken;
552}
553
554template <class Impl>
555bool
556DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid)
557{
558    Fault fault = NoFault;
559
560    //AlphaDep
561    if (cacheBlocked) {
562        DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n",
563                tid);
564        return false;
565    } else if (isSwitchedOut()) {
566        DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, switched out\n",
567                tid);
568        return false;
569    } else if (interruptPending && !(fetch_PC & 0x3)) {
570        // Hold off fetch from getting new instructions when:
571        // Cache is blocked, or
572        // while an interrupt is pending and we're not in PAL mode, or
573        // fetch is switched out.
574        DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n",
575                tid);
576        return false;
577    }
578
579    // Align the fetch PC so it's at the start of a cache block.
580    Addr block_PC = icacheBlockAlignPC(fetch_PC);
581
582    // If we've already got the block, no need to try to fetch it again.
583    if (cacheDataValid[tid] && block_PC == cacheDataPC[tid]) {
584        return true;
585    }
586
587    // Setup the memReq to do a read of the first instruction's address.
588    // Set the appropriate read size and flags as well.
589    // Build request here.
590    RequestPtr mem_req = new Request(tid, block_PC, cacheBlkSize, 0,
591                                     fetch_PC, cpu->readCpuId(), tid);
592
593    memReq[tid] = mem_req;
594
595    // Translate the instruction request.
596    fault = cpu->translateInstReq(mem_req, cpu->thread[tid]);
597
598    // In the case of faults, the fetch stage may need to stall and wait
599    // for the ITB miss to be handled.
600
601    // If translation was successful, attempt to read the first
602    // instruction.
603    if (fault == NoFault) {
604#if 0
605        if (cpu->system->memctrl->badaddr(memReq[tid]->paddr) ||
606            memReq[tid]->isUncacheable()) {
607            DPRINTF(Fetch, "Fetch: Bad address %#x (hopefully on a "
608                    "misspeculating path)!",
609                    memReq[tid]->paddr);
610            ret_fault = TheISA::genMachineCheckFault();
611            return false;
612        }
613#endif
614
615        // Build packet here.
616        PacketPtr data_pkt = new Packet(mem_req,
617                                        MemCmd::ReadReq, Packet::Broadcast);
618        data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]);
619
620        cacheDataPC[tid] = block_PC;
621        cacheDataValid[tid] = false;
622
623        DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
624
625        fetchedCacheLines++;
626
627        // Now do the timing access to see whether or not the instruction
628        // exists within the cache.
629        if (!icachePort->sendTiming(data_pkt)) {
630            if (data_pkt->result == Packet::BadAddress) {
631                fault = TheISA::genMachineCheckFault();
632                delete mem_req;
633                memReq[tid] = NULL;
634                warn("Bad address!\n");
635            }
636            assert(retryPkt == NULL);
637            assert(retryTid == -1);
638            DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
639            fetchStatus[tid] = IcacheWaitRetry;
640            retryPkt = data_pkt;
641            retryTid = tid;
642            cacheBlocked = true;
643            return false;
644        }
645
646        DPRINTF(Fetch, "[tid:%i]: Doing cache access.\n", tid);
647
648        lastIcacheStall[tid] = curTick;
649
650        DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
651                "response.\n", tid);
652
653        fetchStatus[tid] = IcacheWaitResponse;
654    } else {
655        delete mem_req;
656        memReq[tid] = NULL;
657    }
658
659    ret_fault = fault;
660    return true;
661}
662
663template <class Impl>
664inline void
665DefaultFetch<Impl>::doSquash(const Addr &new_PC,
666        const Addr &new_NPC, const Addr &new_microPC, unsigned tid)
667{
668    DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x, NPC to: %#x.\n",
669            tid, new_PC, new_NPC);
670
671    PC[tid] = new_PC;
672    nextPC[tid] = new_NPC;
673    microPC[tid] = new_microPC;
674
675    // Clear the icache miss if it's outstanding.
676    if (fetchStatus[tid] == IcacheWaitResponse) {
677        DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
678                tid);
679        memReq[tid] = NULL;
680    }
681
682    // Get rid of the retrying packet if it was from this thread.
683    if (retryTid == tid) {
684        assert(cacheBlocked);
685        if (retryPkt) {
686            delete retryPkt->req;
687            delete retryPkt;
688        }
689        retryPkt = NULL;
690        retryTid = -1;
691    }
692
693    fetchStatus[tid] = Squashing;
694
695    ++fetchSquashCycles;
696}
697
698template<class Impl>
699void
700DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC, const Addr &new_NPC,
701                                     const Addr &new_MicroPC,
702                                     const InstSeqNum &seq_num, unsigned tid)
703{
704    DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid);
705
706    doSquash(new_PC, new_NPC, new_MicroPC, tid);
707
708    // Tell the CPU to remove any instructions that are in flight between
709    // fetch and decode.
710    cpu->removeInstsUntil(seq_num, tid);
711}
712
713template<class Impl>
714bool
715DefaultFetch<Impl>::checkStall(unsigned tid) const
716{
717    bool ret_val = false;
718
719    if (cpu->contextSwitch) {
720        DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid);
721        ret_val = true;
722    } else if (stalls[tid].decode) {
723        DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid);
724        ret_val = true;
725    } else if (stalls[tid].rename) {
726        DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid);
727        ret_val = true;
728    } else if (stalls[tid].iew) {
729        DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid);
730        ret_val = true;
731    } else if (stalls[tid].commit) {
732        DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid);
733        ret_val = true;
734    }
735
736    return ret_val;
737}
738
739template<class Impl>
740typename DefaultFetch<Impl>::FetchStatus
741DefaultFetch<Impl>::updateFetchStatus()
742{
743    //Check Running
744    std::list<unsigned>::iterator threads = activeThreads->begin();
745    std::list<unsigned>::iterator end = activeThreads->end();
746
747    while (threads != end) {
748        unsigned tid = *threads++;
749
750        if (fetchStatus[tid] == Running ||
751            fetchStatus[tid] == Squashing ||
752            fetchStatus[tid] == IcacheAccessComplete) {
753
754            if (_status == Inactive) {
755                DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid);
756
757                if (fetchStatus[tid] == IcacheAccessComplete) {
758                    DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache"
759                            "completion\n",tid);
760                }
761
762                cpu->activateStage(O3CPU::FetchIdx);
763            }
764
765            return Active;
766        }
767    }
768
769    // Stage is switching from active to inactive, notify CPU of it.
770    if (_status == Active) {
771        DPRINTF(Activity, "Deactivating stage.\n");
772
773        cpu->deactivateStage(O3CPU::FetchIdx);
774    }
775
776    return Inactive;
777}
778
779template <class Impl>
780void
781DefaultFetch<Impl>::squash(const Addr &new_PC, const Addr &new_NPC,
782                           const Addr &new_MicroPC,
783                           const InstSeqNum &seq_num, unsigned tid)
784{
785    DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid);
786
787    doSquash(new_PC, new_NPC, new_MicroPC, tid);
788
789    // Tell the CPU to remove any instructions that are not in the ROB.
790    cpu->removeInstsNotInROB(tid);
791}
792
793template <class Impl>
794void
795DefaultFetch<Impl>::tick()
796{
797    std::list<unsigned>::iterator threads = activeThreads->begin();
798    std::list<unsigned>::iterator end = activeThreads->end();
799    bool status_change = false;
800
801    wroteToTimeBuffer = false;
802
803    while (threads != end) {
804        unsigned tid = *threads++;
805
806        // Check the signals for each thread to determine the proper status
807        // for each thread.
808        bool updated_status = checkSignalsAndUpdate(tid);
809        status_change =  status_change || updated_status;
810    }
811
812    DPRINTF(Fetch, "Running stage.\n");
813
814    // Reset the number of the instruction we're fetching.
815    numInst = 0;
816
817#if FULL_SYSTEM
818    if (fromCommit->commitInfo[0].interruptPending) {
819        interruptPending = true;
820    }
821
822    if (fromCommit->commitInfo[0].clearInterrupt) {
823        interruptPending = false;
824    }
825#endif
826
827    for (threadFetched = 0; threadFetched < numFetchingThreads;
828         threadFetched++) {
829        // Fetch each of the actively fetching threads.
830        fetch(status_change);
831    }
832
833    // Record number of instructions fetched this cycle for distribution.
834    fetchNisnDist.sample(numInst);
835
836    if (status_change) {
837        // Change the fetch stage status if there was a status change.
838        _status = updateFetchStatus();
839    }
840
841    // If there was activity this cycle, inform the CPU of it.
842    if (wroteToTimeBuffer || cpu->contextSwitch) {
843        DPRINTF(Activity, "Activity this cycle.\n");
844
845        cpu->activityThisCycle();
846    }
847}
848
849template <class Impl>
850bool
851DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid)
852{
853    // Update the per thread stall statuses.
854    if (fromDecode->decodeBlock[tid]) {
855        stalls[tid].decode = true;
856    }
857
858    if (fromDecode->decodeUnblock[tid]) {
859        assert(stalls[tid].decode);
860        assert(!fromDecode->decodeBlock[tid]);
861        stalls[tid].decode = false;
862    }
863
864    if (fromRename->renameBlock[tid]) {
865        stalls[tid].rename = true;
866    }
867
868    if (fromRename->renameUnblock[tid]) {
869        assert(stalls[tid].rename);
870        assert(!fromRename->renameBlock[tid]);
871        stalls[tid].rename = false;
872    }
873
874    if (fromIEW->iewBlock[tid]) {
875        stalls[tid].iew = true;
876    }
877
878    if (fromIEW->iewUnblock[tid]) {
879        assert(stalls[tid].iew);
880        assert(!fromIEW->iewBlock[tid]);
881        stalls[tid].iew = false;
882    }
883
884    if (fromCommit->commitBlock[tid]) {
885        stalls[tid].commit = true;
886    }
887
888    if (fromCommit->commitUnblock[tid]) {
889        assert(stalls[tid].commit);
890        assert(!fromCommit->commitBlock[tid]);
891        stalls[tid].commit = false;
892    }
893
894    // Check squash signals from commit.
895    if (fromCommit->commitInfo[tid].squash) {
896
897        DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
898                "from commit.\n",tid);
899        // In any case, squash.
900        squash(fromCommit->commitInfo[tid].nextPC,
901               fromCommit->commitInfo[tid].nextNPC,
902               fromCommit->commitInfo[tid].nextMicroPC,
903               fromCommit->commitInfo[tid].doneSeqNum,
904               tid);
905
906        // Also check if there's a mispredict that happened.
907        if (fromCommit->commitInfo[tid].branchMispredict) {
908            branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
909                              fromCommit->commitInfo[tid].nextPC,
910                              fromCommit->commitInfo[tid].branchTaken,
911                              tid);
912        } else {
913            branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
914                              tid);
915        }
916
917        return true;
918    } else if (fromCommit->commitInfo[tid].doneSeqNum) {
919        // Update the branch predictor if it wasn't a squashed instruction
920        // that was broadcasted.
921        branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid);
922    }
923
924    // Check ROB squash signals from commit.
925    if (fromCommit->commitInfo[tid].robSquashing) {
926        DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid);
927
928        // Continue to squash.
929        fetchStatus[tid] = Squashing;
930
931        return true;
932    }
933
934    // Check squash signals from decode.
935    if (fromDecode->decodeInfo[tid].squash) {
936        DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
937                "from decode.\n",tid);
938
939        // Update the branch predictor.
940        if (fromDecode->decodeInfo[tid].branchMispredict) {
941            branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
942                              fromDecode->decodeInfo[tid].nextPC,
943                              fromDecode->decodeInfo[tid].branchTaken,
944                              tid);
945        } else {
946            branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
947                              tid);
948        }
949
950        if (fetchStatus[tid] != Squashing) {
951
952            DPRINTF(Fetch, "Squashing from decode with PC = %#x, NPC = %#x\n",
953                    fromDecode->decodeInfo[tid].nextPC,
954                    fromDecode->decodeInfo[tid].nextNPC);
955            // Squash unless we're already squashing
956            squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
957                             fromDecode->decodeInfo[tid].nextNPC,
958                             fromDecode->decodeInfo[tid].nextMicroPC,
959                             fromDecode->decodeInfo[tid].doneSeqNum,
960                             tid);
961
962            return true;
963        }
964    }
965
966    if (checkStall(tid) &&
967        fetchStatus[tid] != IcacheWaitResponse &&
968        fetchStatus[tid] != IcacheWaitRetry) {
969        DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid);
970
971        fetchStatus[tid] = Blocked;
972
973        return true;
974    }
975
976    if (fetchStatus[tid] == Blocked ||
977        fetchStatus[tid] == Squashing) {
978        // Switch status to running if fetch isn't being told to block or
979        // squash this cycle.
980        DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n",
981                tid);
982
983        fetchStatus[tid] = Running;
984
985        return true;
986    }
987
988    // If we've reached this point, we have not gotten any signals that
989    // cause fetch to change its status.  Fetch remains the same as before.
990    return false;
991}
992
993template<class Impl>
994void
995DefaultFetch<Impl>::fetch(bool &status_change)
996{
997    //////////////////////////////////////////
998    // Start actual fetch
999    //////////////////////////////////////////
1000    int tid = getFetchingThread(fetchPolicy);
1001
1002    if (tid == -1 || drainPending) {
1003        DPRINTF(Fetch,"There are no more threads available to fetch from.\n");
1004
1005        // Breaks looping condition in tick()
1006        threadFetched = numFetchingThreads;
1007        return;
1008    }
1009
1010    DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
1011
1012    // The current PC.
1013    Addr fetch_PC = PC[tid];
1014    Addr fetch_NPC = nextPC[tid];
1015    Addr fetch_MicroPC = microPC[tid];
1016
1017    // Fault code for memory access.
1018    Fault fault = NoFault;
1019
1020    // If returning from the delay of a cache miss, then update the status
1021    // to running, otherwise do the cache access.  Possibly move this up
1022    // to tick() function.
1023    if (fetchStatus[tid] == IcacheAccessComplete) {
1024        DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n",
1025                tid);
1026
1027        fetchStatus[tid] = Running;
1028        status_change = true;
1029    } else if (fetchStatus[tid] == Running) {
1030        DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
1031                "instruction, starting at PC %08p.\n",
1032                tid, fetch_PC);
1033
1034        bool fetch_success = fetchCacheLine(fetch_PC, fault, tid);
1035        if (!fetch_success) {
1036            if (cacheBlocked) {
1037                ++icacheStallCycles;
1038            } else {
1039                ++fetchMiscStallCycles;
1040            }
1041            return;
1042        }
1043    } else {
1044        if (fetchStatus[tid] == Idle) {
1045            ++fetchIdleCycles;
1046            DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid);
1047        } else if (fetchStatus[tid] == Blocked) {
1048            ++fetchBlockedCycles;
1049            DPRINTF(Fetch, "[tid:%i]: Fetch is blocked!\n", tid);
1050        } else if (fetchStatus[tid] == Squashing) {
1051            ++fetchSquashCycles;
1052            DPRINTF(Fetch, "[tid:%i]: Fetch is squashing!\n", tid);
1053        } else if (fetchStatus[tid] == IcacheWaitResponse) {
1054            ++icacheStallCycles;
1055            DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n", tid);
1056        }
1057
1058        // Status is Idle, Squashing, Blocked, or IcacheWaitResponse, so
1059        // fetch should do nothing.
1060        return;
1061    }
1062
1063    ++fetchCycles;
1064
1065    // If we had a stall due to an icache miss, then return.
1066    if (fetchStatus[tid] == IcacheWaitResponse) {
1067        ++icacheStallCycles;
1068        status_change = true;
1069        return;
1070    }
1071
1072    Addr next_PC = fetch_PC;
1073    Addr next_NPC = fetch_NPC;
1074    Addr next_MicroPC = fetch_MicroPC;
1075
1076    InstSeqNum inst_seq;
1077    MachInst inst;
1078    ExtMachInst ext_inst;
1079    // @todo: Fix this hack.
1080    unsigned offset = (fetch_PC & cacheBlkMask) & ~3;
1081
1082    StaticInstPtr staticInst = NULL;
1083    StaticInstPtr macroop = NULL;
1084
1085    if (fault == NoFault) {
1086        // If the read of the first instruction was successful, then grab the
1087        // instructions from the rest of the cache line and put them into the
1088        // queue heading to decode.
1089
1090        DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
1091                "decode.\n",tid);
1092
1093        // Need to keep track of whether or not a predicted branch
1094        // ended this fetch block.
1095        bool predicted_branch = false;
1096
1097        for (;
1098             offset < cacheBlkSize &&
1099                 numInst < fetchWidth &&
1100                 !predicted_branch;
1101             ++numInst) {
1102
1103            // If we're branching after this instruction, quite fetching
1104            // from the same block then.
1105            predicted_branch =
1106                (fetch_PC + sizeof(TheISA::MachInst) != fetch_NPC);
1107            if (predicted_branch) {
1108                DPRINTF(Fetch, "Branch detected with PC = %#x, NPC = %#x\n",
1109                        fetch_PC, fetch_NPC);
1110            }
1111
1112
1113            // Get a sequence number.
1114            inst_seq = cpu->getAndIncrementInstSeq();
1115
1116            // Make sure this is a valid index.
1117            assert(offset <= cacheBlkSize - instSize);
1118
1119            if (!macroop) {
1120                // Get the instruction from the array of the cache line.
1121                inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
1122                            (&cacheData[tid][offset]));
1123
1124                predecoder.setTC(cpu->thread[tid]->getTC());
1125                predecoder.moreBytes(fetch_PC, 0, inst);
1126
1127                ext_inst = predecoder.getExtMachInst();
1128                staticInst = StaticInstPtr(ext_inst);
1129                if (staticInst->isMacroOp())
1130                    macroop = staticInst;
1131            }
1132            if (macroop) {
1133                staticInst = macroop->fetchMicroOp(fetch_MicroPC);
1134                if (staticInst->isLastMicroOp())
1135                    macroop = NULL;
1136            }
1137
1138            // Create a new DynInst from the instruction fetched.
1139            DynInstPtr instruction = new DynInst(staticInst,
1140                                                 fetch_PC, fetch_NPC, fetch_MicroPC,
1141                                                 next_PC, next_NPC, next_MicroPC,
1142                                                 inst_seq, cpu);
1143            instruction->setTid(tid);
1144
1145            instruction->setASID(tid);
1146
1147            instruction->setThreadState(cpu->thread[tid]);
1148
1149            DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created "
1150                    "[sn:%lli]\n",
1151                    tid, instruction->readPC(), inst_seq);
1152
1153            //DPRINTF(Fetch, "[tid:%i]: MachInst is %#x\n", tid, ext_inst);
1154
1155            DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n",
1156                    tid, instruction->staticInst->disassemble(fetch_PC));
1157
1158            instruction->traceData =
1159                Trace::getInstRecord(curTick, cpu->tcBase(tid),
1160                                     instruction->staticInst,
1161                                     instruction->readPC());
1162
1163            ///FIXME This needs to be more robust in dealing with delay slots
1164            lookupAndUpdateNextPC(instruction, next_PC, next_NPC, next_MicroPC);
1165            predicted_branch |= (next_PC != fetch_NPC);
1166
1167            // Add instruction to the CPU's list of instructions.
1168            instruction->setInstListIt(cpu->addInst(instruction));
1169
1170            // Write the instruction to the first slot in the queue
1171            // that heads to decode.
1172            toDecode->insts[numInst] = instruction;
1173
1174            toDecode->size++;
1175
1176            // Increment stat of fetched instructions.
1177            ++fetchedInsts;
1178
1179            // Move to the next instruction, unless we have a branch.
1180            fetch_PC = next_PC;
1181            fetch_NPC = next_NPC;
1182            fetch_MicroPC = next_MicroPC;
1183
1184            if (instruction->isQuiesce()) {
1185                DPRINTF(Fetch, "Quiesce instruction encountered, halting fetch!",
1186                        curTick);
1187                fetchStatus[tid] = QuiescePending;
1188                ++numInst;
1189                status_change = true;
1190                break;
1191            }
1192
1193            if (!macroop)
1194                offset += instSize;
1195        }
1196
1197        if (offset >= cacheBlkSize) {
1198            DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache "
1199                    "block.\n", tid);
1200        } else if (numInst >= fetchWidth) {
1201            DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth "
1202                    "for this cycle.\n", tid);
1203        } else if (predicted_branch) {
1204            DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch "
1205                    "instruction encountered.\n", tid);
1206        }
1207    }
1208
1209    if (numInst > 0) {
1210        wroteToTimeBuffer = true;
1211    }
1212
1213    // Now that fetching is completed, update the PC to signify what the next
1214    // cycle will be.
1215    if (fault == NoFault) {
1216        PC[tid] = next_PC;
1217        nextPC[tid] = next_NPC;
1218        microPC[tid] = next_MicroPC;
1219        DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, next_PC);
1220    } else {
1221        // We shouldn't be in an icache miss and also have a fault (an ITB
1222        // miss)
1223        if (fetchStatus[tid] == IcacheWaitResponse) {
1224            panic("Fetch should have exited prior to this!");
1225        }
1226
1227        // Send the fault to commit.  This thread will not do anything
1228        // until commit handles the fault.  The only other way it can
1229        // wake up is if a squash comes along and changes the PC.
1230#if FULL_SYSTEM
1231        assert(numInst < fetchWidth);
1232        // Get a sequence number.
1233        inst_seq = cpu->getAndIncrementInstSeq();
1234        // We will use a nop in order to carry the fault.
1235        ext_inst = TheISA::NoopMachInst;
1236
1237        StaticInstPtr staticInst = new StaticInst(ext_inst);
1238        // Create a new DynInst from the dummy nop.
1239        DynInstPtr instruction = new DynInst(staticInst,
1240                                             fetch_PC, fetch_NPC,
1241                                             next_PC, next_NPC,
1242                                             inst_seq, cpu);
1243        instruction->setPredTarg(next_PC, next_NPC);
1244        instruction->setTid(tid);
1245
1246        instruction->setASID(tid);
1247
1248        instruction->setThreadState(cpu->thread[tid]);
1249
1250        instruction->traceData = NULL;
1251
1252        instruction->setInstListIt(cpu->addInst(instruction));
1253
1254        instruction->fault = fault;
1255
1256        toDecode->insts[numInst] = instruction;
1257        toDecode->size++;
1258
1259        DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid);
1260
1261        fetchStatus[tid] = TrapPending;
1262        status_change = true;
1263#else // !FULL_SYSTEM
1264        fetchStatus[tid] = TrapPending;
1265        status_change = true;
1266
1267#endif // FULL_SYSTEM
1268        DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %08p",
1269                tid, fault->name(), PC[tid]);
1270    }
1271}
1272
1273template<class Impl>
1274void
1275DefaultFetch<Impl>::recvRetry()
1276{
1277    if (retryPkt != NULL) {
1278        assert(cacheBlocked);
1279        assert(retryTid != -1);
1280        assert(fetchStatus[retryTid] == IcacheWaitRetry);
1281
1282        if (icachePort->sendTiming(retryPkt)) {
1283            fetchStatus[retryTid] = IcacheWaitResponse;
1284            retryPkt = NULL;
1285            retryTid = -1;
1286            cacheBlocked = false;
1287        }
1288    } else {
1289        assert(retryTid == -1);
1290        // Access has been squashed since it was sent out.  Just clear
1291        // the cache being blocked.
1292        cacheBlocked = false;
1293    }
1294}
1295
1296///////////////////////////////////////
1297//                                   //
1298//  SMT FETCH POLICY MAINTAINED HERE //
1299//                                   //
1300///////////////////////////////////////
1301template<class Impl>
1302int
1303DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority)
1304{
1305    if (numThreads > 1) {
1306        switch (fetch_priority) {
1307
1308          case SingleThread:
1309            return 0;
1310
1311          case RoundRobin:
1312            return roundRobin();
1313
1314          case IQ:
1315            return iqCount();
1316
1317          case LSQ:
1318            return lsqCount();
1319
1320          case Branch:
1321            return branchCount();
1322
1323          default:
1324            return -1;
1325        }
1326    } else {
1327        std::list<unsigned>::iterator thread = activeThreads->begin();
1328        assert(thread != activeThreads->end());
1329        int tid = *thread;
1330
1331        if (fetchStatus[tid] == Running ||
1332            fetchStatus[tid] == IcacheAccessComplete ||
1333            fetchStatus[tid] == Idle) {
1334            return tid;
1335        } else {
1336            return -1;
1337        }
1338    }
1339
1340}
1341
1342
1343template<class Impl>
1344int
1345DefaultFetch<Impl>::roundRobin()
1346{
1347    std::list<unsigned>::iterator pri_iter = priorityList.begin();
1348    std::list<unsigned>::iterator end      = priorityList.end();
1349
1350    int high_pri;
1351
1352    while (pri_iter != end) {
1353        high_pri = *pri_iter;
1354
1355        assert(high_pri <= numThreads);
1356
1357        if (fetchStatus[high_pri] == Running ||
1358            fetchStatus[high_pri] == IcacheAccessComplete ||
1359            fetchStatus[high_pri] == Idle) {
1360
1361            priorityList.erase(pri_iter);
1362            priorityList.push_back(high_pri);
1363
1364            return high_pri;
1365        }
1366
1367        pri_iter++;
1368    }
1369
1370    return -1;
1371}
1372
1373template<class Impl>
1374int
1375DefaultFetch<Impl>::iqCount()
1376{
1377    std::priority_queue<unsigned> PQ;
1378
1379    std::list<unsigned>::iterator threads = activeThreads->begin();
1380    std::list<unsigned>::iterator end = activeThreads->end();
1381
1382    while (threads != end) {
1383        unsigned tid = *threads++;
1384
1385        PQ.push(fromIEW->iewInfo[tid].iqCount);
1386    }
1387
1388    while (!PQ.empty()) {
1389
1390        unsigned high_pri = PQ.top();
1391
1392        if (fetchStatus[high_pri] == Running ||
1393            fetchStatus[high_pri] == IcacheAccessComplete ||
1394            fetchStatus[high_pri] == Idle)
1395            return high_pri;
1396        else
1397            PQ.pop();
1398
1399    }
1400
1401    return -1;
1402}
1403
1404template<class Impl>
1405int
1406DefaultFetch<Impl>::lsqCount()
1407{
1408    std::priority_queue<unsigned> PQ;
1409
1410    std::list<unsigned>::iterator threads = activeThreads->begin();
1411    std::list<unsigned>::iterator end = activeThreads->end();
1412
1413    while (threads != end) {
1414        unsigned tid = *threads++;
1415
1416        PQ.push(fromIEW->iewInfo[tid].ldstqCount);
1417    }
1418
1419    while (!PQ.empty()) {
1420
1421        unsigned high_pri = PQ.top();
1422
1423        if (fetchStatus[high_pri] == Running ||
1424            fetchStatus[high_pri] == IcacheAccessComplete ||
1425            fetchStatus[high_pri] == Idle)
1426            return high_pri;
1427        else
1428            PQ.pop();
1429
1430    }
1431
1432    return -1;
1433}
1434
1435template<class Impl>
1436int
1437DefaultFetch<Impl>::branchCount()
1438{
1439    std::list<unsigned>::iterator thread = activeThreads->begin();
1440    assert(thread != activeThreads->end());
1441    unsigned tid = *thread;
1442
1443    panic("Branch Count Fetch policy unimplemented\n");
1444    return 0 * tid;
1445}
1446