fetch_impl.hh revision 3984:8f1bb70a4abf
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#include "config/use_checker.hh" 33 34#include "arch/isa_traits.hh" 35#include "arch/utility.hh" 36#include "cpu/checker/cpu.hh" 37#include "cpu/exetrace.hh" 38#include "cpu/o3/fetch.hh" 39#include "mem/packet.hh" 40#include "mem/request.hh" 41#include "sim/byteswap.hh" 42#include "sim/host.hh" 43#include "sim/root.hh" 44 45#if FULL_SYSTEM 46#include "arch/tlb.hh" 47#include "arch/vtophys.hh" 48#include "sim/system.hh" 49#endif // FULL_SYSTEM 50 51#include <algorithm> 52 53template<class Impl> 54Tick 55DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt) 56{ 57 panic("DefaultFetch doesn't expect recvAtomic callback!"); 58 return curTick; 59} 60 61template<class Impl> 62void 63DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt) 64{ 65 DPRINTF(Fetch, "DefaultFetch doesn't update its state from a " 66 "functional call."); 67} 68 69template<class Impl> 70void 71DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status) 72{ 73 if (status == RangeChange) { 74 if (!snoopRangeSent) { 75 snoopRangeSent = true; 76 sendStatusChange(Port::RangeChange); 77 } 78 return; 79 } 80 81 panic("DefaultFetch doesn't expect recvStatusChange callback!"); 82} 83 84template<class Impl> 85bool 86DefaultFetch<Impl>::IcachePort::recvTiming(PacketPtr pkt) 87{ 88 DPRINTF(Fetch, "Received timing\n"); 89 if (pkt->isResponse()) { 90 fetch->processCacheCompletion(pkt); 91 } 92 //else Snooped a coherence request, just return 93 return true; 94} 95 96template<class Impl> 97void 98DefaultFetch<Impl>::IcachePort::recvRetry() 99{ 100 fetch->recvRetry(); 101} 102 103template<class Impl> 104DefaultFetch<Impl>::DefaultFetch(Params *params) 105 : branchPred(params), 106 decodeToFetchDelay(params->decodeToFetchDelay), 107 renameToFetchDelay(params->renameToFetchDelay), 108 iewToFetchDelay(params->iewToFetchDelay), 109 commitToFetchDelay(params->commitToFetchDelay), 110 fetchWidth(params->fetchWidth), 111 cacheBlocked(false), 112 retryPkt(NULL), 113 retryTid(-1), 114 numThreads(params->numberOfThreads), 115 numFetchingThreads(params->smtNumFetchingThreads), 116 interruptPending(false), 117 drainPending(false), 118 switchedOut(false) 119{ 120 if (numThreads > Impl::MaxThreads) 121 fatal("numThreads is not a valid value\n"); 122 123 // Set fetch stage's status to inactive. 124 _status = Inactive; 125 126 std::string policy = params->smtFetchPolicy; 127 128 // Convert string to lowercase 129 std::transform(policy.begin(), policy.end(), policy.begin(), 130 (int(*)(int)) tolower); 131 132 // Figure out fetch policy 133 if (policy == "singlethread") { 134 fetchPolicy = SingleThread; 135 if (numThreads > 1) 136 panic("Invalid Fetch Policy for a SMT workload."); 137 } else if (policy == "roundrobin") { 138 fetchPolicy = RoundRobin; 139 DPRINTF(Fetch, "Fetch policy set to Round Robin\n"); 140 } else if (policy == "branch") { 141 fetchPolicy = Branch; 142 DPRINTF(Fetch, "Fetch policy set to Branch Count\n"); 143 } else if (policy == "iqcount") { 144 fetchPolicy = IQ; 145 DPRINTF(Fetch, "Fetch policy set to IQ count\n"); 146 } else if (policy == "lsqcount") { 147 fetchPolicy = LSQ; 148 DPRINTF(Fetch, "Fetch policy set to LSQ count\n"); 149 } else { 150 fatal("Invalid Fetch Policy. Options Are: {SingleThread," 151 " RoundRobin,LSQcount,IQcount}\n"); 152 } 153 154 // Get the size of an instruction. 155 instSize = sizeof(TheISA::MachInst); 156} 157 158template <class Impl> 159std::string 160DefaultFetch<Impl>::name() const 161{ 162 return cpu->name() + ".fetch"; 163} 164 165template <class Impl> 166void 167DefaultFetch<Impl>::regStats() 168{ 169 icacheStallCycles 170 .name(name() + ".icacheStallCycles") 171 .desc("Number of cycles fetch is stalled on an Icache miss") 172 .prereq(icacheStallCycles); 173 174 fetchedInsts 175 .name(name() + ".Insts") 176 .desc("Number of instructions fetch has processed") 177 .prereq(fetchedInsts); 178 179 fetchedBranches 180 .name(name() + ".Branches") 181 .desc("Number of branches that fetch encountered") 182 .prereq(fetchedBranches); 183 184 predictedBranches 185 .name(name() + ".predictedBranches") 186 .desc("Number of branches that fetch has predicted taken") 187 .prereq(predictedBranches); 188 189 fetchCycles 190 .name(name() + ".Cycles") 191 .desc("Number of cycles fetch has run and was not squashing or" 192 " blocked") 193 .prereq(fetchCycles); 194 195 fetchSquashCycles 196 .name(name() + ".SquashCycles") 197 .desc("Number of cycles fetch has spent squashing") 198 .prereq(fetchSquashCycles); 199 200 fetchIdleCycles 201 .name(name() + ".IdleCycles") 202 .desc("Number of cycles fetch was idle") 203 .prereq(fetchIdleCycles); 204 205 fetchBlockedCycles 206 .name(name() + ".BlockedCycles") 207 .desc("Number of cycles fetch has spent blocked") 208 .prereq(fetchBlockedCycles); 209 210 fetchedCacheLines 211 .name(name() + ".CacheLines") 212 .desc("Number of cache lines fetched") 213 .prereq(fetchedCacheLines); 214 215 fetchMiscStallCycles 216 .name(name() + ".MiscStallCycles") 217 .desc("Number of cycles fetch has spent waiting on interrupts, or " 218 "bad addresses, or out of MSHRs") 219 .prereq(fetchMiscStallCycles); 220 221 fetchIcacheSquashes 222 .name(name() + ".IcacheSquashes") 223 .desc("Number of outstanding Icache misses that were squashed") 224 .prereq(fetchIcacheSquashes); 225 226 fetchNisnDist 227 .init(/* base value */ 0, 228 /* last value */ fetchWidth, 229 /* bucket size */ 1) 230 .name(name() + ".rateDist") 231 .desc("Number of instructions fetched each cycle (Total)") 232 .flags(Stats::pdf); 233 234 idleRate 235 .name(name() + ".idleRate") 236 .desc("Percent of cycles fetch was idle") 237 .prereq(idleRate); 238 idleRate = fetchIdleCycles * 100 / cpu->numCycles; 239 240 branchRate 241 .name(name() + ".branchRate") 242 .desc("Number of branch fetches per cycle") 243 .flags(Stats::total); 244 branchRate = fetchedBranches / cpu->numCycles; 245 246 fetchRate 247 .name(name() + ".rate") 248 .desc("Number of inst fetches per cycle") 249 .flags(Stats::total); 250 fetchRate = fetchedInsts / cpu->numCycles; 251 252 branchPred.regStats(); 253} 254 255template<class Impl> 256void 257DefaultFetch<Impl>::setCPU(O3CPU *cpu_ptr) 258{ 259 DPRINTF(Fetch, "Setting the CPU pointer.\n"); 260 cpu = cpu_ptr; 261 262 // Name is finally available, so create the port. 263 icachePort = new IcachePort(this); 264 265 icachePort->snoopRangeSent = false; 266 267#if USE_CHECKER 268 if (cpu->checker) { 269 cpu->checker->setIcachePort(icachePort); 270 } 271#endif 272 273 // Schedule fetch to get the correct PC from the CPU 274 // scheduleFetchStartupEvent(1); 275 276 // Fetch needs to start fetching instructions at the very beginning, 277 // so it must start up in active state. 278 switchToActive(); 279} 280 281template<class Impl> 282void 283DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer) 284{ 285 DPRINTF(Fetch, "Setting the time buffer pointer.\n"); 286 timeBuffer = time_buffer; 287 288 // Create wires to get information from proper places in time buffer. 289 fromDecode = timeBuffer->getWire(-decodeToFetchDelay); 290 fromRename = timeBuffer->getWire(-renameToFetchDelay); 291 fromIEW = timeBuffer->getWire(-iewToFetchDelay); 292 fromCommit = timeBuffer->getWire(-commitToFetchDelay); 293} 294 295template<class Impl> 296void 297DefaultFetch<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) 298{ 299 DPRINTF(Fetch, "Setting active threads list pointer.\n"); 300 activeThreads = at_ptr; 301} 302 303template<class Impl> 304void 305DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 306{ 307 DPRINTF(Fetch, "Setting the fetch queue pointer.\n"); 308 fetchQueue = fq_ptr; 309 310 // Create wire to write information to proper place in fetch queue. 311 toDecode = fetchQueue->getWire(0); 312} 313 314template<class Impl> 315void 316DefaultFetch<Impl>::initStage() 317{ 318 // Setup PC and nextPC with initial state. 319 for (int tid = 0; tid < numThreads; tid++) { 320 PC[tid] = cpu->readPC(tid); 321 nextPC[tid] = cpu->readNextPC(tid); 322 nextNPC[tid] = cpu->readNextNPC(tid); 323 } 324 325 // Size of cache block. 326 cacheBlkSize = icachePort->peerBlockSize(); 327 328 // Create mask to get rid of offset bits. 329 cacheBlkMask = (cacheBlkSize - 1); 330 331 for (int tid=0; tid < numThreads; tid++) { 332 333 fetchStatus[tid] = Running; 334 335 priorityList.push_back(tid); 336 337 memReq[tid] = NULL; 338 339 // Create space to store a cache line. 340 cacheData[tid] = new uint8_t[cacheBlkSize]; 341 cacheDataPC[tid] = 0; 342 cacheDataValid[tid] = false; 343 344 stalls[tid].decode = false; 345 stalls[tid].rename = false; 346 stalls[tid].iew = false; 347 stalls[tid].commit = false; 348 } 349} 350 351template<class Impl> 352void 353DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt) 354{ 355 unsigned tid = pkt->req->getThreadNum(); 356 357 DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid); 358 359 // Only change the status if it's still waiting on the icache access 360 // to return. 361 if (fetchStatus[tid] != IcacheWaitResponse || 362 pkt->req != memReq[tid] || 363 isSwitchedOut()) { 364 ++fetchIcacheSquashes; 365 delete pkt->req; 366 delete pkt; 367 return; 368 } 369 370 memcpy(cacheData[tid], pkt->getPtr<uint8_t *>(), cacheBlkSize); 371 cacheDataValid[tid] = true; 372 373 if (!drainPending) { 374 // Wake up the CPU (if it went to sleep and was waiting on 375 // this completion event). 376 cpu->wakeCPU(); 377 378 DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n", 379 tid); 380 381 switchToActive(); 382 } 383 384 // Only switch to IcacheAccessComplete if we're not stalled as well. 385 if (checkStall(tid)) { 386 fetchStatus[tid] = Blocked; 387 } else { 388 fetchStatus[tid] = IcacheAccessComplete; 389 } 390 391 // Reset the mem req to NULL. 392 delete pkt->req; 393 delete pkt; 394 memReq[tid] = NULL; 395} 396 397template <class Impl> 398bool 399DefaultFetch<Impl>::drain() 400{ 401 // Fetch is ready to drain at any time. 402 cpu->signalDrained(); 403 drainPending = true; 404 return true; 405} 406 407template <class Impl> 408void 409DefaultFetch<Impl>::resume() 410{ 411 drainPending = false; 412} 413 414template <class Impl> 415void 416DefaultFetch<Impl>::switchOut() 417{ 418 switchedOut = true; 419 // Branch predictor needs to have its state cleared. 420 branchPred.switchOut(); 421} 422 423template <class Impl> 424void 425DefaultFetch<Impl>::takeOverFrom() 426{ 427 // Reset all state 428 for (int i = 0; i < Impl::MaxThreads; ++i) { 429 stalls[i].decode = 0; 430 stalls[i].rename = 0; 431 stalls[i].iew = 0; 432 stalls[i].commit = 0; 433 PC[i] = cpu->readPC(i); 434 nextPC[i] = cpu->readNextPC(i); 435#if ISA_HAS_DELAY_SLOT 436 nextNPC[i] = cpu->readNextNPC(i); 437#else 438 nextNPC[i] = nextPC[i] + sizeof(TheISA::MachInst); 439#endif 440 fetchStatus[i] = Running; 441 } 442 numInst = 0; 443 wroteToTimeBuffer = false; 444 _status = Inactive; 445 switchedOut = false; 446 interruptPending = false; 447 branchPred.takeOverFrom(); 448} 449 450template <class Impl> 451void 452DefaultFetch<Impl>::wakeFromQuiesce() 453{ 454 DPRINTF(Fetch, "Waking up from quiesce\n"); 455 // Hopefully this is safe 456 // @todo: Allow other threads to wake from quiesce. 457 fetchStatus[0] = Running; 458} 459 460template <class Impl> 461inline void 462DefaultFetch<Impl>::switchToActive() 463{ 464 if (_status == Inactive) { 465 DPRINTF(Activity, "Activating stage.\n"); 466 467 cpu->activateStage(O3CPU::FetchIdx); 468 469 _status = Active; 470 } 471} 472 473template <class Impl> 474inline void 475DefaultFetch<Impl>::switchToInactive() 476{ 477 if (_status == Active) { 478 DPRINTF(Activity, "Deactivating stage.\n"); 479 480 cpu->deactivateStage(O3CPU::FetchIdx); 481 482 _status = Inactive; 483 } 484} 485 486template <class Impl> 487bool 488DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC, 489 Addr &next_NPC) 490{ 491 // Do branch prediction check here. 492 // A bit of a misnomer...next_PC is actually the current PC until 493 // this function updates it. 494 bool predict_taken; 495 496 if (!inst->isControl()) { 497 next_PC = next_NPC; 498 next_NPC = next_NPC + instSize; 499 inst->setPredTarg(next_PC, next_NPC); 500 inst->setPredTaken(false); 501 return false; 502 } 503 504 int tid = inst->threadNumber; 505 Addr pred_PC = next_PC; 506 predict_taken = branchPred.predict(inst, pred_PC, tid); 507 508/* if (predict_taken) { 509 DPRINTF(Fetch, "[tid:%i]: Branch predicted to be taken to %#x.\n", 510 tid, pred_PC); 511 } else { 512 DPRINTF(Fetch, "[tid:%i]: Branch predicted to be not taken.\n", tid); 513 }*/ 514 515#if ISA_HAS_DELAY_SLOT 516 next_PC = next_NPC; 517 if (predict_taken) 518 next_NPC = pred_PC; 519 else 520 next_NPC += instSize; 521#else 522 if (predict_taken) 523 next_PC = pred_PC; 524 else 525 next_PC += instSize; 526 next_NPC = next_PC + instSize; 527#endif 528/* DPRINTF(Fetch, "[tid:%i]: Branch predicted to go to %#x and then %#x.\n", 529 tid, next_PC, next_NPC);*/ 530 inst->setPredTarg(next_PC, next_NPC); 531 inst->setPredTaken(predict_taken); 532 533 ++fetchedBranches; 534 535 if (predict_taken) { 536 ++predictedBranches; 537 } 538 539 return predict_taken; 540} 541 542template <class Impl> 543bool 544DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid) 545{ 546 Fault fault = NoFault; 547 548 //AlphaDep 549 if (cacheBlocked) { 550 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n", 551 tid); 552 return false; 553 } else if (isSwitchedOut()) { 554 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, switched out\n", 555 tid); 556 return false; 557 } else if (interruptPending && !(fetch_PC & 0x3)) { 558 // Hold off fetch from getting new instructions when: 559 // Cache is blocked, or 560 // while an interrupt is pending and we're not in PAL mode, or 561 // fetch is switched out. 562 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n", 563 tid); 564 return false; 565 } 566 567 // Align the fetch PC so it's at the start of a cache block. 568 Addr block_PC = icacheBlockAlignPC(fetch_PC); 569 570 // If we've already got the block, no need to try to fetch it again. 571 if (cacheDataValid[tid] && block_PC == cacheDataPC[tid]) { 572 return true; 573 } 574 575 // Setup the memReq to do a read of the first instruction's address. 576 // Set the appropriate read size and flags as well. 577 // Build request here. 578 RequestPtr mem_req = new Request(tid, block_PC, cacheBlkSize, 0, 579 fetch_PC, cpu->readCpuId(), tid); 580 581 memReq[tid] = mem_req; 582 583 // Translate the instruction request. 584 fault = cpu->translateInstReq(mem_req, cpu->thread[tid]); 585 586 // In the case of faults, the fetch stage may need to stall and wait 587 // for the ITB miss to be handled. 588 589 // If translation was successful, attempt to read the first 590 // instruction. 591 if (fault == NoFault) { 592#if 0 593 if (cpu->system->memctrl->badaddr(memReq[tid]->paddr) || 594 memReq[tid]->isUncacheable()) { 595 DPRINTF(Fetch, "Fetch: Bad address %#x (hopefully on a " 596 "misspeculating path)!", 597 memReq[tid]->paddr); 598 ret_fault = TheISA::genMachineCheckFault(); 599 return false; 600 } 601#endif 602 603 // Build packet here. 604 PacketPtr data_pkt = new Packet(mem_req, 605 Packet::ReadReq, Packet::Broadcast); 606 data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]); 607 608 cacheDataPC[tid] = block_PC; 609 cacheDataValid[tid] = false; 610 611 DPRINTF(Fetch, "Fetch: Doing instruction read.\n"); 612 613 fetchedCacheLines++; 614 615 // Now do the timing access to see whether or not the instruction 616 // exists within the cache. 617 if (!icachePort->sendTiming(data_pkt)) { 618 if (data_pkt->result == Packet::BadAddress) { 619 fault = TheISA::genMachineCheckFault(); 620 delete mem_req; 621 memReq[tid] = NULL; 622 } 623 assert(retryPkt == NULL); 624 assert(retryTid == -1); 625 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid); 626 fetchStatus[tid] = IcacheWaitRetry; 627 retryPkt = data_pkt; 628 retryTid = tid; 629 cacheBlocked = true; 630 return false; 631 } 632 633 DPRINTF(Fetch, "[tid:%i]: Doing cache access.\n", tid); 634 635 lastIcacheStall[tid] = curTick; 636 637 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache " 638 "response.\n", tid); 639 640 fetchStatus[tid] = IcacheWaitResponse; 641 } else { 642 delete mem_req; 643 memReq[tid] = NULL; 644 } 645 646 ret_fault = fault; 647 return true; 648} 649 650template <class Impl> 651inline void 652DefaultFetch<Impl>::doSquash(const Addr &new_PC, 653 const Addr &new_NPC, unsigned tid) 654{ 655 DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x, NPC to: %#x.\n", 656 tid, new_PC, new_NPC); 657 658 PC[tid] = new_PC; 659 nextPC[tid] = new_NPC; 660 nextNPC[tid] = new_NPC + instSize; 661 662 // Clear the icache miss if it's outstanding. 663 if (fetchStatus[tid] == IcacheWaitResponse) { 664 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n", 665 tid); 666 memReq[tid] = NULL; 667 } 668 669 // Get rid of the retrying packet if it was from this thread. 670 if (retryTid == tid) { 671 assert(cacheBlocked); 672 cacheBlocked = false; 673 retryTid = -1; 674 delete retryPkt->req; 675 delete retryPkt; 676 retryPkt = NULL; 677 } 678 679 fetchStatus[tid] = Squashing; 680 681 ++fetchSquashCycles; 682} 683 684template<class Impl> 685void 686DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC, const Addr &new_NPC, 687 const InstSeqNum &seq_num, 688 unsigned tid) 689{ 690 DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid); 691 692 doSquash(new_PC, new_NPC, tid); 693 694 // Tell the CPU to remove any instructions that are in flight between 695 // fetch and decode. 696 cpu->removeInstsUntil(seq_num, tid); 697} 698 699template<class Impl> 700bool 701DefaultFetch<Impl>::checkStall(unsigned tid) const 702{ 703 bool ret_val = false; 704 705 if (cpu->contextSwitch) { 706 DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid); 707 ret_val = true; 708 } else if (stalls[tid].decode) { 709 DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid); 710 ret_val = true; 711 } else if (stalls[tid].rename) { 712 DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid); 713 ret_val = true; 714 } else if (stalls[tid].iew) { 715 DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid); 716 ret_val = true; 717 } else if (stalls[tid].commit) { 718 DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid); 719 ret_val = true; 720 } 721 722 return ret_val; 723} 724 725template<class Impl> 726typename DefaultFetch<Impl>::FetchStatus 727DefaultFetch<Impl>::updateFetchStatus() 728{ 729 //Check Running 730 std::list<unsigned>::iterator threads = activeThreads->begin(); 731 std::list<unsigned>::iterator end = activeThreads->end(); 732 733 while (threads != end) { 734 unsigned tid = *threads++; 735 736 if (fetchStatus[tid] == Running || 737 fetchStatus[tid] == Squashing || 738 fetchStatus[tid] == IcacheAccessComplete) { 739 740 if (_status == Inactive) { 741 DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid); 742 743 if (fetchStatus[tid] == IcacheAccessComplete) { 744 DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache" 745 "completion\n",tid); 746 } 747 748 cpu->activateStage(O3CPU::FetchIdx); 749 } 750 751 return Active; 752 } 753 } 754 755 // Stage is switching from active to inactive, notify CPU of it. 756 if (_status == Active) { 757 DPRINTF(Activity, "Deactivating stage.\n"); 758 759 cpu->deactivateStage(O3CPU::FetchIdx); 760 } 761 762 return Inactive; 763} 764 765template <class Impl> 766void 767DefaultFetch<Impl>::squash(const Addr &new_PC, const Addr &new_NPC, 768 const InstSeqNum &seq_num, 769 bool squash_delay_slot, unsigned tid) 770{ 771 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid); 772 773 doSquash(new_PC, new_NPC, tid); 774 775#if ISA_HAS_DELAY_SLOT 776 // Tell the CPU to remove any instructions that are not in the ROB. 777 cpu->removeInstsNotInROB(tid, squash_delay_slot, seq_num); 778#else 779 // Tell the CPU to remove any instructions that are not in the ROB. 780 cpu->removeInstsNotInROB(tid, true, 0); 781#endif 782} 783 784template <class Impl> 785void 786DefaultFetch<Impl>::tick() 787{ 788 std::list<unsigned>::iterator threads = activeThreads->begin(); 789 std::list<unsigned>::iterator end = activeThreads->end(); 790 bool status_change = false; 791 792 wroteToTimeBuffer = false; 793 794 while (threads != end) { 795 unsigned tid = *threads++; 796 797 // Check the signals for each thread to determine the proper status 798 // for each thread. 799 bool updated_status = checkSignalsAndUpdate(tid); 800 status_change = status_change || updated_status; 801 } 802 803 DPRINTF(Fetch, "Running stage.\n"); 804 805 // Reset the number of the instruction we're fetching. 806 numInst = 0; 807 808#if FULL_SYSTEM 809 if (fromCommit->commitInfo[0].interruptPending) { 810 interruptPending = true; 811 } 812 813 if (fromCommit->commitInfo[0].clearInterrupt) { 814 interruptPending = false; 815 } 816#endif 817 818 for (threadFetched = 0; threadFetched < numFetchingThreads; 819 threadFetched++) { 820 // Fetch each of the actively fetching threads. 821 fetch(status_change); 822 } 823 824 // Record number of instructions fetched this cycle for distribution. 825 fetchNisnDist.sample(numInst); 826 827 if (status_change) { 828 // Change the fetch stage status if there was a status change. 829 _status = updateFetchStatus(); 830 } 831 832 // If there was activity this cycle, inform the CPU of it. 833 if (wroteToTimeBuffer || cpu->contextSwitch) { 834 DPRINTF(Activity, "Activity this cycle.\n"); 835 836 cpu->activityThisCycle(); 837 } 838} 839 840template <class Impl> 841bool 842DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid) 843{ 844 // Update the per thread stall statuses. 845 if (fromDecode->decodeBlock[tid]) { 846 stalls[tid].decode = true; 847 } 848 849 if (fromDecode->decodeUnblock[tid]) { 850 assert(stalls[tid].decode); 851 assert(!fromDecode->decodeBlock[tid]); 852 stalls[tid].decode = false; 853 } 854 855 if (fromRename->renameBlock[tid]) { 856 stalls[tid].rename = true; 857 } 858 859 if (fromRename->renameUnblock[tid]) { 860 assert(stalls[tid].rename); 861 assert(!fromRename->renameBlock[tid]); 862 stalls[tid].rename = false; 863 } 864 865 if (fromIEW->iewBlock[tid]) { 866 stalls[tid].iew = true; 867 } 868 869 if (fromIEW->iewUnblock[tid]) { 870 assert(stalls[tid].iew); 871 assert(!fromIEW->iewBlock[tid]); 872 stalls[tid].iew = false; 873 } 874 875 if (fromCommit->commitBlock[tid]) { 876 stalls[tid].commit = true; 877 } 878 879 if (fromCommit->commitUnblock[tid]) { 880 assert(stalls[tid].commit); 881 assert(!fromCommit->commitBlock[tid]); 882 stalls[tid].commit = false; 883 } 884 885 // Check squash signals from commit. 886 if (fromCommit->commitInfo[tid].squash) { 887 888 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash " 889 "from commit.\n",tid); 890 891#if ISA_HAS_DELAY_SLOT 892 InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].bdelayDoneSeqNum; 893#else 894 InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].doneSeqNum; 895#endif 896 // In any case, squash. 897 squash(fromCommit->commitInfo[tid].nextPC, 898 fromCommit->commitInfo[tid].nextNPC, 899 doneSeqNum, 900 fromCommit->commitInfo[tid].squashDelaySlot, 901 tid); 902 903 // Also check if there's a mispredict that happened. 904 if (fromCommit->commitInfo[tid].branchMispredict) { 905 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum, 906 fromCommit->commitInfo[tid].nextPC, 907 fromCommit->commitInfo[tid].branchTaken, 908 tid); 909 } else { 910 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum, 911 tid); 912 } 913 914 return true; 915 } else if (fromCommit->commitInfo[tid].doneSeqNum) { 916 // Update the branch predictor if it wasn't a squashed instruction 917 // that was broadcasted. 918 branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid); 919 } 920 921 // Check ROB squash signals from commit. 922 if (fromCommit->commitInfo[tid].robSquashing) { 923 DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid); 924 925 // Continue to squash. 926 fetchStatus[tid] = Squashing; 927 928 return true; 929 } 930 931 // Check squash signals from decode. 932 if (fromDecode->decodeInfo[tid].squash) { 933 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash " 934 "from decode.\n",tid); 935 936 // Update the branch predictor. 937 if (fromDecode->decodeInfo[tid].branchMispredict) { 938 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum, 939 fromDecode->decodeInfo[tid].nextPC, 940 fromDecode->decodeInfo[tid].branchTaken, 941 tid); 942 } else { 943 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum, 944 tid); 945 } 946 947 if (fetchStatus[tid] != Squashing) { 948 949#if ISA_HAS_DELAY_SLOT 950 InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].bdelayDoneSeqNum; 951#else 952 InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].doneSeqNum; 953#endif 954 DPRINTF(Fetch, "Squashing from decode with PC = %#x, NPC = %#x\n", 955 fromDecode->decodeInfo[tid].nextPC, 956 fromDecode->decodeInfo[tid].nextNPC); 957 // Squash unless we're already squashing 958 squashFromDecode(fromDecode->decodeInfo[tid].nextPC, 959 fromDecode->decodeInfo[tid].nextNPC, 960 doneSeqNum, 961 tid); 962 963 return true; 964 } 965 } 966 967 if (checkStall(tid) && 968 fetchStatus[tid] != IcacheWaitResponse && 969 fetchStatus[tid] != IcacheWaitRetry) { 970 DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid); 971 972 fetchStatus[tid] = Blocked; 973 974 return true; 975 } 976 977 if (fetchStatus[tid] == Blocked || 978 fetchStatus[tid] == Squashing) { 979 // Switch status to running if fetch isn't being told to block or 980 // squash this cycle. 981 DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n", 982 tid); 983 984 fetchStatus[tid] = Running; 985 986 return true; 987 } 988 989 // If we've reached this point, we have not gotten any signals that 990 // cause fetch to change its status. Fetch remains the same as before. 991 return false; 992} 993 994template<class Impl> 995void 996DefaultFetch<Impl>::fetch(bool &status_change) 997{ 998 ////////////////////////////////////////// 999 // Start actual fetch 1000 ////////////////////////////////////////// 1001 int tid = getFetchingThread(fetchPolicy); 1002 1003 if (tid == -1 || drainPending) { 1004 DPRINTF(Fetch,"There are no more threads available to fetch from.\n"); 1005 1006 // Breaks looping condition in tick() 1007 threadFetched = numFetchingThreads; 1008 return; 1009 } 1010 1011 DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid); 1012 1013 // The current PC. 1014 Addr &fetch_PC = PC[tid]; 1015 1016 Addr &fetch_NPC = nextPC[tid]; 1017 1018 // Fault code for memory access. 1019 Fault fault = NoFault; 1020 1021 // If returning from the delay of a cache miss, then update the status 1022 // to running, otherwise do the cache access. Possibly move this up 1023 // to tick() function. 1024 if (fetchStatus[tid] == IcacheAccessComplete) { 1025 DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n", 1026 tid); 1027 1028 fetchStatus[tid] = Running; 1029 status_change = true; 1030 } else if (fetchStatus[tid] == Running) { 1031 DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read " 1032 "instruction, starting at PC %08p.\n", 1033 tid, fetch_PC); 1034 1035 bool fetch_success = fetchCacheLine(fetch_PC, fault, tid); 1036 if (!fetch_success) { 1037 if (cacheBlocked) { 1038 ++icacheStallCycles; 1039 } else { 1040 ++fetchMiscStallCycles; 1041 } 1042 return; 1043 } 1044 } else { 1045 if (fetchStatus[tid] == Idle) { 1046 ++fetchIdleCycles; 1047 DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid); 1048 } else if (fetchStatus[tid] == Blocked) { 1049 ++fetchBlockedCycles; 1050 DPRINTF(Fetch, "[tid:%i]: Fetch is blocked!\n", tid); 1051 } else if (fetchStatus[tid] == Squashing) { 1052 ++fetchSquashCycles; 1053 DPRINTF(Fetch, "[tid:%i]: Fetch is squashing!\n", tid); 1054 } else if (fetchStatus[tid] == IcacheWaitResponse) { 1055 ++icacheStallCycles; 1056 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n", tid); 1057 } 1058 1059 // Status is Idle, Squashing, Blocked, or IcacheWaitResponse, so 1060 // fetch should do nothing. 1061 return; 1062 } 1063 1064 ++fetchCycles; 1065 1066 // If we had a stall due to an icache miss, then return. 1067 if (fetchStatus[tid] == IcacheWaitResponse) { 1068 ++icacheStallCycles; 1069 status_change = true; 1070 return; 1071 } 1072 1073 Addr next_PC = fetch_PC; 1074 Addr next_NPC = fetch_NPC; 1075 1076 InstSeqNum inst_seq; 1077 MachInst inst; 1078 ExtMachInst ext_inst; 1079 // @todo: Fix this hack. 1080 unsigned offset = (fetch_PC & cacheBlkMask) & ~3; 1081 1082 if (fault == NoFault) { 1083 // If the read of the first instruction was successful, then grab the 1084 // instructions from the rest of the cache line and put them into the 1085 // queue heading to decode. 1086 1087 DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to " 1088 "decode.\n",tid); 1089 1090 // Need to keep track of whether or not a predicted branch 1091 // ended this fetch block. 1092 bool predicted_branch = false; 1093 1094 for (; 1095 offset < cacheBlkSize && 1096 numInst < fetchWidth && 1097 !predicted_branch; 1098 ++numInst) { 1099 1100 // If we're branching after this instruction, quite fetching 1101 // from the same block then. 1102 predicted_branch = 1103 (fetch_PC + sizeof(TheISA::MachInst) != fetch_NPC); 1104 if (predicted_branch) { 1105 DPRINTF(Fetch, "Branch detected with PC = %#x, NPC = %#x\n", 1106 fetch_PC, fetch_NPC); 1107 } 1108 1109 1110 // Get a sequence number. 1111 inst_seq = cpu->getAndIncrementInstSeq(); 1112 1113 // Make sure this is a valid index. 1114 assert(offset <= cacheBlkSize - instSize); 1115 1116 // Get the instruction from the array of the cache line. 1117 inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *> 1118 (&cacheData[tid][offset])); 1119 1120#if THE_ISA == ALPHA_ISA 1121 ext_inst = TheISA::makeExtMI(inst, fetch_PC); 1122#elif THE_ISA == SPARC_ISA 1123 ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC()); 1124#elif THE_ISA == MIPS_ISA 1125 ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC()); 1126#endif 1127 1128 // Create a new DynInst from the instruction fetched. 1129 DynInstPtr instruction = new DynInst(ext_inst, 1130 fetch_PC, fetch_NPC, 1131 next_PC, next_NPC, 1132 inst_seq, cpu); 1133 instruction->setTid(tid); 1134 1135 instruction->setASID(tid); 1136 1137 instruction->setThreadState(cpu->thread[tid]); 1138 1139 DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created " 1140 "[sn:%lli]\n", 1141 tid, instruction->readPC(), inst_seq); 1142 1143 //DPRINTF(Fetch, "[tid:%i]: MachInst is %#x\n", tid, ext_inst); 1144 1145 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", 1146 tid, instruction->staticInst->disassemble(fetch_PC)); 1147 1148 instruction->traceData = 1149 Trace::getInstRecord(curTick, cpu->tcBase(tid), 1150 instruction->staticInst, 1151 instruction->readPC()); 1152 1153 ///FIXME This needs to be more robust in dealing with delay slots 1154#if !ISA_HAS_DELAY_SLOT 1155 predicted_branch |= 1156#endif 1157 lookupAndUpdateNextPC(instruction, next_PC, next_NPC); 1158 predicted_branch |= (next_PC != fetch_NPC); 1159 1160 // Add instruction to the CPU's list of instructions. 1161 instruction->setInstListIt(cpu->addInst(instruction)); 1162 1163 // Write the instruction to the first slot in the queue 1164 // that heads to decode. 1165 toDecode->insts[numInst] = instruction; 1166 1167 toDecode->size++; 1168 1169 // Increment stat of fetched instructions. 1170 ++fetchedInsts; 1171 1172 // Move to the next instruction, unless we have a branch. 1173 fetch_PC = next_PC; 1174 fetch_NPC = next_NPC; 1175 1176 if (instruction->isQuiesce()) { 1177 DPRINTF(Fetch, "Quiesce instruction encountered, halting fetch!", 1178 curTick); 1179 fetchStatus[tid] = QuiescePending; 1180 ++numInst; 1181 status_change = true; 1182 break; 1183 } 1184 1185 offset += instSize; 1186 } 1187 1188 if (offset >= cacheBlkSize) { 1189 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache " 1190 "block.\n", tid); 1191 } else if (numInst >= fetchWidth) { 1192 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth " 1193 "for this cycle.\n", tid); 1194 } else if (predicted_branch) { 1195 DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch " 1196 "instruction encountered.\n", tid); 1197 } 1198 } 1199 1200 if (numInst > 0) { 1201 wroteToTimeBuffer = true; 1202 } 1203 1204 // Now that fetching is completed, update the PC to signify what the next 1205 // cycle will be. 1206 if (fault == NoFault) { 1207 PC[tid] = next_PC; 1208 nextPC[tid] = next_NPC; 1209 nextNPC[tid] = next_NPC + instSize; 1210#if ISA_HAS_DELAY_SLOT 1211 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, PC[tid]); 1212#else 1213 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, next_PC); 1214#endif 1215 } else { 1216 // We shouldn't be in an icache miss and also have a fault (an ITB 1217 // miss) 1218 if (fetchStatus[tid] == IcacheWaitResponse) { 1219 panic("Fetch should have exited prior to this!"); 1220 } 1221 1222 // Send the fault to commit. This thread will not do anything 1223 // until commit handles the fault. The only other way it can 1224 // wake up is if a squash comes along and changes the PC. 1225#if FULL_SYSTEM 1226 assert(numInst != fetchWidth); 1227 // Get a sequence number. 1228 inst_seq = cpu->getAndIncrementInstSeq(); 1229 // We will use a nop in order to carry the fault. 1230 ext_inst = TheISA::NoopMachInst; 1231 1232 // Create a new DynInst from the dummy nop. 1233 DynInstPtr instruction = new DynInst(ext_inst, 1234 fetch_PC, fetch_NPC, 1235 next_PC, next_NPC, 1236 inst_seq, cpu); 1237 instruction->setPredTarg(next_PC, next_NPC); 1238 instruction->setTid(tid); 1239 1240 instruction->setASID(tid); 1241 1242 instruction->setThreadState(cpu->thread[tid]); 1243 1244 instruction->traceData = NULL; 1245 1246 instruction->setInstListIt(cpu->addInst(instruction)); 1247 1248 instruction->fault = fault; 1249 1250 toDecode->insts[numInst] = instruction; 1251 toDecode->size++; 1252 1253 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid); 1254 1255 fetchStatus[tid] = TrapPending; 1256 status_change = true; 1257#else // !FULL_SYSTEM 1258 fetchStatus[tid] = TrapPending; 1259 status_change = true; 1260 1261#endif // FULL_SYSTEM 1262 DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %08p", 1263 tid, fault->name(), PC[tid]); 1264 } 1265} 1266 1267template<class Impl> 1268void 1269DefaultFetch<Impl>::recvRetry() 1270{ 1271 if (retryPkt != NULL) { 1272 assert(cacheBlocked); 1273 assert(retryTid != -1); 1274 assert(fetchStatus[retryTid] == IcacheWaitRetry); 1275 1276 if (icachePort->sendTiming(retryPkt)) { 1277 fetchStatus[retryTid] = IcacheWaitResponse; 1278 retryPkt = NULL; 1279 retryTid = -1; 1280 cacheBlocked = false; 1281 } 1282 } else { 1283 assert(retryTid == -1); 1284 // Access has been squashed since it was sent out. Just clear 1285 // the cache being blocked. 1286 cacheBlocked = false; 1287 } 1288} 1289 1290/////////////////////////////////////// 1291// // 1292// SMT FETCH POLICY MAINTAINED HERE // 1293// // 1294/////////////////////////////////////// 1295template<class Impl> 1296int 1297DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority) 1298{ 1299 if (numThreads > 1) { 1300 switch (fetch_priority) { 1301 1302 case SingleThread: 1303 return 0; 1304 1305 case RoundRobin: 1306 return roundRobin(); 1307 1308 case IQ: 1309 return iqCount(); 1310 1311 case LSQ: 1312 return lsqCount(); 1313 1314 case Branch: 1315 return branchCount(); 1316 1317 default: 1318 return -1; 1319 } 1320 } else { 1321 std::list<unsigned>::iterator thread = activeThreads->begin(); 1322 assert(thread != activeThreads->end()); 1323 int tid = *thread; 1324 1325 if (fetchStatus[tid] == Running || 1326 fetchStatus[tid] == IcacheAccessComplete || 1327 fetchStatus[tid] == Idle) { 1328 return tid; 1329 } else { 1330 return -1; 1331 } 1332 } 1333 1334} 1335 1336 1337template<class Impl> 1338int 1339DefaultFetch<Impl>::roundRobin() 1340{ 1341 std::list<unsigned>::iterator pri_iter = priorityList.begin(); 1342 std::list<unsigned>::iterator end = priorityList.end(); 1343 1344 int high_pri; 1345 1346 while (pri_iter != end) { 1347 high_pri = *pri_iter; 1348 1349 assert(high_pri <= numThreads); 1350 1351 if (fetchStatus[high_pri] == Running || 1352 fetchStatus[high_pri] == IcacheAccessComplete || 1353 fetchStatus[high_pri] == Idle) { 1354 1355 priorityList.erase(pri_iter); 1356 priorityList.push_back(high_pri); 1357 1358 return high_pri; 1359 } 1360 1361 pri_iter++; 1362 } 1363 1364 return -1; 1365} 1366 1367template<class Impl> 1368int 1369DefaultFetch<Impl>::iqCount() 1370{ 1371 std::priority_queue<unsigned> PQ; 1372 1373 std::list<unsigned>::iterator threads = activeThreads->begin(); 1374 std::list<unsigned>::iterator end = activeThreads->end(); 1375 1376 while (threads != end) { 1377 unsigned tid = *threads++; 1378 1379 PQ.push(fromIEW->iewInfo[tid].iqCount); 1380 } 1381 1382 while (!PQ.empty()) { 1383 1384 unsigned high_pri = PQ.top(); 1385 1386 if (fetchStatus[high_pri] == Running || 1387 fetchStatus[high_pri] == IcacheAccessComplete || 1388 fetchStatus[high_pri] == Idle) 1389 return high_pri; 1390 else 1391 PQ.pop(); 1392 1393 } 1394 1395 return -1; 1396} 1397 1398template<class Impl> 1399int 1400DefaultFetch<Impl>::lsqCount() 1401{ 1402 std::priority_queue<unsigned> PQ; 1403 1404 std::list<unsigned>::iterator threads = activeThreads->begin(); 1405 std::list<unsigned>::iterator end = activeThreads->end(); 1406 1407 while (threads != end) { 1408 unsigned tid = *threads++; 1409 1410 PQ.push(fromIEW->iewInfo[tid].ldstqCount); 1411 } 1412 1413 while (!PQ.empty()) { 1414 1415 unsigned high_pri = PQ.top(); 1416 1417 if (fetchStatus[high_pri] == Running || 1418 fetchStatus[high_pri] == IcacheAccessComplete || 1419 fetchStatus[high_pri] == Idle) 1420 return high_pri; 1421 else 1422 PQ.pop(); 1423 1424 } 1425 1426 return -1; 1427} 1428 1429template<class Impl> 1430int 1431DefaultFetch<Impl>::branchCount() 1432{ 1433 std::list<unsigned>::iterator thread = activeThreads->begin(); 1434 assert(thread != activeThreads->end()); 1435 unsigned tid = *thread; 1436 1437 panic("Branch Count Fetch policy unimplemented\n"); 1438 return 0 * tid; 1439} 1440