fetch_impl.hh revision 3802:e8f55dfb0f56
16973Stjones1@inf.ed.ac.uk/* 27944SGiacomo.Gabrielli@arm.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 37944SGiacomo.Gabrielli@arm.com * All rights reserved. 47944SGiacomo.Gabrielli@arm.com * 57944SGiacomo.Gabrielli@arm.com * Redistribution and use in source and binary forms, with or without 67944SGiacomo.Gabrielli@arm.com * modification, are permitted provided that the following conditions are 77944SGiacomo.Gabrielli@arm.com * met: redistributions of source code must retain the above copyright 87944SGiacomo.Gabrielli@arm.com * notice, this list of conditions and the following disclaimer; 97944SGiacomo.Gabrielli@arm.com * redistributions in binary form must reproduce the above copyright 107944SGiacomo.Gabrielli@arm.com * notice, this list of conditions and the following disclaimer in the 117944SGiacomo.Gabrielli@arm.com * documentation and/or other materials provided with the distribution; 127944SGiacomo.Gabrielli@arm.com * neither the name of the copyright holders nor the names of its 137944SGiacomo.Gabrielli@arm.com * contributors may be used to endorse or promote products derived from 146973Stjones1@inf.ed.ac.uk * this software without specific prior written permission. 156973Stjones1@inf.ed.ac.uk * 166973Stjones1@inf.ed.ac.uk * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176973Stjones1@inf.ed.ac.uk * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186973Stjones1@inf.ed.ac.uk * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196973Stjones1@inf.ed.ac.uk * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206973Stjones1@inf.ed.ac.uk * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216973Stjones1@inf.ed.ac.uk * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226973Stjones1@inf.ed.ac.uk * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236973Stjones1@inf.ed.ac.uk * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246973Stjones1@inf.ed.ac.uk * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256973Stjones1@inf.ed.ac.uk * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266973Stjones1@inf.ed.ac.uk * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276973Stjones1@inf.ed.ac.uk * 286973Stjones1@inf.ed.ac.uk * Authors: Kevin Lim 296973Stjones1@inf.ed.ac.uk * Korey Sewell 306973Stjones1@inf.ed.ac.uk */ 316973Stjones1@inf.ed.ac.uk 326973Stjones1@inf.ed.ac.uk#include "config/use_checker.hh" 336973Stjones1@inf.ed.ac.uk 346973Stjones1@inf.ed.ac.uk#include "arch/isa_traits.hh" 356973Stjones1@inf.ed.ac.uk#include "arch/utility.hh" 366973Stjones1@inf.ed.ac.uk#include "cpu/checker/cpu.hh" 376973Stjones1@inf.ed.ac.uk#include "cpu/exetrace.hh" 386973Stjones1@inf.ed.ac.uk#include "cpu/o3/fetch.hh" 396973Stjones1@inf.ed.ac.uk#include "mem/packet.hh" 406973Stjones1@inf.ed.ac.uk#include "mem/request.hh" 416973Stjones1@inf.ed.ac.uk#include "sim/byteswap.hh" 426973Stjones1@inf.ed.ac.uk#include "sim/host.hh" 436973Stjones1@inf.ed.ac.uk#include "sim/root.hh" 446973Stjones1@inf.ed.ac.uk 456973Stjones1@inf.ed.ac.uk#if FULL_SYSTEM 466973Stjones1@inf.ed.ac.uk#include "arch/tlb.hh" 476973Stjones1@inf.ed.ac.uk#include "arch/vtophys.hh" 487678Sgblack@eecs.umich.edu#include "sim/system.hh" 496973Stjones1@inf.ed.ac.uk#endif // FULL_SYSTEM 506973Stjones1@inf.ed.ac.uk 517049Stjones1@inf.ed.ac.uk#include <algorithm> 527049Stjones1@inf.ed.ac.uk 537049Stjones1@inf.ed.ac.uktemplate<class Impl> 547049Stjones1@inf.ed.ac.ukTick 557049Stjones1@inf.ed.ac.ukDefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt) 567049Stjones1@inf.ed.ac.uk{ 577049Stjones1@inf.ed.ac.uk panic("DefaultFetch doesn't expect recvAtomic callback!"); 587049Stjones1@inf.ed.ac.uk return curTick; 597049Stjones1@inf.ed.ac.uk} 607049Stjones1@inf.ed.ac.uk 616973Stjones1@inf.ed.ac.uktemplate<class Impl> 626973Stjones1@inf.ed.ac.ukvoid 636973Stjones1@inf.ed.ac.ukDefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt) 646973Stjones1@inf.ed.ac.uk{ 656973Stjones1@inf.ed.ac.uk DPRINTF(Fetch, "DefaultFetch doesn't update its state from a " 666973Stjones1@inf.ed.ac.uk "functional call."); 676973Stjones1@inf.ed.ac.uk} 687944SGiacomo.Gabrielli@arm.com 696973Stjones1@inf.ed.ac.uktemplate<class Impl> 706973Stjones1@inf.ed.ac.ukvoid 716973Stjones1@inf.ed.ac.ukDefaultFetch<Impl>::IcachePort::recvStatusChange(Status status) 726973Stjones1@inf.ed.ac.uk{ 736973Stjones1@inf.ed.ac.uk if (status == RangeChange) { 746973Stjones1@inf.ed.ac.uk if (!snoopRangeSent) { 756973Stjones1@inf.ed.ac.uk snoopRangeSent = true; 766973Stjones1@inf.ed.ac.uk sendStatusChange(Port::RangeChange); 777049Stjones1@inf.ed.ac.uk } 787049Stjones1@inf.ed.ac.uk return; 797049Stjones1@inf.ed.ac.uk } 807049Stjones1@inf.ed.ac.uk 816973Stjones1@inf.ed.ac.uk panic("DefaultFetch doesn't expect recvStatusChange callback!"); 826973Stjones1@inf.ed.ac.uk} 837944SGiacomo.Gabrielli@arm.com 847944SGiacomo.Gabrielli@arm.comtemplate<class Impl> 856973Stjones1@inf.ed.ac.ukbool 866973Stjones1@inf.ed.ac.ukDefaultFetch<Impl>::IcachePort::recvTiming(PacketPtr pkt) 876973Stjones1@inf.ed.ac.uk{ 886973Stjones1@inf.ed.ac.uk DPRINTF(Fetch, "Received timing\n"); 896973Stjones1@inf.ed.ac.uk if (pkt->isResponse()) { 907049Stjones1@inf.ed.ac.uk fetch->processCacheCompletion(pkt); 917049Stjones1@inf.ed.ac.uk } 927049Stjones1@inf.ed.ac.uk //else Snooped a coherence request, just return 937049Stjones1@inf.ed.ac.uk return true; 947049Stjones1@inf.ed.ac.uk} 956973Stjones1@inf.ed.ac.uk 966973Stjones1@inf.ed.ac.uktemplate<class Impl> 976973Stjones1@inf.ed.ac.ukvoid 987944SGiacomo.Gabrielli@arm.comDefaultFetch<Impl>::IcachePort::recvRetry() 997944SGiacomo.Gabrielli@arm.com{ 1007944SGiacomo.Gabrielli@arm.com fetch->recvRetry(); 1016973Stjones1@inf.ed.ac.uk} 1026973Stjones1@inf.ed.ac.uk 1036973Stjones1@inf.ed.ac.uktemplate<class Impl> 1046973Stjones1@inf.ed.ac.ukDefaultFetch<Impl>::DefaultFetch(Params *params) 1056973Stjones1@inf.ed.ac.uk : branchPred(params), 1067049Stjones1@inf.ed.ac.uk decodeToFetchDelay(params->decodeToFetchDelay), 1077049Stjones1@inf.ed.ac.uk renameToFetchDelay(params->renameToFetchDelay), 1087049Stjones1@inf.ed.ac.uk iewToFetchDelay(params->iewToFetchDelay), 1097049Stjones1@inf.ed.ac.uk commitToFetchDelay(params->commitToFetchDelay), 1107049Stjones1@inf.ed.ac.uk fetchWidth(params->fetchWidth), 1117049Stjones1@inf.ed.ac.uk cacheBlocked(false), 1127049Stjones1@inf.ed.ac.uk retryPkt(NULL), 1136973Stjones1@inf.ed.ac.uk retryTid(-1), 11410379Sandreas.hansson@arm.com numThreads(params->numberOfThreads), 1156973Stjones1@inf.ed.ac.uk numFetchingThreads(params->smtNumFetchingThreads), 1166973Stjones1@inf.ed.ac.uk interruptPending(false), 1176973Stjones1@inf.ed.ac.uk drainPending(false), 1186973Stjones1@inf.ed.ac.uk switchedOut(false) 1196973Stjones1@inf.ed.ac.uk{ 1206973Stjones1@inf.ed.ac.uk if (numThreads > Impl::MaxThreads) 1216973Stjones1@inf.ed.ac.uk fatal("numThreads is not a valid value\n"); 1226973Stjones1@inf.ed.ac.uk 1236973Stjones1@inf.ed.ac.uk // Set fetch stage's status to inactive. 1246973Stjones1@inf.ed.ac.uk _status = Inactive; 1256973Stjones1@inf.ed.ac.uk 1266973Stjones1@inf.ed.ac.uk std::string policy = params->smtFetchPolicy; 1276973Stjones1@inf.ed.ac.uk 1286973Stjones1@inf.ed.ac.uk // Convert string to lowercase 1296973Stjones1@inf.ed.ac.uk std::transform(policy.begin(), policy.end(), policy.begin(), 1306973Stjones1@inf.ed.ac.uk (int(*)(int)) tolower); 1317049Stjones1@inf.ed.ac.uk 1327049Stjones1@inf.ed.ac.uk // Figure out fetch policy 1337049Stjones1@inf.ed.ac.uk if (policy == "singlethread") { 1347049Stjones1@inf.ed.ac.uk fetchPolicy = SingleThread; 1356973Stjones1@inf.ed.ac.uk if (numThreads > 1) 1366973Stjones1@inf.ed.ac.uk panic("Invalid Fetch Policy for a SMT workload."); 1376973Stjones1@inf.ed.ac.uk } else if (policy == "roundrobin") { 1386973Stjones1@inf.ed.ac.uk fetchPolicy = RoundRobin; 1396973Stjones1@inf.ed.ac.uk DPRINTF(Fetch, "Fetch policy set to Round Robin\n"); 1406973Stjones1@inf.ed.ac.uk } else if (policy == "branch") { 1416973Stjones1@inf.ed.ac.uk fetchPolicy = Branch; 1426973Stjones1@inf.ed.ac.uk DPRINTF(Fetch, "Fetch policy set to Branch Count\n"); 1436973Stjones1@inf.ed.ac.uk } else if (policy == "iqcount") { 1446973Stjones1@inf.ed.ac.uk fetchPolicy = IQ; 1456973Stjones1@inf.ed.ac.uk DPRINTF(Fetch, "Fetch policy set to IQ count\n"); 1466973Stjones1@inf.ed.ac.uk } else if (policy == "lsqcount") { 1476973Stjones1@inf.ed.ac.uk fetchPolicy = LSQ; 1487049Stjones1@inf.ed.ac.uk DPRINTF(Fetch, "Fetch policy set to LSQ count\n"); 1496973Stjones1@inf.ed.ac.uk } else { 1506973Stjones1@inf.ed.ac.uk fatal("Invalid Fetch Policy. Options Are: {SingleThread," 1516973Stjones1@inf.ed.ac.uk " RoundRobin,LSQcount,IQcount}\n"); 1526973Stjones1@inf.ed.ac.uk } 1536973Stjones1@inf.ed.ac.uk 1546973Stjones1@inf.ed.ac.uk // Get the size of an instruction. 1557049Stjones1@inf.ed.ac.uk instSize = sizeof(TheISA::MachInst); 1567049Stjones1@inf.ed.ac.uk} 1577049Stjones1@inf.ed.ac.uk 1587049Stjones1@inf.ed.ac.uktemplate <class Impl> 1597049Stjones1@inf.ed.ac.ukstd::string 1606973Stjones1@inf.ed.ac.ukDefaultFetch<Impl>::name() const 1616973Stjones1@inf.ed.ac.uk{ 1626973Stjones1@inf.ed.ac.uk return cpu->name() + ".fetch"; 1636973Stjones1@inf.ed.ac.uk} 1646973Stjones1@inf.ed.ac.uk 1656973Stjones1@inf.ed.ac.uktemplate <class Impl> 1667049Stjones1@inf.ed.ac.ukvoid 1677049Stjones1@inf.ed.ac.ukDefaultFetch<Impl>::regStats() 1687049Stjones1@inf.ed.ac.uk{ 1697049Stjones1@inf.ed.ac.uk icacheStallCycles 1707049Stjones1@inf.ed.ac.uk .name(name() + ".icacheStallCycles") 1716973Stjones1@inf.ed.ac.uk .desc("Number of cycles fetch is stalled on an Icache miss") 1726973Stjones1@inf.ed.ac.uk .prereq(icacheStallCycles); 1736973Stjones1@inf.ed.ac.uk 1746973Stjones1@inf.ed.ac.uk fetchedInsts 1756973Stjones1@inf.ed.ac.uk .name(name() + ".Insts") 1766973Stjones1@inf.ed.ac.uk .desc("Number of instructions fetch has processed") 1777049Stjones1@inf.ed.ac.uk .prereq(fetchedInsts); 1786973Stjones1@inf.ed.ac.uk 1796973Stjones1@inf.ed.ac.uk fetchedBranches 1806973Stjones1@inf.ed.ac.uk .name(name() + ".Branches") 1816973Stjones1@inf.ed.ac.uk .desc("Number of branches that fetch encountered") 1826973Stjones1@inf.ed.ac.uk .prereq(fetchedBranches); 1836973Stjones1@inf.ed.ac.uk 1847049Stjones1@inf.ed.ac.uk predictedBranches 1857049Stjones1@inf.ed.ac.uk .name(name() + ".predictedBranches") 1867049Stjones1@inf.ed.ac.uk .desc("Number of branches that fetch has predicted taken") 1877049Stjones1@inf.ed.ac.uk .prereq(predictedBranches); 1887049Stjones1@inf.ed.ac.uk 1896973Stjones1@inf.ed.ac.uk fetchCycles 1906973Stjones1@inf.ed.ac.uk .name(name() + ".Cycles") 1916973Stjones1@inf.ed.ac.uk .desc("Number of cycles fetch has run and was not squashing or" 1926973Stjones1@inf.ed.ac.uk " blocked") 1936973Stjones1@inf.ed.ac.uk .prereq(fetchCycles); 1946973Stjones1@inf.ed.ac.uk 1957049Stjones1@inf.ed.ac.uk fetchSquashCycles 1966973Stjones1@inf.ed.ac.uk .name(name() + ".SquashCycles") 1976973Stjones1@inf.ed.ac.uk .desc("Number of cycles fetch has spent squashing") 1986973Stjones1@inf.ed.ac.uk .prereq(fetchSquashCycles); 1996973Stjones1@inf.ed.ac.uk 2006973Stjones1@inf.ed.ac.uk fetchIdleCycles 2016973Stjones1@inf.ed.ac.uk .name(name() + ".IdleCycles") 2026973Stjones1@inf.ed.ac.uk .desc("Number of cycles fetch was idle") 2036973Stjones1@inf.ed.ac.uk .prereq(fetchIdleCycles); 2046973Stjones1@inf.ed.ac.uk 2056973Stjones1@inf.ed.ac.uk fetchBlockedCycles 2066973Stjones1@inf.ed.ac.uk .name(name() + ".BlockedCycles") 2077049Stjones1@inf.ed.ac.uk .desc("Number of cycles fetch has spent blocked") 2087049Stjones1@inf.ed.ac.uk .prereq(fetchBlockedCycles); 2097049Stjones1@inf.ed.ac.uk 2107049Stjones1@inf.ed.ac.uk fetchedCacheLines 2117049Stjones1@inf.ed.ac.uk .name(name() + ".CacheLines") 2127049Stjones1@inf.ed.ac.uk .desc("Number of cache lines fetched") 2137049Stjones1@inf.ed.ac.uk .prereq(fetchedCacheLines); 2147049Stjones1@inf.ed.ac.uk 2157049Stjones1@inf.ed.ac.uk fetchMiscStallCycles 2167049Stjones1@inf.ed.ac.uk .name(name() + ".MiscStallCycles") 2178486Sgblack@eecs.umich.edu .desc("Number of cycles fetch has spent waiting on interrupts, or " 2186973Stjones1@inf.ed.ac.uk "bad addresses, or out of MSHRs") 2196973Stjones1@inf.ed.ac.uk .prereq(fetchMiscStallCycles); 2206973Stjones1@inf.ed.ac.uk 2218486Sgblack@eecs.umich.edu fetchIcacheSquashes 2226973Stjones1@inf.ed.ac.uk .name(name() + ".IcacheSquashes") 2236973Stjones1@inf.ed.ac.uk .desc("Number of outstanding Icache misses that were squashed") 2246973Stjones1@inf.ed.ac.uk .prereq(fetchIcacheSquashes); 2256973Stjones1@inf.ed.ac.uk 2268486Sgblack@eecs.umich.edu fetchNisnDist 2276973Stjones1@inf.ed.ac.uk .init(/* base value */ 0, 2286973Stjones1@inf.ed.ac.uk /* last value */ fetchWidth, 2296973Stjones1@inf.ed.ac.uk /* bucket size */ 1) 2306973Stjones1@inf.ed.ac.uk .name(name() + ".rateDist") 2318486Sgblack@eecs.umich.edu .desc("Number of instructions fetched each cycle (Total)") 2326973Stjones1@inf.ed.ac.uk .flags(Stats::pdf); 2336973Stjones1@inf.ed.ac.uk 2346973Stjones1@inf.ed.ac.uk idleRate 2356973Stjones1@inf.ed.ac.uk .name(name() + ".idleRate") 2366973Stjones1@inf.ed.ac.uk .desc("Percent of cycles fetch was idle") 2377049Stjones1@inf.ed.ac.uk .prereq(idleRate); 2387944SGiacomo.Gabrielli@arm.com idleRate = fetchIdleCycles * 100 / cpu->numCycles; 2397944SGiacomo.Gabrielli@arm.com 2407944SGiacomo.Gabrielli@arm.com branchRate 2417944SGiacomo.Gabrielli@arm.com .name(name() + ".branchRate") 2427944SGiacomo.Gabrielli@arm.com .desc("Number of branch fetches per cycle") 2437944SGiacomo.Gabrielli@arm.com .flags(Stats::total); 2447944SGiacomo.Gabrielli@arm.com branchRate = fetchedBranches / cpu->numCycles; 2457944SGiacomo.Gabrielli@arm.com 2467944SGiacomo.Gabrielli@arm.com fetchRate 2477944SGiacomo.Gabrielli@arm.com .name(name() + ".rate") 2487049Stjones1@inf.ed.ac.uk .desc("Number of inst fetches per cycle") 2497049Stjones1@inf.ed.ac.uk .flags(Stats::total); 2507049Stjones1@inf.ed.ac.uk fetchRate = fetchedInsts / cpu->numCycles; 2516973Stjones1@inf.ed.ac.uk 25210379Sandreas.hansson@arm.com branchPred.regStats(); 2536973Stjones1@inf.ed.ac.uk} 2546973Stjones1@inf.ed.ac.uk 2556973Stjones1@inf.ed.ac.uktemplate<class Impl> 2566973Stjones1@inf.ed.ac.ukvoid 2576973Stjones1@inf.ed.ac.ukDefaultFetch<Impl>::setCPU(O3CPU *cpu_ptr) 25810177SMitchell.Hayenga@ARM.com{ 25910177SMitchell.Hayenga@ARM.com DPRINTF(Fetch, "Setting the CPU pointer.\n"); 26010177SMitchell.Hayenga@ARM.com cpu = cpu_ptr; 26110177SMitchell.Hayenga@ARM.com 2626973Stjones1@inf.ed.ac.uk // Name is finally available, so create the port. 2636973Stjones1@inf.ed.ac.uk icachePort = new IcachePort(this); 2646973Stjones1@inf.ed.ac.uk 2656973Stjones1@inf.ed.ac.uk icachePort->snoopRangeSent = false; 2669258SAli.Saidi@ARM.com 2679258SAli.Saidi@ARM.com#if USE_CHECKER 2689258SAli.Saidi@ARM.com if (cpu->checker) { 2699258SAli.Saidi@ARM.com cpu->checker->setIcachePort(icachePort); 2709258SAli.Saidi@ARM.com } 2719258SAli.Saidi@ARM.com#endif 2726973Stjones1@inf.ed.ac.uk 2736973Stjones1@inf.ed.ac.uk // Schedule fetch to get the correct PC from the CPU 2746973Stjones1@inf.ed.ac.uk // scheduleFetchStartupEvent(1); 275 276 // Fetch needs to start fetching instructions at the very beginning, 277 // so it must start up in active state. 278 switchToActive(); 279} 280 281template<class Impl> 282void 283DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer) 284{ 285 DPRINTF(Fetch, "Setting the time buffer pointer.\n"); 286 timeBuffer = time_buffer; 287 288 // Create wires to get information from proper places in time buffer. 289 fromDecode = timeBuffer->getWire(-decodeToFetchDelay); 290 fromRename = timeBuffer->getWire(-renameToFetchDelay); 291 fromIEW = timeBuffer->getWire(-iewToFetchDelay); 292 fromCommit = timeBuffer->getWire(-commitToFetchDelay); 293} 294 295template<class Impl> 296void 297DefaultFetch<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) 298{ 299 DPRINTF(Fetch, "Setting active threads list pointer.\n"); 300 activeThreads = at_ptr; 301} 302 303template<class Impl> 304void 305DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 306{ 307 DPRINTF(Fetch, "Setting the fetch queue pointer.\n"); 308 fetchQueue = fq_ptr; 309 310 // Create wire to write information to proper place in fetch queue. 311 toDecode = fetchQueue->getWire(0); 312} 313 314template<class Impl> 315void 316DefaultFetch<Impl>::initStage() 317{ 318 // Setup PC and nextPC with initial state. 319 for (int tid = 0; tid < numThreads; tid++) { 320 PC[tid] = cpu->readPC(tid); 321 nextPC[tid] = cpu->readNextPC(tid); 322 nextNPC[tid] = cpu->readNextNPC(tid); 323 } 324 325 // Size of cache block. 326 cacheBlkSize = icachePort->peerBlockSize(); 327 328 // Create mask to get rid of offset bits. 329 cacheBlkMask = (cacheBlkSize - 1); 330 331 for (int tid=0; tid < numThreads; tid++) { 332 333 fetchStatus[tid] = Running; 334 335 priorityList.push_back(tid); 336 337 memReq[tid] = NULL; 338 339 // Create space to store a cache line. 340 cacheData[tid] = new uint8_t[cacheBlkSize]; 341 cacheDataPC[tid] = 0; 342 cacheDataValid[tid] = false; 343 344 delaySlotInfo[tid].branchSeqNum = -1; 345 delaySlotInfo[tid].numInsts = 0; 346 delaySlotInfo[tid].targetAddr = 0; 347 delaySlotInfo[tid].targetReady = false; 348 349 stalls[tid].decode = false; 350 stalls[tid].rename = false; 351 stalls[tid].iew = false; 352 stalls[tid].commit = false; 353 } 354} 355 356template<class Impl> 357void 358DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt) 359{ 360 unsigned tid = pkt->req->getThreadNum(); 361 362 DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid); 363 364 // Only change the status if it's still waiting on the icache access 365 // to return. 366 if (fetchStatus[tid] != IcacheWaitResponse || 367 pkt->req != memReq[tid] || 368 isSwitchedOut()) { 369 ++fetchIcacheSquashes; 370 delete pkt->req; 371 delete pkt; 372 return; 373 } 374 375 memcpy(cacheData[tid], pkt->getPtr<uint8_t *>(), cacheBlkSize); 376 cacheDataValid[tid] = true; 377 378 if (!drainPending) { 379 // Wake up the CPU (if it went to sleep and was waiting on 380 // this completion event). 381 cpu->wakeCPU(); 382 383 DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n", 384 tid); 385 386 switchToActive(); 387 } 388 389 // Only switch to IcacheAccessComplete if we're not stalled as well. 390 if (checkStall(tid)) { 391 fetchStatus[tid] = Blocked; 392 } else { 393 fetchStatus[tid] = IcacheAccessComplete; 394 } 395 396 // Reset the mem req to NULL. 397 delete pkt->req; 398 delete pkt; 399 memReq[tid] = NULL; 400} 401 402template <class Impl> 403bool 404DefaultFetch<Impl>::drain() 405{ 406 // Fetch is ready to drain at any time. 407 cpu->signalDrained(); 408 drainPending = true; 409 return true; 410} 411 412template <class Impl> 413void 414DefaultFetch<Impl>::resume() 415{ 416 drainPending = false; 417} 418 419template <class Impl> 420void 421DefaultFetch<Impl>::switchOut() 422{ 423 switchedOut = true; 424 // Branch predictor needs to have its state cleared. 425 branchPred.switchOut(); 426} 427 428template <class Impl> 429void 430DefaultFetch<Impl>::takeOverFrom() 431{ 432 // Reset all state 433 for (int i = 0; i < Impl::MaxThreads; ++i) { 434 stalls[i].decode = 0; 435 stalls[i].rename = 0; 436 stalls[i].iew = 0; 437 stalls[i].commit = 0; 438 PC[i] = cpu->readPC(i); 439 nextPC[i] = cpu->readNextPC(i); 440#if ISA_HAS_DELAY_SLOT 441 nextNPC[i] = cpu->readNextNPC(i); 442 delaySlotInfo[i].branchSeqNum = -1; 443 delaySlotInfo[i].numInsts = 0; 444 delaySlotInfo[i].targetAddr = 0; 445 delaySlotInfo[i].targetReady = false; 446#endif 447 fetchStatus[i] = Running; 448 } 449 numInst = 0; 450 wroteToTimeBuffer = false; 451 _status = Inactive; 452 switchedOut = false; 453 interruptPending = false; 454 branchPred.takeOverFrom(); 455} 456 457template <class Impl> 458void 459DefaultFetch<Impl>::wakeFromQuiesce() 460{ 461 DPRINTF(Fetch, "Waking up from quiesce\n"); 462 // Hopefully this is safe 463 // @todo: Allow other threads to wake from quiesce. 464 fetchStatus[0] = Running; 465} 466 467template <class Impl> 468inline void 469DefaultFetch<Impl>::switchToActive() 470{ 471 if (_status == Inactive) { 472 DPRINTF(Activity, "Activating stage.\n"); 473 474 cpu->activateStage(O3CPU::FetchIdx); 475 476 _status = Active; 477 } 478} 479 480template <class Impl> 481inline void 482DefaultFetch<Impl>::switchToInactive() 483{ 484 if (_status == Active) { 485 DPRINTF(Activity, "Deactivating stage.\n"); 486 487 cpu->deactivateStage(O3CPU::FetchIdx); 488 489 _status = Inactive; 490 } 491} 492 493template <class Impl> 494bool 495DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC, 496 Addr &next_NPC) 497{ 498 // Do branch prediction check here. 499 // A bit of a misnomer...next_PC is actually the current PC until 500 // this function updates it. 501 bool predict_taken; 502 503 if (!inst->isControl()) { 504#if ISA_HAS_DELAY_SLOT 505 next_PC = next_NPC; 506 next_NPC = next_NPC + instSize; 507 inst->setPredTarg(next_PC, next_NPC); 508#else 509 next_PC = next_PC + instSize; 510 inst->setPredTarg(next_PC, next_PC + sizeof(TheISA::MachInst)); 511#endif 512 inst->setPredTaken(false); 513 return false; 514 } 515 516 int tid = inst->threadNumber; 517#if ISA_HAS_DELAY_SLOT 518 Addr pred_PC = next_PC; 519 predict_taken = branchPred.predict(inst, pred_PC, tid); 520 521 if (predict_taken) { 522 DPRINTF(Fetch, "[tid:%i]: Branch predicted to be taken.\n", tid); 523 } else { 524 DPRINTF(Fetch, "[tid:%i]: Branch predicted to be not taken.\n", tid); 525 } 526 527 next_PC = next_NPC; 528 if (predict_taken) { 529 next_NPC = pred_PC; 530 // Update delay slot info 531 ++delaySlotInfo[tid].numInsts; 532 delaySlotInfo[tid].targetAddr = pred_PC; 533 DPRINTF(Fetch, "[tid:%i]: %i delay slot inst(s) to process.\n", tid, 534 delaySlotInfo[tid].numInsts); 535 } else { 536 next_NPC = next_NPC + instSize; 537 } 538#else 539 predict_taken = branchPred.predict(inst, next_PC, tid); 540#endif 541 DPRINTF(Fetch, "[tid:%i]: Branch predicted to go to %#x and then %#x.\n", 542 tid, next_PC, next_NPC); 543 inst->setPredTarg(next_PC, next_NPC); 544 inst->setPredTaken(predict_taken); 545 546 ++fetchedBranches; 547 548 if (predict_taken) { 549 ++predictedBranches; 550 } 551 552 return predict_taken; 553} 554 555template <class Impl> 556bool 557DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid) 558{ 559 Fault fault = NoFault; 560 561 //AlphaDep 562 if (cacheBlocked) { 563 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n", 564 tid); 565 return false; 566 } else if (isSwitchedOut()) { 567 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, switched out\n", 568 tid); 569 return false; 570 } else if (interruptPending && !(fetch_PC & 0x3)) { 571 // Hold off fetch from getting new instructions when: 572 // Cache is blocked, or 573 // while an interrupt is pending and we're not in PAL mode, or 574 // fetch is switched out. 575 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n", 576 tid); 577 return false; 578 } 579 580 // Align the fetch PC so it's at the start of a cache block. 581 Addr block_PC = icacheBlockAlignPC(fetch_PC); 582 583 // If we've already got the block, no need to try to fetch it again. 584 if (cacheDataValid[tid] && block_PC == cacheDataPC[tid]) { 585 return true; 586 } 587 588 // Setup the memReq to do a read of the first instruction's address. 589 // Set the appropriate read size and flags as well. 590 // Build request here. 591 RequestPtr mem_req = new Request(tid, block_PC, cacheBlkSize, 0, 592 fetch_PC, cpu->readCpuId(), tid); 593 594 memReq[tid] = mem_req; 595 596 // Translate the instruction request. 597 fault = cpu->translateInstReq(mem_req, cpu->thread[tid]); 598 599 // In the case of faults, the fetch stage may need to stall and wait 600 // for the ITB miss to be handled. 601 602 // If translation was successful, attempt to read the first 603 // instruction. 604 if (fault == NoFault) { 605#if 0 606 if (cpu->system->memctrl->badaddr(memReq[tid]->paddr) || 607 memReq[tid]->isUncacheable()) { 608 DPRINTF(Fetch, "Fetch: Bad address %#x (hopefully on a " 609 "misspeculating path)!", 610 memReq[tid]->paddr); 611 ret_fault = TheISA::genMachineCheckFault(); 612 return false; 613 } 614#endif 615 616 // Build packet here. 617 PacketPtr data_pkt = new Packet(mem_req, 618 Packet::ReadReq, Packet::Broadcast); 619 data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]); 620 621 cacheDataPC[tid] = block_PC; 622 cacheDataValid[tid] = false; 623 624 DPRINTF(Fetch, "Fetch: Doing instruction read.\n"); 625 626 fetchedCacheLines++; 627 628 // Now do the timing access to see whether or not the instruction 629 // exists within the cache. 630 if (!icachePort->sendTiming(data_pkt)) { 631 if (data_pkt->result == Packet::BadAddress) { 632 fault = TheISA::genMachineCheckFault(); 633 delete mem_req; 634 memReq[tid] = NULL; 635 } 636 assert(retryPkt == NULL); 637 assert(retryTid == -1); 638 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid); 639 fetchStatus[tid] = IcacheWaitRetry; 640 retryPkt = data_pkt; 641 retryTid = tid; 642 cacheBlocked = true; 643 return false; 644 } 645 646 DPRINTF(Fetch, "[tid:%i]: Doing cache access.\n", tid); 647 648 lastIcacheStall[tid] = curTick; 649 650 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache " 651 "response.\n", tid); 652 653 fetchStatus[tid] = IcacheWaitResponse; 654 } else { 655 delete mem_req; 656 memReq[tid] = NULL; 657 } 658 659 ret_fault = fault; 660 return true; 661} 662 663template <class Impl> 664inline void 665DefaultFetch<Impl>::doSquash(const Addr &new_PC, 666 const Addr &new_NPC, unsigned tid) 667{ 668 DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x, NPC to: %#x.\n", 669 tid, new_PC, new_NPC); 670 671 PC[tid] = new_PC; 672 nextPC[tid] = new_NPC; 673 nextNPC[tid] = new_NPC + instSize; 674 675 // Clear the icache miss if it's outstanding. 676 if (fetchStatus[tid] == IcacheWaitResponse) { 677 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n", 678 tid); 679 memReq[tid] = NULL; 680 } 681 682 // Get rid of the retrying packet if it was from this thread. 683 if (retryTid == tid) { 684 assert(cacheBlocked); 685 cacheBlocked = false; 686 retryTid = -1; 687 delete retryPkt->req; 688 delete retryPkt; 689 retryPkt = NULL; 690 } 691 692 fetchStatus[tid] = Squashing; 693 694 ++fetchSquashCycles; 695} 696 697template<class Impl> 698void 699DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC, const Addr &new_NPC, 700 const InstSeqNum &seq_num, 701 unsigned tid) 702{ 703 DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid); 704 705 doSquash(new_PC, new_NPC, tid); 706 707#if ISA_HAS_DELAY_SLOT 708 if (seq_num <= delaySlotInfo[tid].branchSeqNum) { 709 delaySlotInfo[tid].numInsts = 0; 710 delaySlotInfo[tid].targetAddr = 0; 711 delaySlotInfo[tid].targetReady = false; 712 } 713#endif 714 715 // Tell the CPU to remove any instructions that are in flight between 716 // fetch and decode. 717 cpu->removeInstsUntil(seq_num, tid); 718} 719 720template<class Impl> 721bool 722DefaultFetch<Impl>::checkStall(unsigned tid) const 723{ 724 bool ret_val = false; 725 726 if (cpu->contextSwitch) { 727 DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid); 728 ret_val = true; 729 } else if (stalls[tid].decode) { 730 DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid); 731 ret_val = true; 732 } else if (stalls[tid].rename) { 733 DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid); 734 ret_val = true; 735 } else if (stalls[tid].iew) { 736 DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid); 737 ret_val = true; 738 } else if (stalls[tid].commit) { 739 DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid); 740 ret_val = true; 741 } 742 743 return ret_val; 744} 745 746template<class Impl> 747typename DefaultFetch<Impl>::FetchStatus 748DefaultFetch<Impl>::updateFetchStatus() 749{ 750 //Check Running 751 std::list<unsigned>::iterator threads = (*activeThreads).begin(); 752 753 while (threads != (*activeThreads).end()) { 754 755 unsigned tid = *threads++; 756 757 if (fetchStatus[tid] == Running || 758 fetchStatus[tid] == Squashing || 759 fetchStatus[tid] == IcacheAccessComplete) { 760 761 if (_status == Inactive) { 762 DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid); 763 764 if (fetchStatus[tid] == IcacheAccessComplete) { 765 DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache" 766 "completion\n",tid); 767 } 768 769 cpu->activateStage(O3CPU::FetchIdx); 770 } 771 772 return Active; 773 } 774 } 775 776 // Stage is switching from active to inactive, notify CPU of it. 777 if (_status == Active) { 778 DPRINTF(Activity, "Deactivating stage.\n"); 779 780 cpu->deactivateStage(O3CPU::FetchIdx); 781 } 782 783 return Inactive; 784} 785 786template <class Impl> 787void 788DefaultFetch<Impl>::squash(const Addr &new_PC, const Addr &new_NPC, 789 const InstSeqNum &seq_num, 790 bool squash_delay_slot, unsigned tid) 791{ 792 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid); 793 794 doSquash(new_PC, new_NPC, tid); 795 796#if ISA_HAS_DELAY_SLOT 797 if (seq_num <= delaySlotInfo[tid].branchSeqNum) { 798 delaySlotInfo[tid].numInsts = 0; 799 delaySlotInfo[tid].targetAddr = 0; 800 delaySlotInfo[tid].targetReady = false; 801 } 802 803 // Tell the CPU to remove any instructions that are not in the ROB. 804 cpu->removeInstsNotInROB(tid, squash_delay_slot, seq_num); 805#else 806 // Tell the CPU to remove any instructions that are not in the ROB. 807 cpu->removeInstsNotInROB(tid, true, 0); 808#endif 809} 810 811template <class Impl> 812void 813DefaultFetch<Impl>::tick() 814{ 815 std::list<unsigned>::iterator threads = (*activeThreads).begin(); 816 bool status_change = false; 817 818 wroteToTimeBuffer = false; 819 820 while (threads != (*activeThreads).end()) { 821 unsigned tid = *threads++; 822 823 // Check the signals for each thread to determine the proper status 824 // for each thread. 825 bool updated_status = checkSignalsAndUpdate(tid); 826 status_change = status_change || updated_status; 827 } 828 829 DPRINTF(Fetch, "Running stage.\n"); 830 831 // Reset the number of the instruction we're fetching. 832 numInst = 0; 833 834#if FULL_SYSTEM 835 if (fromCommit->commitInfo[0].interruptPending) { 836 interruptPending = true; 837 } 838 839 if (fromCommit->commitInfo[0].clearInterrupt) { 840 interruptPending = false; 841 } 842#endif 843 844 for (threadFetched = 0; threadFetched < numFetchingThreads; 845 threadFetched++) { 846 // Fetch each of the actively fetching threads. 847 fetch(status_change); 848 } 849 850 // Record number of instructions fetched this cycle for distribution. 851 fetchNisnDist.sample(numInst); 852 853 if (status_change) { 854 // Change the fetch stage status if there was a status change. 855 _status = updateFetchStatus(); 856 } 857 858 // If there was activity this cycle, inform the CPU of it. 859 if (wroteToTimeBuffer || cpu->contextSwitch) { 860 DPRINTF(Activity, "Activity this cycle.\n"); 861 862 cpu->activityThisCycle(); 863 } 864} 865 866template <class Impl> 867bool 868DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid) 869{ 870 // Update the per thread stall statuses. 871 if (fromDecode->decodeBlock[tid]) { 872 stalls[tid].decode = true; 873 } 874 875 if (fromDecode->decodeUnblock[tid]) { 876 assert(stalls[tid].decode); 877 assert(!fromDecode->decodeBlock[tid]); 878 stalls[tid].decode = false; 879 } 880 881 if (fromRename->renameBlock[tid]) { 882 stalls[tid].rename = true; 883 } 884 885 if (fromRename->renameUnblock[tid]) { 886 assert(stalls[tid].rename); 887 assert(!fromRename->renameBlock[tid]); 888 stalls[tid].rename = false; 889 } 890 891 if (fromIEW->iewBlock[tid]) { 892 stalls[tid].iew = true; 893 } 894 895 if (fromIEW->iewUnblock[tid]) { 896 assert(stalls[tid].iew); 897 assert(!fromIEW->iewBlock[tid]); 898 stalls[tid].iew = false; 899 } 900 901 if (fromCommit->commitBlock[tid]) { 902 stalls[tid].commit = true; 903 } 904 905 if (fromCommit->commitUnblock[tid]) { 906 assert(stalls[tid].commit); 907 assert(!fromCommit->commitBlock[tid]); 908 stalls[tid].commit = false; 909 } 910 911 // Check squash signals from commit. 912 if (fromCommit->commitInfo[tid].squash) { 913 914 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash " 915 "from commit.\n",tid); 916 917#if ISA_HAS_DELAY_SLOT 918 InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].bdelayDoneSeqNum; 919#else 920 InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].doneSeqNum; 921#endif 922 // In any case, squash. 923 squash(fromCommit->commitInfo[tid].nextPC, 924 fromCommit->commitInfo[tid].nextNPC, 925 doneSeqNum, 926 fromCommit->commitInfo[tid].squashDelaySlot, 927 tid); 928 929 // Also check if there's a mispredict that happened. 930 if (fromCommit->commitInfo[tid].branchMispredict) { 931 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum, 932 fromCommit->commitInfo[tid].nextPC, 933 fromCommit->commitInfo[tid].branchTaken, 934 tid); 935 } else { 936 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum, 937 tid); 938 } 939 940 return true; 941 } else if (fromCommit->commitInfo[tid].doneSeqNum) { 942 // Update the branch predictor if it wasn't a squashed instruction 943 // that was broadcasted. 944 branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid); 945 } 946 947 // Check ROB squash signals from commit. 948 if (fromCommit->commitInfo[tid].robSquashing) { 949 DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid); 950 951 // Continue to squash. 952 fetchStatus[tid] = Squashing; 953 954 return true; 955 } 956 957 // Check squash signals from decode. 958 if (fromDecode->decodeInfo[tid].squash) { 959 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash " 960 "from decode.\n",tid); 961 962 // Update the branch predictor. 963 if (fromDecode->decodeInfo[tid].branchMispredict) { 964 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum, 965 fromDecode->decodeInfo[tid].nextPC, 966 fromDecode->decodeInfo[tid].branchTaken, 967 tid); 968 } else { 969 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum, 970 tid); 971 } 972 973 if (fetchStatus[tid] != Squashing) { 974 975#if ISA_HAS_DELAY_SLOT 976 InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].bdelayDoneSeqNum; 977#else 978 InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].doneSeqNum; 979#endif 980 // Squash unless we're already squashing 981 squashFromDecode(fromDecode->decodeInfo[tid].nextPC, 982 fromDecode->decodeInfo[tid].nextNPC, 983 doneSeqNum, 984 tid); 985 986 return true; 987 } 988 } 989 990 if (checkStall(tid) && 991 fetchStatus[tid] != IcacheWaitResponse && 992 fetchStatus[tid] != IcacheWaitRetry) { 993 DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid); 994 995 fetchStatus[tid] = Blocked; 996 997 return true; 998 } 999 1000 if (fetchStatus[tid] == Blocked || 1001 fetchStatus[tid] == Squashing) { 1002 // Switch status to running if fetch isn't being told to block or 1003 // squash this cycle. 1004 DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n", 1005 tid); 1006 1007 fetchStatus[tid] = Running; 1008 1009 return true; 1010 } 1011 1012 // If we've reached this point, we have not gotten any signals that 1013 // cause fetch to change its status. Fetch remains the same as before. 1014 return false; 1015} 1016 1017template<class Impl> 1018void 1019DefaultFetch<Impl>::fetch(bool &status_change) 1020{ 1021 ////////////////////////////////////////// 1022 // Start actual fetch 1023 ////////////////////////////////////////// 1024 int tid = getFetchingThread(fetchPolicy); 1025 1026 if (tid == -1 || drainPending) { 1027 DPRINTF(Fetch,"There are no more threads available to fetch from.\n"); 1028 1029 // Breaks looping condition in tick() 1030 threadFetched = numFetchingThreads; 1031 return; 1032 } 1033 1034 DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid); 1035 1036 // The current PC. 1037 Addr &fetch_PC = PC[tid]; 1038 1039 Addr &fetch_NPC = nextPC[tid]; 1040 1041 // Fault code for memory access. 1042 Fault fault = NoFault; 1043 1044 // If returning from the delay of a cache miss, then update the status 1045 // to running, otherwise do the cache access. Possibly move this up 1046 // to tick() function. 1047 if (fetchStatus[tid] == IcacheAccessComplete) { 1048 DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n", 1049 tid); 1050 1051 fetchStatus[tid] = Running; 1052 status_change = true; 1053 } else if (fetchStatus[tid] == Running) { 1054 DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read " 1055 "instruction, starting at PC %08p.\n", 1056 tid, fetch_PC); 1057 1058 bool fetch_success = fetchCacheLine(fetch_PC, fault, tid); 1059 if (!fetch_success) { 1060 if (cacheBlocked) { 1061 ++icacheStallCycles; 1062 } else { 1063 ++fetchMiscStallCycles; 1064 } 1065 return; 1066 } 1067 } else { 1068 if (fetchStatus[tid] == Idle) { 1069 ++fetchIdleCycles; 1070 DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid); 1071 } else if (fetchStatus[tid] == Blocked) { 1072 ++fetchBlockedCycles; 1073 DPRINTF(Fetch, "[tid:%i]: Fetch is blocked!\n", tid); 1074 } else if (fetchStatus[tid] == Squashing) { 1075 ++fetchSquashCycles; 1076 DPRINTF(Fetch, "[tid:%i]: Fetch is squashing!\n", tid); 1077 } else if (fetchStatus[tid] == IcacheWaitResponse) { 1078 ++icacheStallCycles; 1079 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n", tid); 1080 } 1081 1082 // Status is Idle, Squashing, Blocked, or IcacheWaitResponse, so 1083 // fetch should do nothing. 1084 return; 1085 } 1086 1087 ++fetchCycles; 1088 1089 // If we had a stall due to an icache miss, then return. 1090 if (fetchStatus[tid] == IcacheWaitResponse) { 1091 ++icacheStallCycles; 1092 status_change = true; 1093 return; 1094 } 1095 1096 Addr next_PC = fetch_PC; 1097 Addr next_NPC = fetch_NPC; 1098 1099 InstSeqNum inst_seq; 1100 MachInst inst; 1101 ExtMachInst ext_inst; 1102 // @todo: Fix this hack. 1103 unsigned offset = (fetch_PC & cacheBlkMask) & ~3; 1104 1105 if (fault == NoFault) { 1106 // If the read of the first instruction was successful, then grab the 1107 // instructions from the rest of the cache line and put them into the 1108 // queue heading to decode. 1109 1110 DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to " 1111 "decode.\n",tid); 1112 1113 // Need to keep track of whether or not a predicted branch 1114 // ended this fetch block. 1115 bool predicted_branch = false; 1116 1117 for (; 1118 offset < cacheBlkSize && 1119 numInst < fetchWidth && 1120 !predicted_branch; 1121 ++numInst) { 1122 1123 // If we're branching after this instruction, quite fetching 1124 // from the same block then. 1125 predicted_branch = 1126 (fetch_PC + sizeof(TheISA::MachInst) != fetch_NPC); 1127 1128 // Get a sequence number. 1129 inst_seq = cpu->getAndIncrementInstSeq(); 1130 1131 // Make sure this is a valid index. 1132 assert(offset <= cacheBlkSize - instSize); 1133 1134 // Get the instruction from the array of the cache line. 1135 inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *> 1136 (&cacheData[tid][offset])); 1137 1138#if THE_ISA == ALPHA_ISA 1139 ext_inst = TheISA::makeExtMI(inst, fetch_PC); 1140#elif THE_ISA == SPARC_ISA 1141 ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC()); 1142#elif THE_ISA == MIPS_ISA 1143 ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC()); 1144#endif 1145 1146 // Create a new DynInst from the instruction fetched. 1147 DynInstPtr instruction = new DynInst(ext_inst, 1148 fetch_PC, fetch_NPC, 1149 next_PC, next_NPC, 1150 inst_seq, cpu); 1151 instruction->setTid(tid); 1152 1153 instruction->setASID(tid); 1154 1155 instruction->setThreadState(cpu->thread[tid]); 1156 1157 DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created " 1158 "[sn:%lli]\n", 1159 tid, instruction->readPC(), inst_seq); 1160 1161 DPRINTF(Fetch, "[tid:%i]: MachInst is %#x\n", tid, ext_inst); 1162 1163 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", 1164 tid, instruction->staticInst->disassemble(fetch_PC)); 1165 1166 instruction->traceData = 1167 Trace::getInstRecord(curTick, cpu->tcBase(tid), 1168 instruction->staticInst, 1169 instruction->readPC()); 1170 1171 lookupAndUpdateNextPC(instruction, next_PC, next_NPC); 1172 1173 // Add instruction to the CPU's list of instructions. 1174 instruction->setInstListIt(cpu->addInst(instruction)); 1175 1176 // Write the instruction to the first slot in the queue 1177 // that heads to decode. 1178 toDecode->insts[numInst] = instruction; 1179 1180 toDecode->size++; 1181 1182 // Increment stat of fetched instructions. 1183 ++fetchedInsts; 1184 1185 // Move to the next instruction, unless we have a branch. 1186 fetch_PC = next_PC; 1187 fetch_NPC = next_NPC; 1188 1189 if (instruction->isQuiesce()) { 1190 DPRINTF(Fetch, "Quiesce instruction encountered, halting fetch!", 1191 curTick); 1192 fetchStatus[tid] = QuiescePending; 1193 ++numInst; 1194 status_change = true; 1195 break; 1196 } 1197 1198 offset += instSize; 1199 } 1200 1201 if (offset >= cacheBlkSize) { 1202 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache " 1203 "block.\n", tid); 1204 } else if (numInst >= fetchWidth) { 1205 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth " 1206 "for this cycle.\n", tid); 1207 } else if (predicted_branch) { 1208 DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch " 1209 "instruction encountered.\n", tid); 1210 } 1211 } 1212 1213 if (numInst > 0) { 1214 wroteToTimeBuffer = true; 1215 } 1216 1217 // Now that fetching is completed, update the PC to signify what the next 1218 // cycle will be. 1219 if (fault == NoFault) { 1220#if ISA_HAS_DELAY_SLOT 1221 if (delaySlotInfo[tid].targetReady && 1222 delaySlotInfo[tid].numInsts == 0) { 1223 // Set PC to target 1224 PC[tid] = next_PC; 1225 nextPC[tid] = next_NPC; 1226 nextNPC[tid] = next_NPC + instSize; 1227 1228 delaySlotInfo[tid].targetReady = false; 1229 } else { 1230 PC[tid] = next_PC; 1231 nextPC[tid] = next_NPC; 1232 nextNPC[tid] = next_NPC + instSize; 1233 } 1234 1235 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, PC[tid]); 1236#else 1237 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n",tid, next_PC); 1238 PC[tid] = next_PC; 1239 nextPC[tid] = next_PC + instSize; 1240#endif 1241 } else { 1242 // We shouldn't be in an icache miss and also have a fault (an ITB 1243 // miss) 1244 if (fetchStatus[tid] == IcacheWaitResponse) { 1245 panic("Fetch should have exited prior to this!"); 1246 } 1247 1248 // Send the fault to commit. This thread will not do anything 1249 // until commit handles the fault. The only other way it can 1250 // wake up is if a squash comes along and changes the PC. 1251#if FULL_SYSTEM 1252 assert(numInst != fetchWidth); 1253 // Get a sequence number. 1254 inst_seq = cpu->getAndIncrementInstSeq(); 1255 // We will use a nop in order to carry the fault. 1256 ext_inst = TheISA::NoopMachInst; 1257 1258 // Create a new DynInst from the dummy nop. 1259 DynInstPtr instruction = new DynInst(ext_inst, fetch_PC, 1260 next_PC, 1261 inst_seq, cpu); 1262 instruction->setPredTarg(next_PC + instSize); 1263 instruction->setTid(tid); 1264 1265 instruction->setASID(tid); 1266 1267 instruction->setThreadState(cpu->thread[tid]); 1268 1269 instruction->traceData = NULL; 1270 1271 instruction->setInstListIt(cpu->addInst(instruction)); 1272 1273 instruction->fault = fault; 1274 1275 toDecode->insts[numInst] = instruction; 1276 toDecode->size++; 1277 1278 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid); 1279 1280 fetchStatus[tid] = TrapPending; 1281 status_change = true; 1282#else // !FULL_SYSTEM 1283 fetchStatus[tid] = TrapPending; 1284 status_change = true; 1285 1286#endif // FULL_SYSTEM 1287 DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %08p", 1288 tid, fault->name(), PC[tid]); 1289 } 1290} 1291 1292template<class Impl> 1293void 1294DefaultFetch<Impl>::recvRetry() 1295{ 1296 if (retryPkt != NULL) { 1297 assert(cacheBlocked); 1298 assert(retryTid != -1); 1299 assert(fetchStatus[retryTid] == IcacheWaitRetry); 1300 1301 if (icachePort->sendTiming(retryPkt)) { 1302 fetchStatus[retryTid] = IcacheWaitResponse; 1303 retryPkt = NULL; 1304 retryTid = -1; 1305 cacheBlocked = false; 1306 } 1307 } else { 1308 assert(retryTid == -1); 1309 // Access has been squashed since it was sent out. Just clear 1310 // the cache being blocked. 1311 cacheBlocked = false; 1312 } 1313} 1314 1315/////////////////////////////////////// 1316// // 1317// SMT FETCH POLICY MAINTAINED HERE // 1318// // 1319/////////////////////////////////////// 1320template<class Impl> 1321int 1322DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority) 1323{ 1324 if (numThreads > 1) { 1325 switch (fetch_priority) { 1326 1327 case SingleThread: 1328 return 0; 1329 1330 case RoundRobin: 1331 return roundRobin(); 1332 1333 case IQ: 1334 return iqCount(); 1335 1336 case LSQ: 1337 return lsqCount(); 1338 1339 case Branch: 1340 return branchCount(); 1341 1342 default: 1343 return -1; 1344 } 1345 } else { 1346 int tid = *((*activeThreads).begin()); 1347 1348 if (fetchStatus[tid] == Running || 1349 fetchStatus[tid] == IcacheAccessComplete || 1350 fetchStatus[tid] == Idle) { 1351 return tid; 1352 } else { 1353 return -1; 1354 } 1355 } 1356 1357} 1358 1359 1360template<class Impl> 1361int 1362DefaultFetch<Impl>::roundRobin() 1363{ 1364 std::list<unsigned>::iterator pri_iter = priorityList.begin(); 1365 std::list<unsigned>::iterator end = priorityList.end(); 1366 1367 int high_pri; 1368 1369 while (pri_iter != end) { 1370 high_pri = *pri_iter; 1371 1372 assert(high_pri <= numThreads); 1373 1374 if (fetchStatus[high_pri] == Running || 1375 fetchStatus[high_pri] == IcacheAccessComplete || 1376 fetchStatus[high_pri] == Idle) { 1377 1378 priorityList.erase(pri_iter); 1379 priorityList.push_back(high_pri); 1380 1381 return high_pri; 1382 } 1383 1384 pri_iter++; 1385 } 1386 1387 return -1; 1388} 1389 1390template<class Impl> 1391int 1392DefaultFetch<Impl>::iqCount() 1393{ 1394 std::priority_queue<unsigned> PQ; 1395 1396 std::list<unsigned>::iterator threads = (*activeThreads).begin(); 1397 1398 while (threads != (*activeThreads).end()) { 1399 unsigned tid = *threads++; 1400 1401 PQ.push(fromIEW->iewInfo[tid].iqCount); 1402 } 1403 1404 while (!PQ.empty()) { 1405 1406 unsigned high_pri = PQ.top(); 1407 1408 if (fetchStatus[high_pri] == Running || 1409 fetchStatus[high_pri] == IcacheAccessComplete || 1410 fetchStatus[high_pri] == Idle) 1411 return high_pri; 1412 else 1413 PQ.pop(); 1414 1415 } 1416 1417 return -1; 1418} 1419 1420template<class Impl> 1421int 1422DefaultFetch<Impl>::lsqCount() 1423{ 1424 std::priority_queue<unsigned> PQ; 1425 1426 1427 std::list<unsigned>::iterator threads = (*activeThreads).begin(); 1428 1429 while (threads != (*activeThreads).end()) { 1430 unsigned tid = *threads++; 1431 1432 PQ.push(fromIEW->iewInfo[tid].ldstqCount); 1433 } 1434 1435 while (!PQ.empty()) { 1436 1437 unsigned high_pri = PQ.top(); 1438 1439 if (fetchStatus[high_pri] == Running || 1440 fetchStatus[high_pri] == IcacheAccessComplete || 1441 fetchStatus[high_pri] == Idle) 1442 return high_pri; 1443 else 1444 PQ.pop(); 1445 1446 } 1447 1448 return -1; 1449} 1450 1451template<class Impl> 1452int 1453DefaultFetch<Impl>::branchCount() 1454{ 1455 std::list<unsigned>::iterator threads = (*activeThreads).begin(); 1456 panic("Branch Count Fetch policy unimplemented\n"); 1457 return *threads; 1458} 1459