fetch_impl.hh revision 3484:9b7ac1654430 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 *          Korey Sewell
30 */
31
32#include "config/use_checker.hh"
33
34#include "arch/isa_traits.hh"
35#include "arch/utility.hh"
36#include "cpu/checker/cpu.hh"
37#include "cpu/exetrace.hh"
38#include "cpu/o3/fetch.hh"
39#include "mem/packet.hh"
40#include "mem/request.hh"
41#include "sim/byteswap.hh"
42#include "sim/host.hh"
43#include "sim/root.hh"
44
45#if FULL_SYSTEM
46#include "arch/tlb.hh"
47#include "arch/vtophys.hh"
48#include "base/remote_gdb.hh"
49#include "sim/system.hh"
50#endif // FULL_SYSTEM
51
52#include <algorithm>
53
54template<class Impl>
55Tick
56DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt)
57{
58    panic("DefaultFetch doesn't expect recvAtomic callback!");
59    return curTick;
60}
61
62template<class Impl>
63void
64DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
65{
66    warn("Default fetch doesn't update it's state from a functional call.");
67}
68
69template<class Impl>
70void
71DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status)
72{
73    if (status == RangeChange)
74        return;
75
76    panic("DefaultFetch doesn't expect recvStatusChange callback!");
77}
78
79template<class Impl>
80bool
81DefaultFetch<Impl>::IcachePort::recvTiming(PacketPtr pkt)
82{
83    if (pkt->isResponse()) {
84        fetch->processCacheCompletion(pkt);
85    }
86    //else Snooped a coherence request, just return
87    return true;
88}
89
90template<class Impl>
91void
92DefaultFetch<Impl>::IcachePort::recvRetry()
93{
94    fetch->recvRetry();
95}
96
97template<class Impl>
98DefaultFetch<Impl>::DefaultFetch(Params *params)
99    : branchPred(params),
100      decodeToFetchDelay(params->decodeToFetchDelay),
101      renameToFetchDelay(params->renameToFetchDelay),
102      iewToFetchDelay(params->iewToFetchDelay),
103      commitToFetchDelay(params->commitToFetchDelay),
104      fetchWidth(params->fetchWidth),
105      cacheBlocked(false),
106      retryPkt(NULL),
107      retryTid(-1),
108      numThreads(params->numberOfThreads),
109      numFetchingThreads(params->smtNumFetchingThreads),
110      interruptPending(false),
111      drainPending(false),
112      switchedOut(false)
113{
114    if (numThreads > Impl::MaxThreads)
115        fatal("numThreads is not a valid value\n");
116
117    // Set fetch stage's status to inactive.
118    _status = Inactive;
119
120    std::string policy = params->smtFetchPolicy;
121
122    // Convert string to lowercase
123    std::transform(policy.begin(), policy.end(), policy.begin(),
124                   (int(*)(int)) tolower);
125
126    // Figure out fetch policy
127    if (policy == "singlethread") {
128        fetchPolicy = SingleThread;
129        if (numThreads > 1)
130            panic("Invalid Fetch Policy for a SMT workload.");
131    } else if (policy == "roundrobin") {
132        fetchPolicy = RoundRobin;
133        DPRINTF(Fetch, "Fetch policy set to Round Robin\n");
134    } else if (policy == "branch") {
135        fetchPolicy = Branch;
136        DPRINTF(Fetch, "Fetch policy set to Branch Count\n");
137    } else if (policy == "iqcount") {
138        fetchPolicy = IQ;
139        DPRINTF(Fetch, "Fetch policy set to IQ count\n");
140    } else if (policy == "lsqcount") {
141        fetchPolicy = LSQ;
142        DPRINTF(Fetch, "Fetch policy set to LSQ count\n");
143    } else {
144        fatal("Invalid Fetch Policy. Options Are: {SingleThread,"
145              " RoundRobin,LSQcount,IQcount}\n");
146    }
147
148    // Size of cache block.
149    cacheBlkSize = 64;
150
151    // Create mask to get rid of offset bits.
152    cacheBlkMask = (cacheBlkSize - 1);
153
154    for (int tid=0; tid < numThreads; tid++) {
155
156        fetchStatus[tid] = Running;
157
158        priorityList.push_back(tid);
159
160        memReq[tid] = NULL;
161
162        // Create space to store a cache line.
163        cacheData[tid] = new uint8_t[cacheBlkSize];
164        cacheDataPC[tid] = 0;
165        cacheDataValid[tid] = false;
166
167        delaySlotInfo[tid].branchSeqNum = -1;
168        delaySlotInfo[tid].numInsts = 0;
169        delaySlotInfo[tid].targetAddr = 0;
170        delaySlotInfo[tid].targetReady = false;
171
172        stalls[tid].decode = false;
173        stalls[tid].rename = false;
174        stalls[tid].iew = false;
175        stalls[tid].commit = false;
176    }
177
178    // Get the size of an instruction.
179    instSize = sizeof(TheISA::MachInst);
180}
181
182template <class Impl>
183std::string
184DefaultFetch<Impl>::name() const
185{
186    return cpu->name() + ".fetch";
187}
188
189template <class Impl>
190void
191DefaultFetch<Impl>::regStats()
192{
193    icacheStallCycles
194        .name(name() + ".icacheStallCycles")
195        .desc("Number of cycles fetch is stalled on an Icache miss")
196        .prereq(icacheStallCycles);
197
198    fetchedInsts
199        .name(name() + ".Insts")
200        .desc("Number of instructions fetch has processed")
201        .prereq(fetchedInsts);
202
203    fetchedBranches
204        .name(name() + ".Branches")
205        .desc("Number of branches that fetch encountered")
206        .prereq(fetchedBranches);
207
208    predictedBranches
209        .name(name() + ".predictedBranches")
210        .desc("Number of branches that fetch has predicted taken")
211        .prereq(predictedBranches);
212
213    fetchCycles
214        .name(name() + ".Cycles")
215        .desc("Number of cycles fetch has run and was not squashing or"
216              " blocked")
217        .prereq(fetchCycles);
218
219    fetchSquashCycles
220        .name(name() + ".SquashCycles")
221        .desc("Number of cycles fetch has spent squashing")
222        .prereq(fetchSquashCycles);
223
224    fetchIdleCycles
225        .name(name() + ".IdleCycles")
226        .desc("Number of cycles fetch was idle")
227        .prereq(fetchIdleCycles);
228
229    fetchBlockedCycles
230        .name(name() + ".BlockedCycles")
231        .desc("Number of cycles fetch has spent blocked")
232        .prereq(fetchBlockedCycles);
233
234    fetchedCacheLines
235        .name(name() + ".CacheLines")
236        .desc("Number of cache lines fetched")
237        .prereq(fetchedCacheLines);
238
239    fetchMiscStallCycles
240        .name(name() + ".MiscStallCycles")
241        .desc("Number of cycles fetch has spent waiting on interrupts, or "
242              "bad addresses, or out of MSHRs")
243        .prereq(fetchMiscStallCycles);
244
245    fetchIcacheSquashes
246        .name(name() + ".IcacheSquashes")
247        .desc("Number of outstanding Icache misses that were squashed")
248        .prereq(fetchIcacheSquashes);
249
250    fetchNisnDist
251        .init(/* base value */ 0,
252              /* last value */ fetchWidth,
253              /* bucket size */ 1)
254        .name(name() + ".rateDist")
255        .desc("Number of instructions fetched each cycle (Total)")
256        .flags(Stats::pdf);
257
258    idleRate
259        .name(name() + ".idleRate")
260        .desc("Percent of cycles fetch was idle")
261        .prereq(idleRate);
262    idleRate = fetchIdleCycles * 100 / cpu->numCycles;
263
264    branchRate
265        .name(name() + ".branchRate")
266        .desc("Number of branch fetches per cycle")
267        .flags(Stats::total);
268    branchRate = fetchedBranches / cpu->numCycles;
269
270    fetchRate
271        .name(name() + ".rate")
272        .desc("Number of inst fetches per cycle")
273        .flags(Stats::total);
274    fetchRate = fetchedInsts / cpu->numCycles;
275
276    branchPred.regStats();
277}
278
279template<class Impl>
280void
281DefaultFetch<Impl>::setCPU(O3CPU *cpu_ptr)
282{
283    DPRINTF(Fetch, "Setting the CPU pointer.\n");
284    cpu = cpu_ptr;
285
286    // Name is finally available, so create the port.
287    icachePort = new IcachePort(this);
288
289#if USE_CHECKER
290    if (cpu->checker) {
291        cpu->checker->setIcachePort(icachePort);
292    }
293#endif
294
295    // Schedule fetch to get the correct PC from the CPU
296    // scheduleFetchStartupEvent(1);
297
298    // Fetch needs to start fetching instructions at the very beginning,
299    // so it must start up in active state.
300    switchToActive();
301}
302
303template<class Impl>
304void
305DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
306{
307    DPRINTF(Fetch, "Setting the time buffer pointer.\n");
308    timeBuffer = time_buffer;
309
310    // Create wires to get information from proper places in time buffer.
311    fromDecode = timeBuffer->getWire(-decodeToFetchDelay);
312    fromRename = timeBuffer->getWire(-renameToFetchDelay);
313    fromIEW = timeBuffer->getWire(-iewToFetchDelay);
314    fromCommit = timeBuffer->getWire(-commitToFetchDelay);
315}
316
317template<class Impl>
318void
319DefaultFetch<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
320{
321    DPRINTF(Fetch, "Setting active threads list pointer.\n");
322    activeThreads = at_ptr;
323}
324
325template<class Impl>
326void
327DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
328{
329    DPRINTF(Fetch, "Setting the fetch queue pointer.\n");
330    fetchQueue = fq_ptr;
331
332    // Create wire to write information to proper place in fetch queue.
333    toDecode = fetchQueue->getWire(0);
334}
335
336template<class Impl>
337void
338DefaultFetch<Impl>::initStage()
339{
340    // Setup PC and nextPC with initial state.
341    for (int tid = 0; tid < numThreads; tid++) {
342        PC[tid] = cpu->readPC(tid);
343        nextPC[tid] = cpu->readNextPC(tid);
344#if ISA_HAS_DELAY_SLOT
345        nextNPC[tid] = cpu->readNextNPC(tid);
346#endif
347    }
348}
349
350template<class Impl>
351void
352DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
353{
354    unsigned tid = pkt->req->getThreadNum();
355
356    DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid);
357
358    // Only change the status if it's still waiting on the icache access
359    // to return.
360    if (fetchStatus[tid] != IcacheWaitResponse ||
361        pkt->req != memReq[tid] ||
362        isSwitchedOut()) {
363        ++fetchIcacheSquashes;
364        delete pkt->req;
365        delete pkt;
366        return;
367    }
368
369    memcpy(cacheData[tid], pkt->getPtr<uint8_t *>(), cacheBlkSize);
370    cacheDataValid[tid] = true;
371
372    if (!drainPending) {
373        // Wake up the CPU (if it went to sleep and was waiting on
374        // this completion event).
375        cpu->wakeCPU();
376
377        DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",
378                tid);
379
380        switchToActive();
381    }
382
383    // Only switch to IcacheAccessComplete if we're not stalled as well.
384    if (checkStall(tid)) {
385        fetchStatus[tid] = Blocked;
386    } else {
387        fetchStatus[tid] = IcacheAccessComplete;
388    }
389
390    // Reset the mem req to NULL.
391    delete pkt->req;
392    delete pkt;
393    memReq[tid] = NULL;
394}
395
396template <class Impl>
397bool
398DefaultFetch<Impl>::drain()
399{
400    // Fetch is ready to drain at any time.
401    cpu->signalDrained();
402    drainPending = true;
403    return true;
404}
405
406template <class Impl>
407void
408DefaultFetch<Impl>::resume()
409{
410    drainPending = false;
411}
412
413template <class Impl>
414void
415DefaultFetch<Impl>::switchOut()
416{
417    switchedOut = true;
418    // Branch predictor needs to have its state cleared.
419    branchPred.switchOut();
420}
421
422template <class Impl>
423void
424DefaultFetch<Impl>::takeOverFrom()
425{
426    // Reset all state
427    for (int i = 0; i < Impl::MaxThreads; ++i) {
428        stalls[i].decode = 0;
429        stalls[i].rename = 0;
430        stalls[i].iew = 0;
431        stalls[i].commit = 0;
432        PC[i] = cpu->readPC(i);
433        nextPC[i] = cpu->readNextPC(i);
434#if ISA_HAS_DELAY_SLOT
435        nextNPC[i] = cpu->readNextNPC(i);
436        delaySlotInfo[i].branchSeqNum = -1;
437        delaySlotInfo[i].numInsts = 0;
438        delaySlotInfo[i].targetAddr = 0;
439        delaySlotInfo[i].targetReady = false;
440#endif
441        fetchStatus[i] = Running;
442    }
443    numInst = 0;
444    wroteToTimeBuffer = false;
445    _status = Inactive;
446    switchedOut = false;
447    interruptPending = false;
448    branchPred.takeOverFrom();
449}
450
451template <class Impl>
452void
453DefaultFetch<Impl>::wakeFromQuiesce()
454{
455    DPRINTF(Fetch, "Waking up from quiesce\n");
456    // Hopefully this is safe
457    // @todo: Allow other threads to wake from quiesce.
458    fetchStatus[0] = Running;
459}
460
461template <class Impl>
462inline void
463DefaultFetch<Impl>::switchToActive()
464{
465    if (_status == Inactive) {
466        DPRINTF(Activity, "Activating stage.\n");
467
468        cpu->activateStage(O3CPU::FetchIdx);
469
470        _status = Active;
471    }
472}
473
474template <class Impl>
475inline void
476DefaultFetch<Impl>::switchToInactive()
477{
478    if (_status == Active) {
479        DPRINTF(Activity, "Deactivating stage.\n");
480
481        cpu->deactivateStage(O3CPU::FetchIdx);
482
483        _status = Inactive;
484    }
485}
486
487template <class Impl>
488bool
489DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC,
490                                          Addr &next_NPC)
491{
492    // Do branch prediction check here.
493    // A bit of a misnomer...next_PC is actually the current PC until
494    // this function updates it.
495    bool predict_taken;
496
497    if (!inst->isControl()) {
498#if ISA_HAS_DELAY_SLOT
499        Addr cur_PC = next_PC;
500        next_PC  = cur_PC + instSize;      //next_NPC;
501        next_NPC = cur_PC + (2 * instSize);//next_NPC + instSize;
502        inst->setPredTarg(next_NPC);
503#else
504        next_PC = next_PC + instSize;
505        inst->setPredTarg(next_PC);
506#endif
507        return false;
508    }
509
510    int tid = inst->threadNumber;
511#if ISA_HAS_DELAY_SLOT
512    Addr pred_PC = next_PC;
513    predict_taken = branchPred.predict(inst, pred_PC, tid);
514
515    if (predict_taken) {
516        DPRINTF(Fetch, "[tid:%i]: Branch predicted to be true.\n", tid);
517    } else {
518        DPRINTF(Fetch, "[tid:%i]: Branch predicted to be false.\n", tid);
519    }
520
521    if (predict_taken) {
522        next_PC = next_NPC;
523        next_NPC = pred_PC;
524
525        // Update delay slot info
526        ++delaySlotInfo[tid].numInsts;
527        delaySlotInfo[tid].targetAddr = pred_PC;
528        DPRINTF(Fetch, "[tid:%i]: %i delay slot inst(s) to process.\n", tid,
529                delaySlotInfo[tid].numInsts);
530    } else { // !predict_taken
531        if (inst->isCondDelaySlot()) {
532            next_PC = pred_PC;
533            // The delay slot is skipped here if there is on
534            // prediction
535        } else {
536            next_PC = next_NPC;
537            // No need to declare a delay slot here since
538            // there is no for the pred. target to jump
539        }
540
541        next_NPC = next_NPC + instSize;
542    }
543#else
544    predict_taken = branchPred.predict(inst, next_PC, tid);
545#endif
546
547    ++fetchedBranches;
548
549    if (predict_taken) {
550        ++predictedBranches;
551    }
552
553    return predict_taken;
554}
555
556template <class Impl>
557bool
558DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid)
559{
560    Fault fault = NoFault;
561
562#if FULL_SYSTEM
563    // Flag to say whether or not address is physical addr.
564    unsigned flags = cpu->inPalMode(fetch_PC) ? PHYSICAL : 0;
565#else
566    unsigned flags = 0;
567#endif // FULL_SYSTEM
568
569    if (cacheBlocked || isSwitchedOut() || (interruptPending && flags == 0)) {
570        // Hold off fetch from getting new instructions when:
571        // Cache is blocked, or
572        // while an interrupt is pending and we're not in PAL mode, or
573        // fetch is switched out.
574        return false;
575    }
576
577    // Align the fetch PC so it's at the start of a cache block.
578    fetch_PC = icacheBlockAlignPC(fetch_PC);
579
580    // If we've already got the block, no need to try to fetch it again.
581    if (cacheDataValid[tid] && fetch_PC == cacheDataPC[tid]) {
582        return true;
583    }
584
585    // Setup the memReq to do a read of the first instruction's address.
586    // Set the appropriate read size and flags as well.
587    // Build request here.
588    RequestPtr mem_req = new Request(tid, fetch_PC, cacheBlkSize, flags,
589                                     fetch_PC, cpu->readCpuId(), tid);
590
591    memReq[tid] = mem_req;
592
593    // Translate the instruction request.
594    fault = cpu->translateInstReq(mem_req, cpu->thread[tid]);
595
596    // In the case of faults, the fetch stage may need to stall and wait
597    // for the ITB miss to be handled.
598
599    // If translation was successful, attempt to read the first
600    // instruction.
601    if (fault == NoFault) {
602#if 0
603        if (cpu->system->memctrl->badaddr(memReq[tid]->paddr) ||
604            memReq[tid]->isUncacheable()) {
605            DPRINTF(Fetch, "Fetch: Bad address %#x (hopefully on a "
606                    "misspeculating path)!",
607                    memReq[tid]->paddr);
608            ret_fault = TheISA::genMachineCheckFault();
609            return false;
610        }
611#endif
612
613        // Build packet here.
614        PacketPtr data_pkt = new Packet(mem_req,
615                                        Packet::ReadReq, Packet::Broadcast);
616        data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]);
617
618        cacheDataPC[tid] = fetch_PC;
619        cacheDataValid[tid] = false;
620
621        DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
622
623        fetchedCacheLines++;
624
625        // Now do the timing access to see whether or not the instruction
626        // exists within the cache.
627        if (!icachePort->sendTiming(data_pkt)) {
628            if (data_pkt->result == Packet::BadAddress) {
629                fault = TheISA::genMachineCheckFault();
630                delete mem_req;
631                memReq[tid] = NULL;
632            }
633            assert(retryPkt == NULL);
634            assert(retryTid == -1);
635            DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
636            fetchStatus[tid] = IcacheWaitRetry;
637            retryPkt = data_pkt;
638            retryTid = tid;
639            cacheBlocked = true;
640            return false;
641        }
642
643        DPRINTF(Fetch, "[tid:%i]: Doing cache access.\n", tid);
644
645        lastIcacheStall[tid] = curTick;
646
647        DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
648                "response.\n", tid);
649
650        fetchStatus[tid] = IcacheWaitResponse;
651    } else {
652        delete mem_req;
653        memReq[tid] = NULL;
654    }
655
656    ret_fault = fault;
657    return true;
658}
659
660template <class Impl>
661inline void
662DefaultFetch<Impl>::doSquash(const Addr &new_PC, unsigned tid)
663{
664    DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x.\n",
665            tid, new_PC);
666
667    PC[tid] = new_PC;
668    nextPC[tid] = new_PC + instSize;
669    nextNPC[tid] = new_PC + (2 * instSize);
670
671    // Clear the icache miss if it's outstanding.
672    if (fetchStatus[tid] == IcacheWaitResponse) {
673        DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
674                tid);
675        memReq[tid] = NULL;
676    }
677
678    // Get rid of the retrying packet if it was from this thread.
679    if (retryTid == tid) {
680        assert(cacheBlocked);
681        cacheBlocked = false;
682        retryTid = -1;
683        delete retryPkt->req;
684        delete retryPkt;
685        retryPkt = NULL;
686    }
687
688    fetchStatus[tid] = Squashing;
689
690    ++fetchSquashCycles;
691}
692
693template<class Impl>
694void
695DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC,
696                                     const InstSeqNum &seq_num,
697                                     unsigned tid)
698{
699    DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid);
700
701    doSquash(new_PC, tid);
702
703#if ISA_HAS_DELAY_SLOT
704    if (seq_num <=  delaySlotInfo[tid].branchSeqNum) {
705        delaySlotInfo[tid].numInsts = 0;
706        delaySlotInfo[tid].targetAddr = 0;
707        delaySlotInfo[tid].targetReady = false;
708    }
709#endif
710
711    // Tell the CPU to remove any instructions that are in flight between
712    // fetch and decode.
713    cpu->removeInstsUntil(seq_num, tid);
714}
715
716template<class Impl>
717bool
718DefaultFetch<Impl>::checkStall(unsigned tid) const
719{
720    bool ret_val = false;
721
722    if (cpu->contextSwitch) {
723        DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid);
724        ret_val = true;
725    } else if (stalls[tid].decode) {
726        DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid);
727        ret_val = true;
728    } else if (stalls[tid].rename) {
729        DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid);
730        ret_val = true;
731    } else if (stalls[tid].iew) {
732        DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid);
733        ret_val = true;
734    } else if (stalls[tid].commit) {
735        DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid);
736        ret_val = true;
737    }
738
739    return ret_val;
740}
741
742template<class Impl>
743typename DefaultFetch<Impl>::FetchStatus
744DefaultFetch<Impl>::updateFetchStatus()
745{
746    //Check Running
747    std::list<unsigned>::iterator threads = (*activeThreads).begin();
748
749    while (threads != (*activeThreads).end()) {
750
751        unsigned tid = *threads++;
752
753        if (fetchStatus[tid] == Running ||
754            fetchStatus[tid] == Squashing ||
755            fetchStatus[tid] == IcacheAccessComplete) {
756
757            if (_status == Inactive) {
758                DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid);
759
760                if (fetchStatus[tid] == IcacheAccessComplete) {
761                    DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache"
762                            "completion\n",tid);
763                }
764
765                cpu->activateStage(O3CPU::FetchIdx);
766            }
767
768            return Active;
769        }
770    }
771
772    // Stage is switching from active to inactive, notify CPU of it.
773    if (_status == Active) {
774        DPRINTF(Activity, "Deactivating stage.\n");
775
776        cpu->deactivateStage(O3CPU::FetchIdx);
777    }
778
779    return Inactive;
780}
781
782template <class Impl>
783void
784DefaultFetch<Impl>::squash(const Addr &new_PC, const InstSeqNum &seq_num,
785                           bool squash_delay_slot, unsigned tid)
786{
787    DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid);
788
789    doSquash(new_PC, tid);
790
791#if ISA_HAS_DELAY_SLOT
792    if (seq_num <=  delaySlotInfo[tid].branchSeqNum) {
793        delaySlotInfo[tid].numInsts = 0;
794        delaySlotInfo[tid].targetAddr = 0;
795        delaySlotInfo[tid].targetReady = false;
796    }
797
798    // Tell the CPU to remove any instructions that are not in the ROB.
799    cpu->removeInstsNotInROB(tid, squash_delay_slot, seq_num);
800#else
801    // Tell the CPU to remove any instructions that are not in the ROB.
802    cpu->removeInstsNotInROB(tid, true, 0);
803#endif
804}
805
806template <class Impl>
807void
808DefaultFetch<Impl>::tick()
809{
810    std::list<unsigned>::iterator threads = (*activeThreads).begin();
811    bool status_change = false;
812
813    wroteToTimeBuffer = false;
814
815    while (threads != (*activeThreads).end()) {
816        unsigned tid = *threads++;
817
818        // Check the signals for each thread to determine the proper status
819        // for each thread.
820        bool updated_status = checkSignalsAndUpdate(tid);
821        status_change =  status_change || updated_status;
822    }
823
824    DPRINTF(Fetch, "Running stage.\n");
825
826    // Reset the number of the instruction we're fetching.
827    numInst = 0;
828
829#if FULL_SYSTEM
830    if (fromCommit->commitInfo[0].interruptPending) {
831        interruptPending = true;
832    }
833
834    if (fromCommit->commitInfo[0].clearInterrupt) {
835        interruptPending = false;
836    }
837#endif
838
839    for (threadFetched = 0; threadFetched < numFetchingThreads;
840         threadFetched++) {
841        // Fetch each of the actively fetching threads.
842        fetch(status_change);
843    }
844
845    // Record number of instructions fetched this cycle for distribution.
846    fetchNisnDist.sample(numInst);
847
848    if (status_change) {
849        // Change the fetch stage status if there was a status change.
850        _status = updateFetchStatus();
851    }
852
853    // If there was activity this cycle, inform the CPU of it.
854    if (wroteToTimeBuffer || cpu->contextSwitch) {
855        DPRINTF(Activity, "Activity this cycle.\n");
856
857        cpu->activityThisCycle();
858    }
859}
860
861template <class Impl>
862bool
863DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid)
864{
865    // Update the per thread stall statuses.
866    if (fromDecode->decodeBlock[tid]) {
867        stalls[tid].decode = true;
868    }
869
870    if (fromDecode->decodeUnblock[tid]) {
871        assert(stalls[tid].decode);
872        assert(!fromDecode->decodeBlock[tid]);
873        stalls[tid].decode = false;
874    }
875
876    if (fromRename->renameBlock[tid]) {
877        stalls[tid].rename = true;
878    }
879
880    if (fromRename->renameUnblock[tid]) {
881        assert(stalls[tid].rename);
882        assert(!fromRename->renameBlock[tid]);
883        stalls[tid].rename = false;
884    }
885
886    if (fromIEW->iewBlock[tid]) {
887        stalls[tid].iew = true;
888    }
889
890    if (fromIEW->iewUnblock[tid]) {
891        assert(stalls[tid].iew);
892        assert(!fromIEW->iewBlock[tid]);
893        stalls[tid].iew = false;
894    }
895
896    if (fromCommit->commitBlock[tid]) {
897        stalls[tid].commit = true;
898    }
899
900    if (fromCommit->commitUnblock[tid]) {
901        assert(stalls[tid].commit);
902        assert(!fromCommit->commitBlock[tid]);
903        stalls[tid].commit = false;
904    }
905
906    // Check squash signals from commit.
907    if (fromCommit->commitInfo[tid].squash) {
908
909        DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
910                "from commit.\n",tid);
911
912#if ISA_HAS_DELAY_SLOT
913    InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
914#else
915    InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].doneSeqNum;
916#endif
917        // In any case, squash.
918        squash(fromCommit->commitInfo[tid].nextPC,
919               doneSeqNum,
920               fromCommit->commitInfo[tid].squashDelaySlot,
921               tid);
922
923        // Also check if there's a mispredict that happened.
924        if (fromCommit->commitInfo[tid].branchMispredict) {
925            branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
926                              fromCommit->commitInfo[tid].nextPC,
927                              fromCommit->commitInfo[tid].branchTaken,
928                              tid);
929        } else {
930            branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
931                              tid);
932        }
933
934        return true;
935    } else if (fromCommit->commitInfo[tid].doneSeqNum) {
936        // Update the branch predictor if it wasn't a squashed instruction
937        // that was broadcasted.
938        branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid);
939    }
940
941    // Check ROB squash signals from commit.
942    if (fromCommit->commitInfo[tid].robSquashing) {
943        DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid);
944
945        // Continue to squash.
946        fetchStatus[tid] = Squashing;
947
948        return true;
949    }
950
951    // Check squash signals from decode.
952    if (fromDecode->decodeInfo[tid].squash) {
953        DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
954                "from decode.\n",tid);
955
956        // Update the branch predictor.
957        if (fromDecode->decodeInfo[tid].branchMispredict) {
958            branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
959                              fromDecode->decodeInfo[tid].nextPC,
960                              fromDecode->decodeInfo[tid].branchTaken,
961                              tid);
962        } else {
963            branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
964                              tid);
965        }
966
967        if (fetchStatus[tid] != Squashing) {
968
969#if ISA_HAS_DELAY_SLOT
970            InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].bdelayDoneSeqNum;
971#else
972            InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].doneSeqNum;
973#endif
974            // Squash unless we're already squashing
975            squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
976                             doneSeqNum,
977                             tid);
978
979            return true;
980        }
981    }
982
983    if (checkStall(tid) && fetchStatus[tid] != IcacheWaitResponse) {
984        DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid);
985
986        fetchStatus[tid] = Blocked;
987
988        return true;
989    }
990
991    if (fetchStatus[tid] == Blocked ||
992        fetchStatus[tid] == Squashing) {
993        // Switch status to running if fetch isn't being told to block or
994        // squash this cycle.
995        DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n",
996                tid);
997
998        fetchStatus[tid] = Running;
999
1000        return true;
1001    }
1002
1003    // If we've reached this point, we have not gotten any signals that
1004    // cause fetch to change its status.  Fetch remains the same as before.
1005    return false;
1006}
1007
1008template<class Impl>
1009void
1010DefaultFetch<Impl>::fetch(bool &status_change)
1011{
1012    //////////////////////////////////////////
1013    // Start actual fetch
1014    //////////////////////////////////////////
1015    int tid = getFetchingThread(fetchPolicy);
1016
1017    if (tid == -1 || drainPending) {
1018        DPRINTF(Fetch,"There are no more threads available to fetch from.\n");
1019
1020        // Breaks looping condition in tick()
1021        threadFetched = numFetchingThreads;
1022        return;
1023    }
1024
1025    DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
1026
1027    // The current PC.
1028    Addr &fetch_PC = PC[tid];
1029
1030    // Fault code for memory access.
1031    Fault fault = NoFault;
1032
1033    // If returning from the delay of a cache miss, then update the status
1034    // to running, otherwise do the cache access.  Possibly move this up
1035    // to tick() function.
1036    if (fetchStatus[tid] == IcacheAccessComplete) {
1037        DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n",
1038                tid);
1039
1040        fetchStatus[tid] = Running;
1041        status_change = true;
1042    } else if (fetchStatus[tid] == Running) {
1043        DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
1044                "instruction, starting at PC %08p.\n",
1045                tid, fetch_PC);
1046
1047        bool fetch_success = fetchCacheLine(fetch_PC, fault, tid);
1048        if (!fetch_success) {
1049            if (cacheBlocked) {
1050                ++icacheStallCycles;
1051            } else {
1052                ++fetchMiscStallCycles;
1053            }
1054            return;
1055        }
1056    } else {
1057        if (fetchStatus[tid] == Idle) {
1058            ++fetchIdleCycles;
1059        } else if (fetchStatus[tid] == Blocked) {
1060            ++fetchBlockedCycles;
1061        } else if (fetchStatus[tid] == Squashing) {
1062            ++fetchSquashCycles;
1063        } else if (fetchStatus[tid] == IcacheWaitResponse) {
1064            ++icacheStallCycles;
1065        }
1066
1067        // Status is Idle, Squashing, Blocked, or IcacheWaitResponse, so
1068        // fetch should do nothing.
1069        return;
1070    }
1071
1072    ++fetchCycles;
1073
1074    // If we had a stall due to an icache miss, then return.
1075    if (fetchStatus[tid] == IcacheWaitResponse) {
1076        ++icacheStallCycles;
1077        status_change = true;
1078        return;
1079    }
1080
1081    Addr next_PC = fetch_PC;
1082    Addr next_NPC = next_PC + instSize;
1083    InstSeqNum inst_seq;
1084    MachInst inst;
1085    ExtMachInst ext_inst;
1086    // @todo: Fix this hack.
1087    unsigned offset = (fetch_PC & cacheBlkMask) & ~3;
1088
1089    if (fault == NoFault) {
1090        // If the read of the first instruction was successful, then grab the
1091        // instructions from the rest of the cache line and put them into the
1092        // queue heading to decode.
1093
1094        DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
1095                "decode.\n",tid);
1096
1097        // Need to keep track of whether or not a predicted branch
1098        // ended this fetch block.
1099        bool predicted_branch = false;
1100
1101        // Need to keep track of whether or not a delay slot
1102        // instruction has been fetched
1103
1104        for (;
1105             offset < cacheBlkSize &&
1106                 numInst < fetchWidth &&
1107                 (!predicted_branch || delaySlotInfo[tid].numInsts > 0);
1108             ++numInst) {
1109
1110            // Get a sequence number.
1111            inst_seq = cpu->getAndIncrementInstSeq();
1112
1113            // Make sure this is a valid index.
1114            assert(offset <= cacheBlkSize - instSize);
1115
1116            // Get the instruction from the array of the cache line.
1117            inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
1118                        (&cacheData[tid][offset]));
1119
1120#if THE_ISA == ALPHA_ISA
1121            ext_inst = TheISA::makeExtMI(inst, fetch_PC);
1122#elif THE_ISA == SPARC_ISA
1123            ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC());
1124#endif
1125
1126            // Create a new DynInst from the instruction fetched.
1127            DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
1128                                                 next_PC,
1129                                                 inst_seq, cpu);
1130            instruction->setTid(tid);
1131
1132            instruction->setASID(tid);
1133
1134            instruction->setThreadState(cpu->thread[tid]);
1135
1136            DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created "
1137                    "[sn:%lli]\n",
1138                    tid, instruction->readPC(), inst_seq);
1139
1140            DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n",
1141                    tid, instruction->staticInst->disassemble(fetch_PC));
1142
1143            instruction->traceData =
1144                Trace::getInstRecord(curTick, cpu->tcBase(tid),
1145                                     instruction->staticInst,
1146                                     instruction->readPC());
1147
1148            predicted_branch = lookupAndUpdateNextPC(instruction, next_PC,
1149                                                     next_NPC);
1150
1151            // Add instruction to the CPU's list of instructions.
1152            instruction->setInstListIt(cpu->addInst(instruction));
1153
1154            // Write the instruction to the first slot in the queue
1155            // that heads to decode.
1156            toDecode->insts[numInst] = instruction;
1157
1158            toDecode->size++;
1159
1160            // Increment stat of fetched instructions.
1161            ++fetchedInsts;
1162
1163            // Move to the next instruction, unless we have a branch.
1164            fetch_PC = next_PC;
1165
1166            if (instruction->isQuiesce()) {
1167//                warn("%lli: Quiesce instruction encountered, halting fetch!",
1168//                     curTick);
1169                fetchStatus[tid] = QuiescePending;
1170                ++numInst;
1171                status_change = true;
1172                break;
1173            }
1174
1175            offset += instSize;
1176
1177#if ISA_HAS_DELAY_SLOT
1178            if (predicted_branch) {
1179                delaySlotInfo[tid].branchSeqNum = inst_seq;
1180
1181                DPRINTF(Fetch, "[tid:%i]: Delay slot branch set to [sn:%i]\n",
1182                        tid, inst_seq);
1183                continue;
1184            } else if (delaySlotInfo[tid].numInsts > 0) {
1185                --delaySlotInfo[tid].numInsts;
1186
1187                // It's OK to set PC to target of branch
1188                if (delaySlotInfo[tid].numInsts == 0) {
1189                    delaySlotInfo[tid].targetReady = true;
1190
1191                    // Break the looping condition
1192                    predicted_branch = true;
1193                }
1194
1195                DPRINTF(Fetch, "[tid:%i]: %i delay slot inst(s) left to"
1196                        " process.\n", tid, delaySlotInfo[tid].numInsts);
1197            }
1198#endif
1199        }
1200
1201        if (offset >= cacheBlkSize) {
1202            DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache "
1203                    "block.\n", tid);
1204        } else if (numInst >= fetchWidth) {
1205            DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth "
1206                    "for this cycle.\n", tid);
1207        } else if (predicted_branch && delaySlotInfo[tid].numInsts <= 0) {
1208            DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch "
1209                    "instruction encountered.\n", tid);
1210        }
1211    }
1212
1213    if (numInst > 0) {
1214        wroteToTimeBuffer = true;
1215    }
1216
1217    // Now that fetching is completed, update the PC to signify what the next
1218    // cycle will be.
1219    if (fault == NoFault) {
1220#if ISA_HAS_DELAY_SLOT
1221        if (delaySlotInfo[tid].targetReady &&
1222            delaySlotInfo[tid].numInsts == 0) {
1223            // Set PC to target
1224            PC[tid] = delaySlotInfo[tid].targetAddr; //next_PC
1225            nextPC[tid] = next_PC + instSize;        //next_NPC
1226            nextNPC[tid] = next_PC + (2 * instSize);
1227
1228            delaySlotInfo[tid].targetReady = false;
1229        } else {
1230            PC[tid] = next_PC;
1231            nextPC[tid] = next_NPC;
1232            nextNPC[tid] = next_NPC + instSize;
1233        }
1234
1235        DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, PC[tid]);
1236#else
1237        DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n",tid, next_PC);
1238        PC[tid] = next_PC;
1239        nextPC[tid] = next_PC + instSize;
1240#endif
1241    } else {
1242        // We shouldn't be in an icache miss and also have a fault (an ITB
1243        // miss)
1244        if (fetchStatus[tid] == IcacheWaitResponse) {
1245            panic("Fetch should have exited prior to this!");
1246        }
1247
1248        // Send the fault to commit.  This thread will not do anything
1249        // until commit handles the fault.  The only other way it can
1250        // wake up is if a squash comes along and changes the PC.
1251#if FULL_SYSTEM
1252        assert(numInst != fetchWidth);
1253        // Get a sequence number.
1254        inst_seq = cpu->getAndIncrementInstSeq();
1255        // We will use a nop in order to carry the fault.
1256        ext_inst = TheISA::NoopMachInst;
1257
1258        // Create a new DynInst from the dummy nop.
1259        DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
1260                                             next_PC,
1261                                             inst_seq, cpu);
1262        instruction->setPredTarg(next_PC + instSize);
1263        instruction->setTid(tid);
1264
1265        instruction->setASID(tid);
1266
1267        instruction->setThreadState(cpu->thread[tid]);
1268
1269        instruction->traceData = NULL;
1270
1271        instruction->setInstListIt(cpu->addInst(instruction));
1272
1273        instruction->fault = fault;
1274
1275        toDecode->insts[numInst] = instruction;
1276        toDecode->size++;
1277
1278        DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid);
1279
1280        fetchStatus[tid] = TrapPending;
1281        status_change = true;
1282
1283//        warn("%lli fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
1284#else // !FULL_SYSTEM
1285        warn("cycle %lli: fault (%s) detected @ PC %08p", curTick, fault->name(), PC[tid]);
1286#endif // FULL_SYSTEM
1287    }
1288}
1289
1290template<class Impl>
1291void
1292DefaultFetch<Impl>::recvRetry()
1293{
1294    if (retryPkt != NULL) {
1295        assert(cacheBlocked);
1296        assert(retryTid != -1);
1297        assert(fetchStatus[retryTid] == IcacheWaitRetry);
1298
1299        if (icachePort->sendTiming(retryPkt)) {
1300            fetchStatus[retryTid] = IcacheWaitResponse;
1301            retryPkt = NULL;
1302            retryTid = -1;
1303            cacheBlocked = false;
1304        }
1305    } else {
1306        assert(retryTid == -1);
1307        // Access has been squashed since it was sent out.  Just clear
1308        // the cache being blocked.
1309        cacheBlocked = false;
1310    }
1311}
1312
1313///////////////////////////////////////
1314//                                   //
1315//  SMT FETCH POLICY MAINTAINED HERE //
1316//                                   //
1317///////////////////////////////////////
1318template<class Impl>
1319int
1320DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority)
1321{
1322    if (numThreads > 1) {
1323        switch (fetch_priority) {
1324
1325          case SingleThread:
1326            return 0;
1327
1328          case RoundRobin:
1329            return roundRobin();
1330
1331          case IQ:
1332            return iqCount();
1333
1334          case LSQ:
1335            return lsqCount();
1336
1337          case Branch:
1338            return branchCount();
1339
1340          default:
1341            return -1;
1342        }
1343    } else {
1344        int tid = *((*activeThreads).begin());
1345
1346        if (fetchStatus[tid] == Running ||
1347            fetchStatus[tid] == IcacheAccessComplete ||
1348            fetchStatus[tid] == Idle) {
1349            return tid;
1350        } else {
1351            return -1;
1352        }
1353    }
1354
1355}
1356
1357
1358template<class Impl>
1359int
1360DefaultFetch<Impl>::roundRobin()
1361{
1362    std::list<unsigned>::iterator pri_iter = priorityList.begin();
1363    std::list<unsigned>::iterator end      = priorityList.end();
1364
1365    int high_pri;
1366
1367    while (pri_iter != end) {
1368        high_pri = *pri_iter;
1369
1370        assert(high_pri <= numThreads);
1371
1372        if (fetchStatus[high_pri] == Running ||
1373            fetchStatus[high_pri] == IcacheAccessComplete ||
1374            fetchStatus[high_pri] == Idle) {
1375
1376            priorityList.erase(pri_iter);
1377            priorityList.push_back(high_pri);
1378
1379            return high_pri;
1380        }
1381
1382        pri_iter++;
1383    }
1384
1385    return -1;
1386}
1387
1388template<class Impl>
1389int
1390DefaultFetch<Impl>::iqCount()
1391{
1392    std::priority_queue<unsigned> PQ;
1393
1394    std::list<unsigned>::iterator threads = (*activeThreads).begin();
1395
1396    while (threads != (*activeThreads).end()) {
1397        unsigned tid = *threads++;
1398
1399        PQ.push(fromIEW->iewInfo[tid].iqCount);
1400    }
1401
1402    while (!PQ.empty()) {
1403
1404        unsigned high_pri = PQ.top();
1405
1406        if (fetchStatus[high_pri] == Running ||
1407            fetchStatus[high_pri] == IcacheAccessComplete ||
1408            fetchStatus[high_pri] == Idle)
1409            return high_pri;
1410        else
1411            PQ.pop();
1412
1413    }
1414
1415    return -1;
1416}
1417
1418template<class Impl>
1419int
1420DefaultFetch<Impl>::lsqCount()
1421{
1422    std::priority_queue<unsigned> PQ;
1423
1424
1425    std::list<unsigned>::iterator threads = (*activeThreads).begin();
1426
1427    while (threads != (*activeThreads).end()) {
1428        unsigned tid = *threads++;
1429
1430        PQ.push(fromIEW->iewInfo[tid].ldstqCount);
1431    }
1432
1433    while (!PQ.empty()) {
1434
1435        unsigned high_pri = PQ.top();
1436
1437        if (fetchStatus[high_pri] == Running ||
1438            fetchStatus[high_pri] == IcacheAccessComplete ||
1439            fetchStatus[high_pri] == Idle)
1440            return high_pri;
1441        else
1442            PQ.pop();
1443
1444    }
1445
1446    return -1;
1447}
1448
1449template<class Impl>
1450int
1451DefaultFetch<Impl>::branchCount()
1452{
1453    std::list<unsigned>::iterator threads = (*activeThreads).begin();
1454    panic("Branch Count Fetch policy unimplemented\n");
1455    return *threads;
1456}
1457