fetch_impl.hh revision 2900:7cccbae04d02 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 *          Korey Sewell
30 */
31
32#include "config/use_checker.hh"
33
34#include "arch/isa_traits.hh"
35#include "arch/utility.hh"
36#include "cpu/checker/cpu.hh"
37#include "cpu/exetrace.hh"
38#include "cpu/o3/fetch.hh"
39#include "mem/packet.hh"
40#include "mem/request.hh"
41#include "sim/byteswap.hh"
42#include "sim/host.hh"
43#include "sim/root.hh"
44
45#if FULL_SYSTEM
46#include "arch/tlb.hh"
47#include "arch/vtophys.hh"
48#include "base/remote_gdb.hh"
49#include "sim/system.hh"
50#endif // FULL_SYSTEM
51
52#include <algorithm>
53
54using namespace std;
55using namespace TheISA;
56
57template<class Impl>
58Tick
59DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt)
60{
61    panic("DefaultFetch doesn't expect recvAtomic callback!");
62    return curTick;
63}
64
65template<class Impl>
66void
67DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
68{
69    panic("DefaultFetch doesn't expect recvFunctional callback!");
70}
71
72template<class Impl>
73void
74DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status)
75{
76    if (status == RangeChange)
77        return;
78
79    panic("DefaultFetch doesn't expect recvStatusChange callback!");
80}
81
82template<class Impl>
83bool
84DefaultFetch<Impl>::IcachePort::recvTiming(Packet *pkt)
85{
86    fetch->processCacheCompletion(pkt);
87    return true;
88}
89
90template<class Impl>
91void
92DefaultFetch<Impl>::IcachePort::recvRetry()
93{
94    fetch->recvRetry();
95}
96
97template<class Impl>
98DefaultFetch<Impl>::DefaultFetch(Params *params)
99    : mem(params->mem),
100      branchPred(params),
101      decodeToFetchDelay(params->decodeToFetchDelay),
102      renameToFetchDelay(params->renameToFetchDelay),
103      iewToFetchDelay(params->iewToFetchDelay),
104      commitToFetchDelay(params->commitToFetchDelay),
105      fetchWidth(params->fetchWidth),
106      cacheBlocked(false),
107      retryPkt(NULL),
108      retryTid(-1),
109      numThreads(params->numberOfThreads),
110      numFetchingThreads(params->smtNumFetchingThreads),
111      interruptPending(false),
112      drainPending(false),
113      switchedOut(false)
114{
115    if (numThreads > Impl::MaxThreads)
116        fatal("numThreads is not a valid value\n");
117
118    // Set fetch stage's status to inactive.
119    _status = Inactive;
120
121    string policy = params->smtFetchPolicy;
122
123    // Convert string to lowercase
124    std::transform(policy.begin(), policy.end(), policy.begin(),
125                   (int(*)(int)) tolower);
126
127    // Figure out fetch policy
128    if (policy == "singlethread") {
129        fetchPolicy = SingleThread;
130        if (numThreads > 1)
131            panic("Invalid Fetch Policy for a SMT workload.");
132    } else if (policy == "roundrobin") {
133        fetchPolicy = RoundRobin;
134        DPRINTF(Fetch, "Fetch policy set to Round Robin\n");
135    } else if (policy == "branch") {
136        fetchPolicy = Branch;
137        DPRINTF(Fetch, "Fetch policy set to Branch Count\n");
138    } else if (policy == "iqcount") {
139        fetchPolicy = IQ;
140        DPRINTF(Fetch, "Fetch policy set to IQ count\n");
141    } else if (policy == "lsqcount") {
142        fetchPolicy = LSQ;
143        DPRINTF(Fetch, "Fetch policy set to LSQ count\n");
144    } else {
145        fatal("Invalid Fetch Policy. Options Are: {SingleThread,"
146              " RoundRobin,LSQcount,IQcount}\n");
147    }
148
149    // Size of cache block.
150    cacheBlkSize = 64;
151
152    // Create mask to get rid of offset bits.
153    cacheBlkMask = (cacheBlkSize - 1);
154
155    for (int tid=0; tid < numThreads; tid++) {
156
157        fetchStatus[tid] = Running;
158
159        priorityList.push_back(tid);
160
161        memReq[tid] = NULL;
162
163        // Create space to store a cache line.
164        cacheData[tid] = new uint8_t[cacheBlkSize];
165
166        stalls[tid].decode = 0;
167        stalls[tid].rename = 0;
168        stalls[tid].iew = 0;
169        stalls[tid].commit = 0;
170    }
171
172    // Get the size of an instruction.
173    instSize = sizeof(MachInst);
174}
175
176template <class Impl>
177std::string
178DefaultFetch<Impl>::name() const
179{
180    return cpu->name() + ".fetch";
181}
182
183template <class Impl>
184void
185DefaultFetch<Impl>::regStats()
186{
187    icacheStallCycles
188        .name(name() + ".icacheStallCycles")
189        .desc("Number of cycles fetch is stalled on an Icache miss")
190        .prereq(icacheStallCycles);
191
192    fetchedInsts
193        .name(name() + ".Insts")
194        .desc("Number of instructions fetch has processed")
195        .prereq(fetchedInsts);
196
197    fetchedBranches
198        .name(name() + ".Branches")
199        .desc("Number of branches that fetch encountered")
200        .prereq(fetchedBranches);
201
202    predictedBranches
203        .name(name() + ".predictedBranches")
204        .desc("Number of branches that fetch has predicted taken")
205        .prereq(predictedBranches);
206
207    fetchCycles
208        .name(name() + ".Cycles")
209        .desc("Number of cycles fetch has run and was not squashing or"
210              " blocked")
211        .prereq(fetchCycles);
212
213    fetchSquashCycles
214        .name(name() + ".SquashCycles")
215        .desc("Number of cycles fetch has spent squashing")
216        .prereq(fetchSquashCycles);
217
218    fetchIdleCycles
219        .name(name() + ".IdleCycles")
220        .desc("Number of cycles fetch was idle")
221        .prereq(fetchIdleCycles);
222
223    fetchBlockedCycles
224        .name(name() + ".BlockedCycles")
225        .desc("Number of cycles fetch has spent blocked")
226        .prereq(fetchBlockedCycles);
227
228    fetchedCacheLines
229        .name(name() + ".CacheLines")
230        .desc("Number of cache lines fetched")
231        .prereq(fetchedCacheLines);
232
233    fetchMiscStallCycles
234        .name(name() + ".MiscStallCycles")
235        .desc("Number of cycles fetch has spent waiting on interrupts, or "
236              "bad addresses, or out of MSHRs")
237        .prereq(fetchMiscStallCycles);
238
239    fetchIcacheSquashes
240        .name(name() + ".IcacheSquashes")
241        .desc("Number of outstanding Icache misses that were squashed")
242        .prereq(fetchIcacheSquashes);
243
244    fetchNisnDist
245        .init(/* base value */ 0,
246              /* last value */ fetchWidth,
247              /* bucket size */ 1)
248        .name(name() + ".rateDist")
249        .desc("Number of instructions fetched each cycle (Total)")
250        .flags(Stats::pdf);
251
252    idleRate
253        .name(name() + ".idleRate")
254        .desc("Percent of cycles fetch was idle")
255        .prereq(idleRate);
256    idleRate = fetchIdleCycles * 100 / cpu->numCycles;
257
258    branchRate
259        .name(name() + ".branchRate")
260        .desc("Number of branch fetches per cycle")
261        .flags(Stats::total);
262    branchRate = fetchedBranches / cpu->numCycles;
263
264    fetchRate
265        .name(name() + ".rate")
266        .desc("Number of inst fetches per cycle")
267        .flags(Stats::total);
268    fetchRate = fetchedInsts / cpu->numCycles;
269
270    branchPred.regStats();
271}
272
273template<class Impl>
274void
275DefaultFetch<Impl>::setCPU(O3CPU *cpu_ptr)
276{
277    DPRINTF(Fetch, "Setting the CPU pointer.\n");
278    cpu = cpu_ptr;
279
280    // Name is finally available, so create the port.
281    icachePort = new IcachePort(this);
282
283#if USE_CHECKER
284    if (cpu->checker) {
285        cpu->checker->setIcachePort(icachePort);
286    }
287#endif
288
289    // Fetch needs to start fetching instructions at the very beginning,
290    // so it must start up in active state.
291    switchToActive();
292}
293
294template<class Impl>
295void
296DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
297{
298    DPRINTF(Fetch, "Setting the time buffer pointer.\n");
299    timeBuffer = time_buffer;
300
301    // Create wires to get information from proper places in time buffer.
302    fromDecode = timeBuffer->getWire(-decodeToFetchDelay);
303    fromRename = timeBuffer->getWire(-renameToFetchDelay);
304    fromIEW = timeBuffer->getWire(-iewToFetchDelay);
305    fromCommit = timeBuffer->getWire(-commitToFetchDelay);
306}
307
308template<class Impl>
309void
310DefaultFetch<Impl>::setActiveThreads(list<unsigned> *at_ptr)
311{
312    DPRINTF(Fetch, "Setting active threads list pointer.\n");
313    activeThreads = at_ptr;
314}
315
316template<class Impl>
317void
318DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
319{
320    DPRINTF(Fetch, "Setting the fetch queue pointer.\n");
321    fetchQueue = fq_ptr;
322
323    // Create wire to write information to proper place in fetch queue.
324    toDecode = fetchQueue->getWire(0);
325}
326
327template<class Impl>
328void
329DefaultFetch<Impl>::initStage()
330{
331    // Setup PC and nextPC with initial state.
332    for (int tid = 0; tid < numThreads; tid++) {
333        PC[tid] = cpu->readPC(tid);
334        nextPC[tid] = cpu->readNextPC(tid);
335#if THE_ISA != ALPHA_ISA
336        nextNPC[tid] = cpu->readNextNPC(tid);
337#endif
338    }
339}
340
341template<class Impl>
342void
343DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
344{
345    unsigned tid = pkt->req->getThreadNum();
346
347    DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid);
348
349    // Only change the status if it's still waiting on the icache access
350    // to return.
351    if (fetchStatus[tid] != IcacheWaitResponse ||
352        pkt->req != memReq[tid] ||
353        isSwitchedOut()) {
354        ++fetchIcacheSquashes;
355        delete pkt->req;
356        delete pkt;
357        return;
358    }
359
360    memcpy(cacheData[tid], pkt->getPtr<uint8_t *>(), cacheBlkSize);
361
362    if (!drainPending) {
363        // Wake up the CPU (if it went to sleep and was waiting on
364        // this completion event).
365        cpu->wakeCPU();
366
367        DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",
368                tid);
369
370        switchToActive();
371    }
372
373    // Only switch to IcacheAccessComplete if we're not stalled as well.
374    if (checkStall(tid)) {
375        fetchStatus[tid] = Blocked;
376    } else {
377        fetchStatus[tid] = IcacheAccessComplete;
378    }
379
380    // Reset the mem req to NULL.
381    delete pkt->req;
382    delete pkt;
383    memReq[tid] = NULL;
384}
385
386template <class Impl>
387bool
388DefaultFetch<Impl>::drain()
389{
390    // Fetch is ready to drain at any time.
391    cpu->signalDrained();
392    drainPending = true;
393    return true;
394}
395
396template <class Impl>
397void
398DefaultFetch<Impl>::resume()
399{
400    drainPending = false;
401}
402
403template <class Impl>
404void
405DefaultFetch<Impl>::switchOut()
406{
407    switchedOut = true;
408    // Branch predictor needs to have its state cleared.
409    branchPred.switchOut();
410}
411
412template <class Impl>
413void
414DefaultFetch<Impl>::takeOverFrom()
415{
416    // Reset all state
417    for (int i = 0; i < Impl::MaxThreads; ++i) {
418        stalls[i].decode = 0;
419        stalls[i].rename = 0;
420        stalls[i].iew = 0;
421        stalls[i].commit = 0;
422        PC[i] = cpu->readPC(i);
423        nextPC[i] = cpu->readNextPC(i);
424#if THE_ISA != ALPHA_ISA
425        nextNPC[i] = cpu->readNextNPC(i);
426#endif
427        fetchStatus[i] = Running;
428    }
429    numInst = 0;
430    wroteToTimeBuffer = false;
431    _status = Inactive;
432    switchedOut = false;
433    branchPred.takeOverFrom();
434}
435
436template <class Impl>
437void
438DefaultFetch<Impl>::wakeFromQuiesce()
439{
440    DPRINTF(Fetch, "Waking up from quiesce\n");
441    // Hopefully this is safe
442    // @todo: Allow other threads to wake from quiesce.
443    fetchStatus[0] = Running;
444}
445
446template <class Impl>
447inline void
448DefaultFetch<Impl>::switchToActive()
449{
450    if (_status == Inactive) {
451        DPRINTF(Activity, "Activating stage.\n");
452
453        cpu->activateStage(O3CPU::FetchIdx);
454
455        _status = Active;
456    }
457}
458
459template <class Impl>
460inline void
461DefaultFetch<Impl>::switchToInactive()
462{
463    if (_status == Active) {
464        DPRINTF(Activity, "Deactivating stage.\n");
465
466        cpu->deactivateStage(O3CPU::FetchIdx);
467
468        _status = Inactive;
469    }
470}
471
472template <class Impl>
473bool
474DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC)
475{
476    // Do branch prediction check here.
477    // A bit of a misnomer...next_PC is actually the current PC until
478    // this function updates it.
479    bool predict_taken;
480
481    if (!inst->isControl()) {
482        next_PC = next_PC + instSize;
483        inst->setPredTarg(next_PC);
484        return false;
485    }
486
487    predict_taken = branchPred.predict(inst, next_PC, inst->threadNumber);
488
489    ++fetchedBranches;
490
491    if (predict_taken) {
492        ++predictedBranches;
493    }
494
495    return predict_taken;
496}
497
498template <class Impl>
499bool
500DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid)
501{
502    Fault fault = NoFault;
503
504#if FULL_SYSTEM
505    // Flag to say whether or not address is physical addr.
506    unsigned flags = cpu->inPalMode(fetch_PC) ? PHYSICAL : 0;
507#else
508    unsigned flags = 0;
509#endif // FULL_SYSTEM
510
511    if (cacheBlocked || (interruptPending && flags == 0)) {
512        // Hold off fetch from getting new instructions when:
513        // Cache is blocked, or
514        // while an interrupt is pending and we're not in PAL mode, or
515        // fetch is switched out.
516        return false;
517    }
518
519    // Align the fetch PC so it's at the start of a cache block.
520    fetch_PC = icacheBlockAlignPC(fetch_PC);
521
522    // If we've already got the block, no need to try to fetch it again.
523    if (fetch_PC == cacheDataPC[tid]) {
524        return true;
525    }
526
527    // Setup the memReq to do a read of the first instruction's address.
528    // Set the appropriate read size and flags as well.
529    // Build request here.
530    RequestPtr mem_req = new Request(tid, fetch_PC, cacheBlkSize, flags,
531                                     fetch_PC, cpu->readCpuId(), tid);
532
533    memReq[tid] = mem_req;
534
535    // Translate the instruction request.
536    fault = cpu->translateInstReq(mem_req, cpu->thread[tid]);
537
538    // In the case of faults, the fetch stage may need to stall and wait
539    // for the ITB miss to be handled.
540
541    // If translation was successful, attempt to read the first
542    // instruction.
543    if (fault == NoFault) {
544#if 0
545        if (cpu->system->memctrl->badaddr(memReq[tid]->paddr) ||
546            memReq[tid]->flags & UNCACHEABLE) {
547            DPRINTF(Fetch, "Fetch: Bad address %#x (hopefully on a "
548                    "misspeculating path)!",
549                    memReq[tid]->paddr);
550            ret_fault = TheISA::genMachineCheckFault();
551            return false;
552        }
553#endif
554
555        // Build packet here.
556        PacketPtr data_pkt = new Packet(mem_req,
557                                        Packet::ReadReq, Packet::Broadcast);
558        data_pkt->dataDynamic(new uint8_t[cacheBlkSize]);
559
560        cacheDataPC[tid] = fetch_PC;
561
562        DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
563
564        fetchedCacheLines++;
565
566        // Now do the timing access to see whether or not the instruction
567        // exists within the cache.
568        if (!icachePort->sendTiming(data_pkt)) {
569            assert(retryPkt == NULL);
570            assert(retryTid == -1);
571            DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
572            fetchStatus[tid] = IcacheWaitRetry;
573            retryPkt = data_pkt;
574            retryTid = tid;
575            cacheBlocked = true;
576            return false;
577        }
578
579        DPRINTF(Fetch, "[tid:%i]: Doing cache access.\n", tid);
580
581        lastIcacheStall[tid] = curTick;
582
583        DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
584                "response.\n", tid);
585
586        fetchStatus[tid] = IcacheWaitResponse;
587    } else {
588        delete mem_req;
589        memReq[tid] = NULL;
590    }
591
592    ret_fault = fault;
593    return true;
594}
595
596template <class Impl>
597inline void
598DefaultFetch<Impl>::doSquash(const Addr &new_PC, unsigned tid)
599{
600    DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x.\n",
601            tid, new_PC);
602
603    PC[tid] = new_PC;
604    nextPC[tid] = new_PC + instSize;
605
606    // Clear the icache miss if it's outstanding.
607    if (fetchStatus[tid] == IcacheWaitResponse) {
608        DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
609                tid);
610        memReq[tid] = NULL;
611    }
612
613    // Get rid of the retrying packet if it was from this thread.
614    if (retryTid == tid) {
615        assert(cacheBlocked);
616        cacheBlocked = false;
617        retryTid = -1;
618        retryPkt = NULL;
619        delete retryPkt->req;
620        delete retryPkt;
621    }
622
623    fetchStatus[tid] = Squashing;
624
625    ++fetchSquashCycles;
626}
627
628template<class Impl>
629void
630DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC,
631                                     const InstSeqNum &seq_num,
632                                     unsigned tid)
633{
634    DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid);
635
636    doSquash(new_PC, tid);
637
638    // Tell the CPU to remove any instructions that are in flight between
639    // fetch and decode.
640    cpu->removeInstsUntil(seq_num, tid);
641}
642
643template<class Impl>
644bool
645DefaultFetch<Impl>::checkStall(unsigned tid) const
646{
647    bool ret_val = false;
648
649    if (cpu->contextSwitch) {
650        DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid);
651        ret_val = true;
652    } else if (stalls[tid].decode) {
653        DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid);
654        ret_val = true;
655    } else if (stalls[tid].rename) {
656        DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid);
657        ret_val = true;
658    } else if (stalls[tid].iew) {
659        DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid);
660        ret_val = true;
661    } else if (stalls[tid].commit) {
662        DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid);
663        ret_val = true;
664    }
665
666    return ret_val;
667}
668
669template<class Impl>
670typename DefaultFetch<Impl>::FetchStatus
671DefaultFetch<Impl>::updateFetchStatus()
672{
673    //Check Running
674    list<unsigned>::iterator threads = (*activeThreads).begin();
675
676    while (threads != (*activeThreads).end()) {
677
678        unsigned tid = *threads++;
679
680        if (fetchStatus[tid] == Running ||
681            fetchStatus[tid] == Squashing ||
682            fetchStatus[tid] == IcacheAccessComplete) {
683
684            if (_status == Inactive) {
685                DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid);
686
687                if (fetchStatus[tid] == IcacheAccessComplete) {
688                    DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache"
689                            "completion\n",tid);
690                }
691
692                cpu->activateStage(O3CPU::FetchIdx);
693            }
694
695            return Active;
696        }
697    }
698
699    // Stage is switching from active to inactive, notify CPU of it.
700    if (_status == Active) {
701        DPRINTF(Activity, "Deactivating stage.\n");
702
703        cpu->deactivateStage(O3CPU::FetchIdx);
704    }
705
706    return Inactive;
707}
708
709template <class Impl>
710void
711DefaultFetch<Impl>::squash(const Addr &new_PC, unsigned tid)
712{
713    DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid);
714
715    doSquash(new_PC, tid);
716
717    // Tell the CPU to remove any instructions that are not in the ROB.
718    cpu->removeInstsNotInROB(tid);
719}
720
721template <class Impl>
722void
723DefaultFetch<Impl>::tick()
724{
725    list<unsigned>::iterator threads = (*activeThreads).begin();
726    bool status_change = false;
727
728    wroteToTimeBuffer = false;
729
730    while (threads != (*activeThreads).end()) {
731        unsigned tid = *threads++;
732
733        // Check the signals for each thread to determine the proper status
734        // for each thread.
735        bool updated_status = checkSignalsAndUpdate(tid);
736        status_change =  status_change || updated_status;
737    }
738
739    DPRINTF(Fetch, "Running stage.\n");
740
741    // Reset the number of the instruction we're fetching.
742    numInst = 0;
743
744#if FULL_SYSTEM
745    if (fromCommit->commitInfo[0].interruptPending) {
746        interruptPending = true;
747    }
748
749    if (fromCommit->commitInfo[0].clearInterrupt) {
750        interruptPending = false;
751    }
752#endif
753
754    for (threadFetched = 0; threadFetched < numFetchingThreads;
755         threadFetched++) {
756        // Fetch each of the actively fetching threads.
757        fetch(status_change);
758    }
759
760    // Record number of instructions fetched this cycle for distribution.
761    fetchNisnDist.sample(numInst);
762
763    if (status_change) {
764        // Change the fetch stage status if there was a status change.
765        _status = updateFetchStatus();
766    }
767
768    // If there was activity this cycle, inform the CPU of it.
769    if (wroteToTimeBuffer || cpu->contextSwitch) {
770        DPRINTF(Activity, "Activity this cycle.\n");
771
772        cpu->activityThisCycle();
773    }
774}
775
776template <class Impl>
777bool
778DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid)
779{
780    // Update the per thread stall statuses.
781    if (fromDecode->decodeBlock[tid]) {
782        stalls[tid].decode = true;
783    }
784
785    if (fromDecode->decodeUnblock[tid]) {
786        assert(stalls[tid].decode);
787        assert(!fromDecode->decodeBlock[tid]);
788        stalls[tid].decode = false;
789    }
790
791    if (fromRename->renameBlock[tid]) {
792        stalls[tid].rename = true;
793    }
794
795    if (fromRename->renameUnblock[tid]) {
796        assert(stalls[tid].rename);
797        assert(!fromRename->renameBlock[tid]);
798        stalls[tid].rename = false;
799    }
800
801    if (fromIEW->iewBlock[tid]) {
802        stalls[tid].iew = true;
803    }
804
805    if (fromIEW->iewUnblock[tid]) {
806        assert(stalls[tid].iew);
807        assert(!fromIEW->iewBlock[tid]);
808        stalls[tid].iew = false;
809    }
810
811    if (fromCommit->commitBlock[tid]) {
812        stalls[tid].commit = true;
813    }
814
815    if (fromCommit->commitUnblock[tid]) {
816        assert(stalls[tid].commit);
817        assert(!fromCommit->commitBlock[tid]);
818        stalls[tid].commit = false;
819    }
820
821    // Check squash signals from commit.
822    if (fromCommit->commitInfo[tid].squash) {
823
824        DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
825                "from commit.\n",tid);
826
827        // In any case, squash.
828        squash(fromCommit->commitInfo[tid].nextPC,tid);
829
830        // Also check if there's a mispredict that happened.
831        if (fromCommit->commitInfo[tid].branchMispredict) {
832            branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
833                              fromCommit->commitInfo[tid].nextPC,
834                              fromCommit->commitInfo[tid].branchTaken,
835                              tid);
836        } else {
837            branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
838                              tid);
839        }
840
841        return true;
842    } else if (fromCommit->commitInfo[tid].doneSeqNum) {
843        // Update the branch predictor if it wasn't a squashed instruction
844        // that was broadcasted.
845        branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid);
846    }
847
848    // Check ROB squash signals from commit.
849    if (fromCommit->commitInfo[tid].robSquashing) {
850        DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid);
851
852        // Continue to squash.
853        fetchStatus[tid] = Squashing;
854
855        return true;
856    }
857
858    // Check squash signals from decode.
859    if (fromDecode->decodeInfo[tid].squash) {
860        DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
861                "from decode.\n",tid);
862
863        // Update the branch predictor.
864        if (fromDecode->decodeInfo[tid].branchMispredict) {
865            branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
866                              fromDecode->decodeInfo[tid].nextPC,
867                              fromDecode->decodeInfo[tid].branchTaken,
868                              tid);
869        } else {
870            branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
871                              tid);
872        }
873
874        if (fetchStatus[tid] != Squashing) {
875            // Squash unless we're already squashing
876            squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
877                             fromDecode->decodeInfo[tid].doneSeqNum,
878                             tid);
879
880            return true;
881        }
882    }
883
884    if (checkStall(tid) && fetchStatus[tid] != IcacheWaitResponse) {
885        DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid);
886
887        fetchStatus[tid] = Blocked;
888
889        return true;
890    }
891
892    if (fetchStatus[tid] == Blocked ||
893        fetchStatus[tid] == Squashing) {
894        // Switch status to running if fetch isn't being told to block or
895        // squash this cycle.
896        DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n",
897                tid);
898
899        fetchStatus[tid] = Running;
900
901        return true;
902    }
903
904    // If we've reached this point, we have not gotten any signals that
905    // cause fetch to change its status.  Fetch remains the same as before.
906    return false;
907}
908
909template<class Impl>
910void
911DefaultFetch<Impl>::fetch(bool &status_change)
912{
913    //////////////////////////////////////////
914    // Start actual fetch
915    //////////////////////////////////////////
916    int tid = getFetchingThread(fetchPolicy);
917
918    if (tid == -1 || drainPending) {
919        DPRINTF(Fetch,"There are no more threads available to fetch from.\n");
920
921        // Breaks looping condition in tick()
922        threadFetched = numFetchingThreads;
923        return;
924    }
925
926    DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
927
928    // The current PC.
929    Addr &fetch_PC = PC[tid];
930
931    // Fault code for memory access.
932    Fault fault = NoFault;
933
934    // If returning from the delay of a cache miss, then update the status
935    // to running, otherwise do the cache access.  Possibly move this up
936    // to tick() function.
937    if (fetchStatus[tid] == IcacheAccessComplete) {
938        DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n",
939                tid);
940
941        fetchStatus[tid] = Running;
942        status_change = true;
943    } else if (fetchStatus[tid] == Running) {
944        DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
945                "instruction, starting at PC %08p.\n",
946                tid, fetch_PC);
947
948        bool fetch_success = fetchCacheLine(fetch_PC, fault, tid);
949        if (!fetch_success) {
950            if (cacheBlocked) {
951                ++icacheStallCycles;
952            } else {
953                ++fetchMiscStallCycles;
954            }
955            return;
956        }
957    } else {
958        if (fetchStatus[tid] == Idle) {
959            ++fetchIdleCycles;
960        } else if (fetchStatus[tid] == Blocked) {
961            ++fetchBlockedCycles;
962        } else if (fetchStatus[tid] == Squashing) {
963            ++fetchSquashCycles;
964        } else if (fetchStatus[tid] == IcacheWaitResponse) {
965            ++icacheStallCycles;
966        }
967
968        // Status is Idle, Squashing, Blocked, or IcacheWaitResponse, so
969        // fetch should do nothing.
970        return;
971    }
972
973    ++fetchCycles;
974
975    // If we had a stall due to an icache miss, then return.
976    if (fetchStatus[tid] == IcacheWaitResponse) {
977        ++icacheStallCycles;
978        status_change = true;
979        return;
980    }
981
982    Addr next_PC = fetch_PC;
983    InstSeqNum inst_seq;
984    MachInst inst;
985    ExtMachInst ext_inst;
986    // @todo: Fix this hack.
987    unsigned offset = (fetch_PC & cacheBlkMask) & ~3;
988
989    if (fault == NoFault) {
990        // If the read of the first instruction was successful, then grab the
991        // instructions from the rest of the cache line and put them into the
992        // queue heading to decode.
993
994        DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
995                "decode.\n",tid);
996
997        // Need to keep track of whether or not a predicted branch
998        // ended this fetch block.
999        bool predicted_branch = false;
1000
1001        for (;
1002             offset < cacheBlkSize &&
1003                 numInst < fetchWidth &&
1004                 !predicted_branch;
1005             ++numInst) {
1006
1007            // Get a sequence number.
1008            inst_seq = cpu->getAndIncrementInstSeq();
1009
1010            // Make sure this is a valid index.
1011            assert(offset <= cacheBlkSize - instSize);
1012
1013            // Get the instruction from the array of the cache line.
1014            inst = gtoh(*reinterpret_cast<MachInst *>
1015                        (&cacheData[tid][offset]));
1016
1017            ext_inst = TheISA::makeExtMI(inst, fetch_PC);
1018
1019            // Create a new DynInst from the instruction fetched.
1020            DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
1021                                                 next_PC,
1022                                                 inst_seq, cpu);
1023            instruction->setTid(tid);
1024
1025            instruction->setASID(tid);
1026
1027            instruction->setThreadState(cpu->thread[tid]);
1028
1029            DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created "
1030                    "[sn:%lli]\n",
1031                    tid, instruction->readPC(), inst_seq);
1032
1033            DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n",
1034                    tid, instruction->staticInst->disassemble(fetch_PC));
1035
1036            instruction->traceData =
1037                Trace::getInstRecord(curTick, cpu->tcBase(tid), cpu,
1038                                     instruction->staticInst,
1039                                     instruction->readPC(),tid);
1040
1041            predicted_branch = lookupAndUpdateNextPC(instruction, next_PC);
1042
1043            // Add instruction to the CPU's list of instructions.
1044            instruction->setInstListIt(cpu->addInst(instruction));
1045
1046            // Write the instruction to the first slot in the queue
1047            // that heads to decode.
1048            toDecode->insts[numInst] = instruction;
1049
1050            toDecode->size++;
1051
1052            // Increment stat of fetched instructions.
1053            ++fetchedInsts;
1054
1055            // Move to the next instruction, unless we have a branch.
1056            fetch_PC = next_PC;
1057
1058            if (instruction->isQuiesce()) {
1059                warn("cycle %lli: Quiesce instruction encountered, halting fetch!",
1060                     curTick);
1061                fetchStatus[tid] = QuiescePending;
1062                ++numInst;
1063                status_change = true;
1064                break;
1065            }
1066
1067            offset+= instSize;
1068        }
1069    }
1070
1071    if (numInst > 0) {
1072        wroteToTimeBuffer = true;
1073    }
1074
1075    // Now that fetching is completed, update the PC to signify what the next
1076    // cycle will be.
1077    if (fault == NoFault) {
1078        DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n",tid, next_PC);
1079
1080#if THE_ISA == ALPHA_ISA
1081        PC[tid] = next_PC;
1082        nextPC[tid] = next_PC + instSize;
1083#else
1084        PC[tid] = next_PC;
1085        nextPC[tid] = next_PC + instSize;
1086        nextPC[tid] = next_PC + instSize;
1087
1088        thread->setNextPC(thread->readNextNPC());
1089        thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
1090#endif
1091    } else {
1092        // We shouldn't be in an icache miss and also have a fault (an ITB
1093        // miss)
1094        if (fetchStatus[tid] == IcacheWaitResponse) {
1095            panic("Fetch should have exited prior to this!");
1096        }
1097
1098        // Send the fault to commit.  This thread will not do anything
1099        // until commit handles the fault.  The only other way it can
1100        // wake up is if a squash comes along and changes the PC.
1101#if FULL_SYSTEM
1102        assert(numInst != fetchWidth);
1103        // Get a sequence number.
1104        inst_seq = cpu->getAndIncrementInstSeq();
1105        // We will use a nop in order to carry the fault.
1106        ext_inst = TheISA::NoopMachInst;
1107
1108        // Create a new DynInst from the dummy nop.
1109        DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
1110                                             next_PC,
1111                                             inst_seq, cpu);
1112        instruction->setPredTarg(next_PC + instSize);
1113        instruction->setTid(tid);
1114
1115        instruction->setASID(tid);
1116
1117        instruction->setThreadState(cpu->thread[tid]);
1118
1119        instruction->traceData = NULL;
1120
1121        instruction->setInstListIt(cpu->addInst(instruction));
1122
1123        instruction->fault = fault;
1124
1125        toDecode->insts[numInst] = instruction;
1126        toDecode->size++;
1127
1128        DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid);
1129
1130        fetchStatus[tid] = TrapPending;
1131        status_change = true;
1132
1133        warn("cycle %lli: fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
1134#else // !FULL_SYSTEM
1135        warn("cycle %lli: fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
1136#endif // FULL_SYSTEM
1137    }
1138}
1139
1140template<class Impl>
1141void
1142DefaultFetch<Impl>::recvRetry()
1143{
1144    assert(cacheBlocked);
1145    if (retryPkt != NULL) {
1146        assert(retryTid != -1);
1147        assert(fetchStatus[retryTid] == IcacheWaitRetry);
1148
1149        if (icachePort->sendTiming(retryPkt)) {
1150            fetchStatus[retryTid] = IcacheWaitResponse;
1151            retryPkt = NULL;
1152            retryTid = -1;
1153            cacheBlocked = false;
1154        }
1155    } else {
1156        assert(retryTid == -1);
1157        // Access has been squashed since it was sent out.  Just clear
1158        // the cache being blocked.
1159        cacheBlocked = false;
1160    }
1161}
1162
1163///////////////////////////////////////
1164//                                   //
1165//  SMT FETCH POLICY MAINTAINED HERE //
1166//                                   //
1167///////////////////////////////////////
1168template<class Impl>
1169int
1170DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority)
1171{
1172    if (numThreads > 1) {
1173        switch (fetch_priority) {
1174
1175          case SingleThread:
1176            return 0;
1177
1178          case RoundRobin:
1179            return roundRobin();
1180
1181          case IQ:
1182            return iqCount();
1183
1184          case LSQ:
1185            return lsqCount();
1186
1187          case Branch:
1188            return branchCount();
1189
1190          default:
1191            return -1;
1192        }
1193    } else {
1194        int tid = *((*activeThreads).begin());
1195
1196        if (fetchStatus[tid] == Running ||
1197            fetchStatus[tid] == IcacheAccessComplete ||
1198            fetchStatus[tid] == Idle) {
1199            return tid;
1200        } else {
1201            return -1;
1202        }
1203    }
1204
1205}
1206
1207
1208template<class Impl>
1209int
1210DefaultFetch<Impl>::roundRobin()
1211{
1212    list<unsigned>::iterator pri_iter = priorityList.begin();
1213    list<unsigned>::iterator end      = priorityList.end();
1214
1215    int high_pri;
1216
1217    while (pri_iter != end) {
1218        high_pri = *pri_iter;
1219
1220        assert(high_pri <= numThreads);
1221
1222        if (fetchStatus[high_pri] == Running ||
1223            fetchStatus[high_pri] == IcacheAccessComplete ||
1224            fetchStatus[high_pri] == Idle) {
1225
1226            priorityList.erase(pri_iter);
1227            priorityList.push_back(high_pri);
1228
1229            return high_pri;
1230        }
1231
1232        pri_iter++;
1233    }
1234
1235    return -1;
1236}
1237
1238template<class Impl>
1239int
1240DefaultFetch<Impl>::iqCount()
1241{
1242    priority_queue<unsigned> PQ;
1243
1244    list<unsigned>::iterator threads = (*activeThreads).begin();
1245
1246    while (threads != (*activeThreads).end()) {
1247        unsigned tid = *threads++;
1248
1249        PQ.push(fromIEW->iewInfo[tid].iqCount);
1250    }
1251
1252    while (!PQ.empty()) {
1253
1254        unsigned high_pri = PQ.top();
1255
1256        if (fetchStatus[high_pri] == Running ||
1257            fetchStatus[high_pri] == IcacheAccessComplete ||
1258            fetchStatus[high_pri] == Idle)
1259            return high_pri;
1260        else
1261            PQ.pop();
1262
1263    }
1264
1265    return -1;
1266}
1267
1268template<class Impl>
1269int
1270DefaultFetch<Impl>::lsqCount()
1271{
1272    priority_queue<unsigned> PQ;
1273
1274
1275    list<unsigned>::iterator threads = (*activeThreads).begin();
1276
1277    while (threads != (*activeThreads).end()) {
1278        unsigned tid = *threads++;
1279
1280        PQ.push(fromIEW->iewInfo[tid].ldstqCount);
1281    }
1282
1283    while (!PQ.empty()) {
1284
1285        unsigned high_pri = PQ.top();
1286
1287        if (fetchStatus[high_pri] == Running ||
1288            fetchStatus[high_pri] == IcacheAccessComplete ||
1289            fetchStatus[high_pri] == Idle)
1290            return high_pri;
1291        else
1292            PQ.pop();
1293
1294    }
1295
1296    return -1;
1297}
1298
1299template<class Impl>
1300int
1301DefaultFetch<Impl>::branchCount()
1302{
1303    list<unsigned>::iterator threads = (*activeThreads).begin();
1304    panic("Branch Count Fetch policy unimplemented\n");
1305    return *threads;
1306}
1307