fetch_impl.hh revision 2831:0a42b294727c 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 *          Korey Sewell
30 */
31
32#include "config/use_checker.hh"
33
34#include "arch/isa_traits.hh"
35#include "arch/utility.hh"
36#include "cpu/checker/cpu.hh"
37#include "cpu/exetrace.hh"
38#include "cpu/o3/fetch.hh"
39#include "mem/packet.hh"
40#include "mem/request.hh"
41#include "sim/byteswap.hh"
42#include "sim/host.hh"
43#include "sim/root.hh"
44
45#if FULL_SYSTEM
46#include "arch/tlb.hh"
47#include "arch/vtophys.hh"
48#include "base/remote_gdb.hh"
49#include "sim/system.hh"
50#endif // FULL_SYSTEM
51
52#include <algorithm>
53
54using namespace std;
55using namespace TheISA;
56
57template<class Impl>
58Tick
59DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt)
60{
61    panic("DefaultFetch doesn't expect recvAtomic callback!");
62    return curTick;
63}
64
65template<class Impl>
66void
67DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
68{
69    panic("DefaultFetch doesn't expect recvFunctional callback!");
70}
71
72template<class Impl>
73void
74DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status)
75{
76    if (status == RangeChange)
77        return;
78
79    panic("DefaultFetch doesn't expect recvStatusChange callback!");
80}
81
82template<class Impl>
83bool
84DefaultFetch<Impl>::IcachePort::recvTiming(Packet *pkt)
85{
86    fetch->processCacheCompletion(pkt);
87    return true;
88}
89
90template<class Impl>
91void
92DefaultFetch<Impl>::IcachePort::recvRetry()
93{
94    fetch->recvRetry();
95}
96
97template<class Impl>
98DefaultFetch<Impl>::DefaultFetch(Params *params)
99    : mem(params->mem),
100      branchPred(params),
101      decodeToFetchDelay(params->decodeToFetchDelay),
102      renameToFetchDelay(params->renameToFetchDelay),
103      iewToFetchDelay(params->iewToFetchDelay),
104      commitToFetchDelay(params->commitToFetchDelay),
105      fetchWidth(params->fetchWidth),
106      cacheBlocked(false),
107      retryPkt(NULL),
108      retryTid(-1),
109      numThreads(params->numberOfThreads),
110      numFetchingThreads(params->smtNumFetchingThreads),
111      interruptPending(false),
112      switchedOut(false)
113{
114    if (numThreads > Impl::MaxThreads)
115        fatal("numThreads is not a valid value\n");
116
117    // Set fetch stage's status to inactive.
118    _status = Inactive;
119
120    string policy = params->smtFetchPolicy;
121
122    // Convert string to lowercase
123    std::transform(policy.begin(), policy.end(), policy.begin(),
124                   (int(*)(int)) tolower);
125
126    // Figure out fetch policy
127    if (policy == "singlethread") {
128        fetchPolicy = SingleThread;
129        if (numThreads > 1)
130            panic("Invalid Fetch Policy for a SMT workload.");
131    } else if (policy == "roundrobin") {
132        fetchPolicy = RoundRobin;
133        DPRINTF(Fetch, "Fetch policy set to Round Robin\n");
134    } else if (policy == "branch") {
135        fetchPolicy = Branch;
136        DPRINTF(Fetch, "Fetch policy set to Branch Count\n");
137    } else if (policy == "iqcount") {
138        fetchPolicy = IQ;
139        DPRINTF(Fetch, "Fetch policy set to IQ count\n");
140    } else if (policy == "lsqcount") {
141        fetchPolicy = LSQ;
142        DPRINTF(Fetch, "Fetch policy set to LSQ count\n");
143    } else {
144        fatal("Invalid Fetch Policy. Options Are: {SingleThread,"
145              " RoundRobin,LSQcount,IQcount}\n");
146    }
147
148    // Size of cache block.
149    cacheBlkSize = 64;
150
151    // Create mask to get rid of offset bits.
152    cacheBlkMask = (cacheBlkSize - 1);
153
154    for (int tid=0; tid < numThreads; tid++) {
155
156        fetchStatus[tid] = Running;
157
158        priorityList.push_back(tid);
159
160        memReq[tid] = NULL;
161
162        // Create space to store a cache line.
163        cacheData[tid] = new uint8_t[cacheBlkSize];
164
165        stalls[tid].decode = 0;
166        stalls[tid].rename = 0;
167        stalls[tid].iew = 0;
168        stalls[tid].commit = 0;
169    }
170
171    // Get the size of an instruction.
172    instSize = sizeof(MachInst);
173}
174
175template <class Impl>
176std::string
177DefaultFetch<Impl>::name() const
178{
179    return cpu->name() + ".fetch";
180}
181
182template <class Impl>
183void
184DefaultFetch<Impl>::regStats()
185{
186    icacheStallCycles
187        .name(name() + ".icacheStallCycles")
188        .desc("Number of cycles fetch is stalled on an Icache miss")
189        .prereq(icacheStallCycles);
190
191    fetchedInsts
192        .name(name() + ".Insts")
193        .desc("Number of instructions fetch has processed")
194        .prereq(fetchedInsts);
195
196    fetchedBranches
197        .name(name() + ".Branches")
198        .desc("Number of branches that fetch encountered")
199        .prereq(fetchedBranches);
200
201    predictedBranches
202        .name(name() + ".predictedBranches")
203        .desc("Number of branches that fetch has predicted taken")
204        .prereq(predictedBranches);
205
206    fetchCycles
207        .name(name() + ".Cycles")
208        .desc("Number of cycles fetch has run and was not squashing or"
209              " blocked")
210        .prereq(fetchCycles);
211
212    fetchSquashCycles
213        .name(name() + ".SquashCycles")
214        .desc("Number of cycles fetch has spent squashing")
215        .prereq(fetchSquashCycles);
216
217    fetchIdleCycles
218        .name(name() + ".IdleCycles")
219        .desc("Number of cycles fetch was idle")
220        .prereq(fetchIdleCycles);
221
222    fetchBlockedCycles
223        .name(name() + ".BlockedCycles")
224        .desc("Number of cycles fetch has spent blocked")
225        .prereq(fetchBlockedCycles);
226
227    fetchedCacheLines
228        .name(name() + ".CacheLines")
229        .desc("Number of cache lines fetched")
230        .prereq(fetchedCacheLines);
231
232    fetchMiscStallCycles
233        .name(name() + ".MiscStallCycles")
234        .desc("Number of cycles fetch has spent waiting on interrupts, or "
235              "bad addresses, or out of MSHRs")
236        .prereq(fetchMiscStallCycles);
237
238    fetchIcacheSquashes
239        .name(name() + ".IcacheSquashes")
240        .desc("Number of outstanding Icache misses that were squashed")
241        .prereq(fetchIcacheSquashes);
242
243    fetchNisnDist
244        .init(/* base value */ 0,
245              /* last value */ fetchWidth,
246              /* bucket size */ 1)
247        .name(name() + ".rateDist")
248        .desc("Number of instructions fetched each cycle (Total)")
249        .flags(Stats::pdf);
250
251    idleRate
252        .name(name() + ".idleRate")
253        .desc("Percent of cycles fetch was idle")
254        .prereq(idleRate);
255    idleRate = fetchIdleCycles * 100 / cpu->numCycles;
256
257    branchRate
258        .name(name() + ".branchRate")
259        .desc("Number of branch fetches per cycle")
260        .flags(Stats::total);
261    branchRate = fetchedBranches / cpu->numCycles;
262
263    fetchRate
264        .name(name() + ".rate")
265        .desc("Number of inst fetches per cycle")
266        .flags(Stats::total);
267    fetchRate = fetchedInsts / cpu->numCycles;
268
269    branchPred.regStats();
270}
271
272template<class Impl>
273void
274DefaultFetch<Impl>::setCPU(O3CPU *cpu_ptr)
275{
276    DPRINTF(Fetch, "Setting the CPU pointer.\n");
277    cpu = cpu_ptr;
278
279    // Name is finally available, so create the port.
280    icachePort = new IcachePort(this);
281
282    Port *mem_dport = mem->getPort("");
283    icachePort->setPeer(mem_dport);
284    mem_dport->setPeer(icachePort);
285
286#if USE_CHECKER
287    if (cpu->checker) {
288        cpu->checker->setIcachePort(icachePort);
289    }
290#endif
291
292    // Fetch needs to start fetching instructions at the very beginning,
293    // so it must start up in active state.
294    switchToActive();
295}
296
297template<class Impl>
298void
299DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
300{
301    DPRINTF(Fetch, "Setting the time buffer pointer.\n");
302    timeBuffer = time_buffer;
303
304    // Create wires to get information from proper places in time buffer.
305    fromDecode = timeBuffer->getWire(-decodeToFetchDelay);
306    fromRename = timeBuffer->getWire(-renameToFetchDelay);
307    fromIEW = timeBuffer->getWire(-iewToFetchDelay);
308    fromCommit = timeBuffer->getWire(-commitToFetchDelay);
309}
310
311template<class Impl>
312void
313DefaultFetch<Impl>::setActiveThreads(list<unsigned> *at_ptr)
314{
315    DPRINTF(Fetch, "Setting active threads list pointer.\n");
316    activeThreads = at_ptr;
317}
318
319template<class Impl>
320void
321DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
322{
323    DPRINTF(Fetch, "Setting the fetch queue pointer.\n");
324    fetchQueue = fq_ptr;
325
326    // Create wire to write information to proper place in fetch queue.
327    toDecode = fetchQueue->getWire(0);
328}
329
330template<class Impl>
331void
332DefaultFetch<Impl>::initStage()
333{
334    // Setup PC and nextPC with initial state.
335    for (int tid = 0; tid < numThreads; tid++) {
336        PC[tid] = cpu->readPC(tid);
337        nextPC[tid] = cpu->readNextPC(tid);
338#if THE_ISA != ALPHA_ISA
339        nextNPC[tid] = cpu->readNextNPC(tid);
340#endif
341    }
342}
343
344template<class Impl>
345void
346DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
347{
348    unsigned tid = pkt->req->getThreadNum();
349
350    DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid);
351
352    // Only change the status if it's still waiting on the icache access
353    // to return.
354    if (fetchStatus[tid] != IcacheWaitResponse ||
355        pkt->req != memReq[tid] ||
356        isSwitchedOut()) {
357        ++fetchIcacheSquashes;
358        delete pkt->req;
359        delete pkt;
360        return;
361    }
362
363    // Wake up the CPU (if it went to sleep and was waiting on this completion
364    // event).
365    cpu->wakeCPU();
366
367    DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",
368            tid);
369
370    switchToActive();
371
372    // Only switch to IcacheAccessComplete if we're not stalled as well.
373    if (checkStall(tid)) {
374        fetchStatus[tid] = Blocked;
375    } else {
376        fetchStatus[tid] = IcacheAccessComplete;
377    }
378
379    // Reset the mem req to NULL.
380    delete pkt->req;
381    delete pkt;
382    memReq[tid] = NULL;
383}
384
385template <class Impl>
386void
387DefaultFetch<Impl>::switchOut()
388{
389    // Fetch is ready to switch out at any time.
390    switchedOut = true;
391    cpu->signalSwitched();
392}
393
394template <class Impl>
395void
396DefaultFetch<Impl>::doSwitchOut()
397{
398    // Branch predictor needs to have its state cleared.
399    branchPred.switchOut();
400}
401
402template <class Impl>
403void
404DefaultFetch<Impl>::takeOverFrom()
405{
406    // Reset all state
407    for (int i = 0; i < Impl::MaxThreads; ++i) {
408        stalls[i].decode = 0;
409        stalls[i].rename = 0;
410        stalls[i].iew = 0;
411        stalls[i].commit = 0;
412        PC[i] = cpu->readPC(i);
413        nextPC[i] = cpu->readNextPC(i);
414#if THE_ISA != ALPHA_ISA
415        nextNPC[i] = cpu->readNextNPC(i);
416#endif
417        fetchStatus[i] = Running;
418    }
419    numInst = 0;
420    wroteToTimeBuffer = false;
421    _status = Inactive;
422    switchedOut = false;
423    branchPred.takeOverFrom();
424}
425
426template <class Impl>
427void
428DefaultFetch<Impl>::wakeFromQuiesce()
429{
430    DPRINTF(Fetch, "Waking up from quiesce\n");
431    // Hopefully this is safe
432    // @todo: Allow other threads to wake from quiesce.
433    fetchStatus[0] = Running;
434}
435
436template <class Impl>
437inline void
438DefaultFetch<Impl>::switchToActive()
439{
440    if (_status == Inactive) {
441        DPRINTF(Activity, "Activating stage.\n");
442
443        cpu->activateStage(O3CPU::FetchIdx);
444
445        _status = Active;
446    }
447}
448
449template <class Impl>
450inline void
451DefaultFetch<Impl>::switchToInactive()
452{
453    if (_status == Active) {
454        DPRINTF(Activity, "Deactivating stage.\n");
455
456        cpu->deactivateStage(O3CPU::FetchIdx);
457
458        _status = Inactive;
459    }
460}
461
462template <class Impl>
463bool
464DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC)
465{
466    // Do branch prediction check here.
467    // A bit of a misnomer...next_PC is actually the current PC until
468    // this function updates it.
469    bool predict_taken;
470
471    if (!inst->isControl()) {
472        next_PC = next_PC + instSize;
473        inst->setPredTarg(next_PC);
474        return false;
475    }
476
477    predict_taken = branchPred.predict(inst, next_PC, inst->threadNumber);
478
479    ++fetchedBranches;
480
481    if (predict_taken) {
482        ++predictedBranches;
483    }
484
485    return predict_taken;
486}
487
488template <class Impl>
489bool
490DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid)
491{
492    Fault fault = NoFault;
493
494#if FULL_SYSTEM
495    // Flag to say whether or not address is physical addr.
496    unsigned flags = cpu->inPalMode(fetch_PC) ? PHYSICAL : 0;
497#else
498    unsigned flags = 0;
499#endif // FULL_SYSTEM
500
501    if (cacheBlocked || (interruptPending && flags == 0) || switchedOut) {
502        // Hold off fetch from getting new instructions when:
503        // Cache is blocked, or
504        // while an interrupt is pending and we're not in PAL mode, or
505        // fetch is switched out.
506        return false;
507    }
508
509    // Align the fetch PC so it's at the start of a cache block.
510    fetch_PC = icacheBlockAlignPC(fetch_PC);
511
512    // Setup the memReq to do a read of the first instruction's address.
513    // Set the appropriate read size and flags as well.
514    // Build request here.
515    RequestPtr mem_req = new Request(tid, fetch_PC, cacheBlkSize, flags,
516                                     fetch_PC, cpu->readCpuId(), tid);
517
518    memReq[tid] = mem_req;
519
520    // Translate the instruction request.
521    fault = cpu->translateInstReq(mem_req, cpu->thread[tid]);
522
523    // In the case of faults, the fetch stage may need to stall and wait
524    // for the ITB miss to be handled.
525
526    // If translation was successful, attempt to read the first
527    // instruction.
528    if (fault == NoFault) {
529#if 0
530        if (cpu->system->memctrl->badaddr(memReq[tid]->paddr) ||
531            memReq[tid]->flags & UNCACHEABLE) {
532            DPRINTF(Fetch, "Fetch: Bad address %#x (hopefully on a "
533                    "misspeculating path)!",
534                    memReq[tid]->paddr);
535            ret_fault = TheISA::genMachineCheckFault();
536            return false;
537        }
538#endif
539
540        // Build packet here.
541        PacketPtr data_pkt = new Packet(mem_req,
542                                        Packet::ReadReq, Packet::Broadcast);
543        data_pkt->dataStatic(cacheData[tid]);
544
545        DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
546
547        fetchedCacheLines++;
548
549        // Now do the timing access to see whether or not the instruction
550        // exists within the cache.
551        if (!icachePort->sendTiming(data_pkt)) {
552            assert(retryPkt == NULL);
553            assert(retryTid == -1);
554            DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
555            fetchStatus[tid] = IcacheWaitRetry;
556            retryPkt = data_pkt;
557            retryTid = tid;
558            cacheBlocked = true;
559            return false;
560        }
561
562        DPRINTF(Fetch, "[tid:%i]: Doing cache access.\n", tid);
563
564        lastIcacheStall[tid] = curTick;
565
566        DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
567                "response.\n", tid);
568
569        fetchStatus[tid] = IcacheWaitResponse;
570    } else {
571        delete mem_req;
572        memReq[tid] = NULL;
573    }
574
575    ret_fault = fault;
576    return true;
577}
578
579template <class Impl>
580inline void
581DefaultFetch<Impl>::doSquash(const Addr &new_PC, unsigned tid)
582{
583    DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x.\n",
584            tid, new_PC);
585
586    PC[tid] = new_PC;
587    nextPC[tid] = new_PC + instSize;
588
589    // Clear the icache miss if it's outstanding.
590    if (fetchStatus[tid] == IcacheWaitResponse) {
591        DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
592                tid);
593        memReq[tid] = NULL;
594    }
595
596    // Get rid of the retrying packet if it was from this thread.
597    if (retryTid == tid) {
598        assert(cacheBlocked);
599        cacheBlocked = false;
600        retryTid = -1;
601        retryPkt = NULL;
602        delete retryPkt->req;
603        delete retryPkt;
604    }
605
606    fetchStatus[tid] = Squashing;
607
608    ++fetchSquashCycles;
609}
610
611template<class Impl>
612void
613DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC,
614                                     const InstSeqNum &seq_num,
615                                     unsigned tid)
616{
617    DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid);
618
619    doSquash(new_PC, tid);
620
621    // Tell the CPU to remove any instructions that are in flight between
622    // fetch and decode.
623    cpu->removeInstsUntil(seq_num, tid);
624}
625
626template<class Impl>
627bool
628DefaultFetch<Impl>::checkStall(unsigned tid) const
629{
630    bool ret_val = false;
631
632    if (cpu->contextSwitch) {
633        DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid);
634        ret_val = true;
635    } else if (stalls[tid].decode) {
636        DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid);
637        ret_val = true;
638    } else if (stalls[tid].rename) {
639        DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid);
640        ret_val = true;
641    } else if (stalls[tid].iew) {
642        DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid);
643        ret_val = true;
644    } else if (stalls[tid].commit) {
645        DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid);
646        ret_val = true;
647    }
648
649    return ret_val;
650}
651
652template<class Impl>
653typename DefaultFetch<Impl>::FetchStatus
654DefaultFetch<Impl>::updateFetchStatus()
655{
656    //Check Running
657    list<unsigned>::iterator threads = (*activeThreads).begin();
658
659    while (threads != (*activeThreads).end()) {
660
661        unsigned tid = *threads++;
662
663        if (fetchStatus[tid] == Running ||
664            fetchStatus[tid] == Squashing ||
665            fetchStatus[tid] == IcacheAccessComplete) {
666
667            if (_status == Inactive) {
668                DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid);
669
670                if (fetchStatus[tid] == IcacheAccessComplete) {
671                    DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache"
672                            "completion\n",tid);
673                }
674
675                cpu->activateStage(O3CPU::FetchIdx);
676            }
677
678            return Active;
679        }
680    }
681
682    // Stage is switching from active to inactive, notify CPU of it.
683    if (_status == Active) {
684        DPRINTF(Activity, "Deactivating stage.\n");
685
686        cpu->deactivateStage(O3CPU::FetchIdx);
687    }
688
689    return Inactive;
690}
691
692template <class Impl>
693void
694DefaultFetch<Impl>::squash(const Addr &new_PC, unsigned tid)
695{
696    DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid);
697
698    doSquash(new_PC, tid);
699
700    // Tell the CPU to remove any instructions that are not in the ROB.
701    cpu->removeInstsNotInROB(tid);
702}
703
704template <class Impl>
705void
706DefaultFetch<Impl>::tick()
707{
708    list<unsigned>::iterator threads = (*activeThreads).begin();
709    bool status_change = false;
710
711    wroteToTimeBuffer = false;
712
713    while (threads != (*activeThreads).end()) {
714        unsigned tid = *threads++;
715
716        // Check the signals for each thread to determine the proper status
717        // for each thread.
718        bool updated_status = checkSignalsAndUpdate(tid);
719        status_change =  status_change || updated_status;
720    }
721
722    DPRINTF(Fetch, "Running stage.\n");
723
724    // Reset the number of the instruction we're fetching.
725    numInst = 0;
726
727#if FULL_SYSTEM
728    if (fromCommit->commitInfo[0].interruptPending) {
729        interruptPending = true;
730    }
731
732    if (fromCommit->commitInfo[0].clearInterrupt) {
733        interruptPending = false;
734    }
735#endif
736
737    for (threadFetched = 0; threadFetched < numFetchingThreads;
738         threadFetched++) {
739        // Fetch each of the actively fetching threads.
740        fetch(status_change);
741    }
742
743    // Record number of instructions fetched this cycle for distribution.
744    fetchNisnDist.sample(numInst);
745
746    if (status_change) {
747        // Change the fetch stage status if there was a status change.
748        _status = updateFetchStatus();
749    }
750
751    // If there was activity this cycle, inform the CPU of it.
752    if (wroteToTimeBuffer || cpu->contextSwitch) {
753        DPRINTF(Activity, "Activity this cycle.\n");
754
755        cpu->activityThisCycle();
756    }
757}
758
759template <class Impl>
760bool
761DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid)
762{
763    // Update the per thread stall statuses.
764    if (fromDecode->decodeBlock[tid]) {
765        stalls[tid].decode = true;
766    }
767
768    if (fromDecode->decodeUnblock[tid]) {
769        assert(stalls[tid].decode);
770        assert(!fromDecode->decodeBlock[tid]);
771        stalls[tid].decode = false;
772    }
773
774    if (fromRename->renameBlock[tid]) {
775        stalls[tid].rename = true;
776    }
777
778    if (fromRename->renameUnblock[tid]) {
779        assert(stalls[tid].rename);
780        assert(!fromRename->renameBlock[tid]);
781        stalls[tid].rename = false;
782    }
783
784    if (fromIEW->iewBlock[tid]) {
785        stalls[tid].iew = true;
786    }
787
788    if (fromIEW->iewUnblock[tid]) {
789        assert(stalls[tid].iew);
790        assert(!fromIEW->iewBlock[tid]);
791        stalls[tid].iew = false;
792    }
793
794    if (fromCommit->commitBlock[tid]) {
795        stalls[tid].commit = true;
796    }
797
798    if (fromCommit->commitUnblock[tid]) {
799        assert(stalls[tid].commit);
800        assert(!fromCommit->commitBlock[tid]);
801        stalls[tid].commit = false;
802    }
803
804    // Check squash signals from commit.
805    if (fromCommit->commitInfo[tid].squash) {
806
807        DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
808                "from commit.\n",tid);
809
810        // In any case, squash.
811        squash(fromCommit->commitInfo[tid].nextPC,tid);
812
813        // Also check if there's a mispredict that happened.
814        if (fromCommit->commitInfo[tid].branchMispredict) {
815            branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
816                              fromCommit->commitInfo[tid].nextPC,
817                              fromCommit->commitInfo[tid].branchTaken,
818                              tid);
819        } else {
820            branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
821                              tid);
822        }
823
824        return true;
825    } else if (fromCommit->commitInfo[tid].doneSeqNum) {
826        // Update the branch predictor if it wasn't a squashed instruction
827        // that was broadcasted.
828        branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid);
829    }
830
831    // Check ROB squash signals from commit.
832    if (fromCommit->commitInfo[tid].robSquashing) {
833        DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid);
834
835        // Continue to squash.
836        fetchStatus[tid] = Squashing;
837
838        return true;
839    }
840
841    // Check squash signals from decode.
842    if (fromDecode->decodeInfo[tid].squash) {
843        DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
844                "from decode.\n",tid);
845
846        // Update the branch predictor.
847        if (fromDecode->decodeInfo[tid].branchMispredict) {
848            branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
849                              fromDecode->decodeInfo[tid].nextPC,
850                              fromDecode->decodeInfo[tid].branchTaken,
851                              tid);
852        } else {
853            branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
854                              tid);
855        }
856
857        if (fetchStatus[tid] != Squashing) {
858            // Squash unless we're already squashing
859            squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
860                             fromDecode->decodeInfo[tid].doneSeqNum,
861                             tid);
862
863            return true;
864        }
865    }
866
867    if (checkStall(tid) && fetchStatus[tid] != IcacheWaitResponse) {
868        DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid);
869
870        fetchStatus[tid] = Blocked;
871
872        return true;
873    }
874
875    if (fetchStatus[tid] == Blocked ||
876        fetchStatus[tid] == Squashing) {
877        // Switch status to running if fetch isn't being told to block or
878        // squash this cycle.
879        DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n",
880                tid);
881
882        fetchStatus[tid] = Running;
883
884        return true;
885    }
886
887    // If we've reached this point, we have not gotten any signals that
888    // cause fetch to change its status.  Fetch remains the same as before.
889    return false;
890}
891
892template<class Impl>
893void
894DefaultFetch<Impl>::fetch(bool &status_change)
895{
896    //////////////////////////////////////////
897    // Start actual fetch
898    //////////////////////////////////////////
899    int tid = getFetchingThread(fetchPolicy);
900
901    if (tid == -1) {
902        DPRINTF(Fetch,"There are no more threads available to fetch from.\n");
903
904        // Breaks looping condition in tick()
905        threadFetched = numFetchingThreads;
906        return;
907    }
908
909    DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
910
911    // The current PC.
912    Addr &fetch_PC = PC[tid];
913
914    // Fault code for memory access.
915    Fault fault = NoFault;
916
917    // If returning from the delay of a cache miss, then update the status
918    // to running, otherwise do the cache access.  Possibly move this up
919    // to tick() function.
920    if (fetchStatus[tid] == IcacheAccessComplete) {
921        DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n",
922                tid);
923
924        fetchStatus[tid] = Running;
925        status_change = true;
926    } else if (fetchStatus[tid] == Running) {
927        DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
928                "instruction, starting at PC %08p.\n",
929                tid, fetch_PC);
930
931        bool fetch_success = fetchCacheLine(fetch_PC, fault, tid);
932        if (!fetch_success) {
933            if (cacheBlocked) {
934                ++icacheStallCycles;
935            } else {
936                ++fetchMiscStallCycles;
937            }
938            return;
939        }
940    } else {
941        if (fetchStatus[tid] == Idle) {
942            ++fetchIdleCycles;
943        } else if (fetchStatus[tid] == Blocked) {
944            ++fetchBlockedCycles;
945        } else if (fetchStatus[tid] == Squashing) {
946            ++fetchSquashCycles;
947        } else if (fetchStatus[tid] == IcacheWaitResponse) {
948            ++icacheStallCycles;
949        }
950
951        // Status is Idle, Squashing, Blocked, or IcacheWaitResponse, so
952        // fetch should do nothing.
953        return;
954    }
955
956    ++fetchCycles;
957
958    // If we had a stall due to an icache miss, then return.
959    if (fetchStatus[tid] == IcacheWaitResponse) {
960        ++icacheStallCycles;
961        status_change = true;
962        return;
963    }
964
965    Addr next_PC = fetch_PC;
966    InstSeqNum inst_seq;
967    MachInst inst;
968    ExtMachInst ext_inst;
969    // @todo: Fix this hack.
970    unsigned offset = (fetch_PC & cacheBlkMask) & ~3;
971
972    if (fault == NoFault) {
973        // If the read of the first instruction was successful, then grab the
974        // instructions from the rest of the cache line and put them into the
975        // queue heading to decode.
976
977        DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
978                "decode.\n",tid);
979
980        // Need to keep track of whether or not a predicted branch
981        // ended this fetch block.
982        bool predicted_branch = false;
983
984        for (;
985             offset < cacheBlkSize &&
986                 numInst < fetchWidth &&
987                 !predicted_branch;
988             ++numInst) {
989
990            // Get a sequence number.
991            inst_seq = cpu->getAndIncrementInstSeq();
992
993            // Make sure this is a valid index.
994            assert(offset <= cacheBlkSize - instSize);
995
996            // Get the instruction from the array of the cache line.
997            inst = gtoh(*reinterpret_cast<MachInst *>
998                        (&cacheData[tid][offset]));
999
1000            ext_inst = TheISA::makeExtMI(inst, fetch_PC);
1001
1002            // Create a new DynInst from the instruction fetched.
1003            DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
1004                                                 next_PC,
1005                                                 inst_seq, cpu);
1006            instruction->setTid(tid);
1007
1008            instruction->setASID(tid);
1009
1010            instruction->setThreadState(cpu->thread[tid]);
1011
1012            DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created "
1013                    "[sn:%lli]\n",
1014                    tid, instruction->readPC(), inst_seq);
1015
1016            DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n",
1017                    tid, instruction->staticInst->disassemble(fetch_PC));
1018
1019            instruction->traceData =
1020                Trace::getInstRecord(curTick, cpu->tcBase(tid), cpu,
1021                                     instruction->staticInst,
1022                                     instruction->readPC(),tid);
1023
1024            predicted_branch = lookupAndUpdateNextPC(instruction, next_PC);
1025
1026            // Add instruction to the CPU's list of instructions.
1027            instruction->setInstListIt(cpu->addInst(instruction));
1028
1029            // Write the instruction to the first slot in the queue
1030            // that heads to decode.
1031            toDecode->insts[numInst] = instruction;
1032
1033            toDecode->size++;
1034
1035            // Increment stat of fetched instructions.
1036            ++fetchedInsts;
1037
1038            // Move to the next instruction, unless we have a branch.
1039            fetch_PC = next_PC;
1040
1041            if (instruction->isQuiesce()) {
1042                warn("cycle %lli: Quiesce instruction encountered, halting fetch!",
1043                     curTick);
1044                fetchStatus[tid] = QuiescePending;
1045                ++numInst;
1046                status_change = true;
1047                break;
1048            }
1049
1050            offset+= instSize;
1051        }
1052    }
1053
1054    if (numInst > 0) {
1055        wroteToTimeBuffer = true;
1056    }
1057
1058    // Now that fetching is completed, update the PC to signify what the next
1059    // cycle will be.
1060    if (fault == NoFault) {
1061        DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n",tid, next_PC);
1062
1063#if THE_ISA == ALPHA_ISA
1064        PC[tid] = next_PC;
1065        nextPC[tid] = next_PC + instSize;
1066#else
1067        PC[tid] = next_PC;
1068        nextPC[tid] = next_PC + instSize;
1069        nextPC[tid] = next_PC + instSize;
1070
1071        thread->setNextPC(thread->readNextNPC());
1072        thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
1073#endif
1074    } else {
1075        // We shouldn't be in an icache miss and also have a fault (an ITB
1076        // miss)
1077        if (fetchStatus[tid] == IcacheWaitResponse) {
1078            panic("Fetch should have exited prior to this!");
1079        }
1080
1081        // Send the fault to commit.  This thread will not do anything
1082        // until commit handles the fault.  The only other way it can
1083        // wake up is if a squash comes along and changes the PC.
1084#if FULL_SYSTEM
1085        assert(numInst != fetchWidth);
1086        // Get a sequence number.
1087        inst_seq = cpu->getAndIncrementInstSeq();
1088        // We will use a nop in order to carry the fault.
1089        ext_inst = TheISA::NoopMachInst;
1090
1091        // Create a new DynInst from the dummy nop.
1092        DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
1093                                             next_PC,
1094                                             inst_seq, cpu);
1095        instruction->setPredTarg(next_PC + instSize);
1096        instruction->setTid(tid);
1097
1098        instruction->setASID(tid);
1099
1100        instruction->setThreadState(cpu->thread[tid]);
1101
1102        instruction->traceData = NULL;
1103
1104        instruction->setInstListIt(cpu->addInst(instruction));
1105
1106        instruction->fault = fault;
1107
1108        toDecode->insts[numInst] = instruction;
1109        toDecode->size++;
1110
1111        DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid);
1112
1113        fetchStatus[tid] = TrapPending;
1114        status_change = true;
1115
1116        warn("cycle %lli: fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
1117#else // !FULL_SYSTEM
1118        warn("cycle %lli: fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
1119#endif // FULL_SYSTEM
1120    }
1121}
1122
1123template<class Impl>
1124void
1125DefaultFetch<Impl>::recvRetry()
1126{
1127    assert(cacheBlocked);
1128    if (retryPkt != NULL) {
1129        assert(retryTid != -1);
1130        assert(fetchStatus[retryTid] == IcacheWaitRetry);
1131
1132        if (icachePort->sendTiming(retryPkt)) {
1133            fetchStatus[retryTid] = IcacheWaitResponse;
1134            retryPkt = NULL;
1135            retryTid = -1;
1136            cacheBlocked = false;
1137        }
1138    } else {
1139        assert(retryTid == -1);
1140        // Access has been squashed since it was sent out.  Just clear
1141        // the cache being blocked.
1142        cacheBlocked = false;
1143    }
1144}
1145
1146///////////////////////////////////////
1147//                                   //
1148//  SMT FETCH POLICY MAINTAINED HERE //
1149//                                   //
1150///////////////////////////////////////
1151template<class Impl>
1152int
1153DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority)
1154{
1155    if (numThreads > 1) {
1156        switch (fetch_priority) {
1157
1158          case SingleThread:
1159            return 0;
1160
1161          case RoundRobin:
1162            return roundRobin();
1163
1164          case IQ:
1165            return iqCount();
1166
1167          case LSQ:
1168            return lsqCount();
1169
1170          case Branch:
1171            return branchCount();
1172
1173          default:
1174            return -1;
1175        }
1176    } else {
1177        int tid = *((*activeThreads).begin());
1178
1179        if (fetchStatus[tid] == Running ||
1180            fetchStatus[tid] == IcacheAccessComplete ||
1181            fetchStatus[tid] == Idle) {
1182            return tid;
1183        } else {
1184            return -1;
1185        }
1186    }
1187
1188}
1189
1190
1191template<class Impl>
1192int
1193DefaultFetch<Impl>::roundRobin()
1194{
1195    list<unsigned>::iterator pri_iter = priorityList.begin();
1196    list<unsigned>::iterator end      = priorityList.end();
1197
1198    int high_pri;
1199
1200    while (pri_iter != end) {
1201        high_pri = *pri_iter;
1202
1203        assert(high_pri <= numThreads);
1204
1205        if (fetchStatus[high_pri] == Running ||
1206            fetchStatus[high_pri] == IcacheAccessComplete ||
1207            fetchStatus[high_pri] == Idle) {
1208
1209            priorityList.erase(pri_iter);
1210            priorityList.push_back(high_pri);
1211
1212            return high_pri;
1213        }
1214
1215        pri_iter++;
1216    }
1217
1218    return -1;
1219}
1220
1221template<class Impl>
1222int
1223DefaultFetch<Impl>::iqCount()
1224{
1225    priority_queue<unsigned> PQ;
1226
1227    list<unsigned>::iterator threads = (*activeThreads).begin();
1228
1229    while (threads != (*activeThreads).end()) {
1230        unsigned tid = *threads++;
1231
1232        PQ.push(fromIEW->iewInfo[tid].iqCount);
1233    }
1234
1235    while (!PQ.empty()) {
1236
1237        unsigned high_pri = PQ.top();
1238
1239        if (fetchStatus[high_pri] == Running ||
1240            fetchStatus[high_pri] == IcacheAccessComplete ||
1241            fetchStatus[high_pri] == Idle)
1242            return high_pri;
1243        else
1244            PQ.pop();
1245
1246    }
1247
1248    return -1;
1249}
1250
1251template<class Impl>
1252int
1253DefaultFetch<Impl>::lsqCount()
1254{
1255    priority_queue<unsigned> PQ;
1256
1257
1258    list<unsigned>::iterator threads = (*activeThreads).begin();
1259
1260    while (threads != (*activeThreads).end()) {
1261        unsigned tid = *threads++;
1262
1263        PQ.push(fromIEW->iewInfo[tid].ldstqCount);
1264    }
1265
1266    while (!PQ.empty()) {
1267
1268        unsigned high_pri = PQ.top();
1269
1270        if (fetchStatus[high_pri] == Running ||
1271            fetchStatus[high_pri] == IcacheAccessComplete ||
1272            fetchStatus[high_pri] == Idle)
1273            return high_pri;
1274        else
1275            PQ.pop();
1276
1277    }
1278
1279    return -1;
1280}
1281
1282template<class Impl>
1283int
1284DefaultFetch<Impl>::branchCount()
1285{
1286    list<unsigned>::iterator threads = (*activeThreads).begin();
1287    panic("Branch Count Fetch policy unimplemented\n");
1288    return *threads;
1289}
1290