fetch_impl.hh revision 2790:2f8e9762bee9
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#include "config/use_checker.hh" 33 34#include "arch/isa_traits.hh" 35#include "arch/utility.hh" 36#include "cpu/checker/cpu.hh" 37#include "cpu/exetrace.hh" 38#include "cpu/o3/fetch.hh" 39#include "mem/packet.hh" 40#include "mem/request.hh" 41#include "sim/byteswap.hh" 42#include "sim/host.hh" 43#include "sim/root.hh" 44 45#if FULL_SYSTEM 46#include "arch/tlb.hh" 47#include "arch/vtophys.hh" 48#include "base/remote_gdb.hh" 49#include "sim/system.hh" 50#endif // FULL_SYSTEM 51 52#include <algorithm> 53 54using namespace std; 55using namespace TheISA; 56 57template<class Impl> 58Tick 59DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt) 60{ 61 panic("DefaultFetch doesn't expect recvAtomic callback!"); 62 return curTick; 63} 64 65template<class Impl> 66void 67DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt) 68{ 69 panic("DefaultFetch doesn't expect recvFunctional callback!"); 70} 71 72template<class Impl> 73void 74DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status) 75{ 76 if (status == RangeChange) 77 return; 78 79 panic("DefaultFetch doesn't expect recvStatusChange callback!"); 80} 81 82template<class Impl> 83bool 84DefaultFetch<Impl>::IcachePort::recvTiming(Packet *pkt) 85{ 86 fetch->processCacheCompletion(pkt); 87 return true; 88} 89 90template<class Impl> 91void 92DefaultFetch<Impl>::IcachePort::recvRetry() 93{ 94 fetch->recvRetry(); 95} 96 97template<class Impl> 98DefaultFetch<Impl>::DefaultFetch(Params *params) 99 : mem(params->mem), 100 branchPred(params), 101 decodeToFetchDelay(params->decodeToFetchDelay), 102 renameToFetchDelay(params->renameToFetchDelay), 103 iewToFetchDelay(params->iewToFetchDelay), 104 commitToFetchDelay(params->commitToFetchDelay), 105 fetchWidth(params->fetchWidth), 106 cacheBlocked(false), 107 retryPkt(NULL), 108 retryTid(-1), 109 numThreads(params->numberOfThreads), 110 numFetchingThreads(params->smtNumFetchingThreads), 111 interruptPending(false), 112 switchedOut(false) 113{ 114 if (numThreads > Impl::MaxThreads) 115 fatal("numThreads is not a valid value\n"); 116 117 DPRINTF(Fetch, "Fetch constructor called\n"); 118 119 // Set fetch stage's status to inactive. 120 _status = Inactive; 121 122 string policy = params->smtFetchPolicy; 123 124 // Convert string to lowercase 125 std::transform(policy.begin(), policy.end(), policy.begin(), 126 (int(*)(int)) tolower); 127 128 // Figure out fetch policy 129 if (policy == "singlethread") { 130 fetchPolicy = SingleThread; 131 } else if (policy == "roundrobin") { 132 fetchPolicy = RoundRobin; 133 DPRINTF(Fetch, "Fetch policy set to Round Robin\n"); 134 } else if (policy == "branch") { 135 fetchPolicy = Branch; 136 DPRINTF(Fetch, "Fetch policy set to Branch Count\n"); 137 } else if (policy == "iqcount") { 138 fetchPolicy = IQ; 139 DPRINTF(Fetch, "Fetch policy set to IQ count\n"); 140 } else if (policy == "lsqcount") { 141 fetchPolicy = LSQ; 142 DPRINTF(Fetch, "Fetch policy set to LSQ count\n"); 143 } else { 144 fatal("Invalid Fetch Policy. Options Are: {SingleThread," 145 " RoundRobin,LSQcount,IQcount}\n"); 146 } 147 148 // Size of cache block. 149 cacheBlkSize = 64; 150 151 // Create mask to get rid of offset bits. 152 cacheBlkMask = (cacheBlkSize - 1); 153 154 for (int tid=0; tid < numThreads; tid++) { 155 156 fetchStatus[tid] = Running; 157 158 priorityList.push_back(tid); 159 160 memReq[tid] = NULL; 161 162 // Create space to store a cache line. 163 cacheData[tid] = new uint8_t[cacheBlkSize]; 164 165 stalls[tid].decode = 0; 166 stalls[tid].rename = 0; 167 stalls[tid].iew = 0; 168 stalls[tid].commit = 0; 169 } 170 171 // Get the size of an instruction. 172 instSize = sizeof(MachInst); 173} 174 175template <class Impl> 176std::string 177DefaultFetch<Impl>::name() const 178{ 179 return cpu->name() + ".fetch"; 180} 181 182template <class Impl> 183void 184DefaultFetch<Impl>::regStats() 185{ 186 icacheStallCycles 187 .name(name() + ".icacheStallCycles") 188 .desc("Number of cycles fetch is stalled on an Icache miss") 189 .prereq(icacheStallCycles); 190 191 fetchedInsts 192 .name(name() + ".Insts") 193 .desc("Number of instructions fetch has processed") 194 .prereq(fetchedInsts); 195 196 fetchedBranches 197 .name(name() + ".Branches") 198 .desc("Number of branches that fetch encountered") 199 .prereq(fetchedBranches); 200 201 predictedBranches 202 .name(name() + ".predictedBranches") 203 .desc("Number of branches that fetch has predicted taken") 204 .prereq(predictedBranches); 205 206 fetchCycles 207 .name(name() + ".Cycles") 208 .desc("Number of cycles fetch has run and was not squashing or" 209 " blocked") 210 .prereq(fetchCycles); 211 212 fetchSquashCycles 213 .name(name() + ".SquashCycles") 214 .desc("Number of cycles fetch has spent squashing") 215 .prereq(fetchSquashCycles); 216 217 fetchIdleCycles 218 .name(name() + ".IdleCycles") 219 .desc("Number of cycles fetch was idle") 220 .prereq(fetchIdleCycles); 221 222 fetchBlockedCycles 223 .name(name() + ".BlockedCycles") 224 .desc("Number of cycles fetch has spent blocked") 225 .prereq(fetchBlockedCycles); 226 227 fetchedCacheLines 228 .name(name() + ".CacheLines") 229 .desc("Number of cache lines fetched") 230 .prereq(fetchedCacheLines); 231 232 fetchMiscStallCycles 233 .name(name() + ".MiscStallCycles") 234 .desc("Number of cycles fetch has spent waiting on interrupts, or " 235 "bad addresses, or out of MSHRs") 236 .prereq(fetchMiscStallCycles); 237 238 fetchIcacheSquashes 239 .name(name() + ".IcacheSquashes") 240 .desc("Number of outstanding Icache misses that were squashed") 241 .prereq(fetchIcacheSquashes); 242 243 fetchNisnDist 244 .init(/* base value */ 0, 245 /* last value */ fetchWidth, 246 /* bucket size */ 1) 247 .name(name() + ".rateDist") 248 .desc("Number of instructions fetched each cycle (Total)") 249 .flags(Stats::pdf); 250 251 idleRate 252 .name(name() + ".idleRate") 253 .desc("Percent of cycles fetch was idle") 254 .prereq(idleRate); 255 idleRate = fetchIdleCycles * 100 / cpu->numCycles; 256 257 branchRate 258 .name(name() + ".branchRate") 259 .desc("Number of branch fetches per cycle") 260 .flags(Stats::total); 261 branchRate = fetchedBranches / cpu->numCycles; 262 263 fetchRate 264 .name(name() + ".rate") 265 .desc("Number of inst fetches per cycle") 266 .flags(Stats::total); 267 fetchRate = fetchedInsts / cpu->numCycles; 268 269 branchPred.regStats(); 270} 271 272template<class Impl> 273void 274DefaultFetch<Impl>::setCPU(O3CPU *cpu_ptr) 275{ 276 DPRINTF(Fetch, "Setting the CPU pointer.\n"); 277 cpu = cpu_ptr; 278 279 // Name is finally available, so create the port. 280 icachePort = new IcachePort(this); 281 282 Port *mem_dport = mem->getPort(""); 283 icachePort->setPeer(mem_dport); 284 mem_dport->setPeer(icachePort); 285 286#if USE_CHECKER 287 if (cpu->checker) { 288 cpu->checker->setIcachePort(icachePort); 289 } 290#endif 291 292 // Fetch needs to start fetching instructions at the very beginning, 293 // so it must start up in active state. 294 switchToActive(); 295} 296 297template<class Impl> 298void 299DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer) 300{ 301 DPRINTF(Fetch, "Setting the time buffer pointer.\n"); 302 timeBuffer = time_buffer; 303 304 // Create wires to get information from proper places in time buffer. 305 fromDecode = timeBuffer->getWire(-decodeToFetchDelay); 306 fromRename = timeBuffer->getWire(-renameToFetchDelay); 307 fromIEW = timeBuffer->getWire(-iewToFetchDelay); 308 fromCommit = timeBuffer->getWire(-commitToFetchDelay); 309} 310 311template<class Impl> 312void 313DefaultFetch<Impl>::setActiveThreads(list<unsigned> *at_ptr) 314{ 315 DPRINTF(Fetch, "Setting active threads list pointer.\n"); 316 activeThreads = at_ptr; 317} 318 319template<class Impl> 320void 321DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 322{ 323 DPRINTF(Fetch, "Setting the fetch queue pointer.\n"); 324 fetchQueue = fq_ptr; 325 326 // Create wire to write information to proper place in fetch queue. 327 toDecode = fetchQueue->getWire(0); 328} 329 330template<class Impl> 331void 332DefaultFetch<Impl>::initStage() 333{ 334 // Setup PC and nextPC with initial state. 335 for (int tid = 0; tid < numThreads; tid++) { 336 PC[tid] = cpu->readPC(tid); 337 nextPC[tid] = cpu->readNextPC(tid); 338#if THE_ISA != ALPHA_ISA 339 nextNPC[tid] = cpu->readNextNPC(tid); 340#endif 341 } 342} 343 344template<class Impl> 345void 346DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt) 347{ 348 unsigned tid = pkt->req->getThreadNum(); 349 350 DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid); 351 352 // Only change the status if it's still waiting on the icache access 353 // to return. 354 if (fetchStatus[tid] != IcacheWaitResponse || 355 pkt->req != memReq[tid] || 356 isSwitchedOut()) { 357 ++fetchIcacheSquashes; 358 delete pkt->req; 359 delete pkt; 360 return; 361 } 362 363 // Wake up the CPU (if it went to sleep and was waiting on this completion 364 // event). 365 cpu->wakeCPU(); 366 367 DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n", 368 tid); 369 370 switchToActive(); 371 372 // Only switch to IcacheAccessComplete if we're not stalled as well. 373 if (checkStall(tid)) { 374 fetchStatus[tid] = Blocked; 375 } else { 376 fetchStatus[tid] = IcacheAccessComplete; 377 } 378 379 // Reset the mem req to NULL. 380 delete pkt->req; 381 delete pkt; 382 memReq[tid] = NULL; 383} 384 385template <class Impl> 386void 387DefaultFetch<Impl>::switchOut() 388{ 389 // Fetch is ready to switch out at any time. 390 switchedOut = true; 391 cpu->signalSwitched(); 392} 393 394template <class Impl> 395void 396DefaultFetch<Impl>::doSwitchOut() 397{ 398 // Branch predictor needs to have its state cleared. 399 branchPred.switchOut(); 400} 401 402template <class Impl> 403void 404DefaultFetch<Impl>::takeOverFrom() 405{ 406 // Reset all state 407 for (int i = 0; i < Impl::MaxThreads; ++i) { 408 stalls[i].decode = 0; 409 stalls[i].rename = 0; 410 stalls[i].iew = 0; 411 stalls[i].commit = 0; 412 PC[i] = cpu->readPC(i); 413 nextPC[i] = cpu->readNextPC(i); 414#if THE_ISA != ALPHA_ISA 415 nextNPC[i] = cpu->readNextNPC(i); 416#endif 417 fetchStatus[i] = Running; 418 } 419 numInst = 0; 420 wroteToTimeBuffer = false; 421 _status = Inactive; 422 switchedOut = false; 423 branchPred.takeOverFrom(); 424} 425 426template <class Impl> 427void 428DefaultFetch<Impl>::wakeFromQuiesce() 429{ 430 DPRINTF(Fetch, "Waking up from quiesce\n"); 431 // Hopefully this is safe 432 // @todo: Allow other threads to wake from quiesce. 433 fetchStatus[0] = Running; 434} 435 436template <class Impl> 437inline void 438DefaultFetch<Impl>::switchToActive() 439{ 440 if (_status == Inactive) { 441 DPRINTF(Activity, "Activating stage.\n"); 442 443 cpu->activateStage(O3CPU::FetchIdx); 444 445 _status = Active; 446 } 447} 448 449template <class Impl> 450inline void 451DefaultFetch<Impl>::switchToInactive() 452{ 453 if (_status == Active) { 454 DPRINTF(Activity, "Deactivating stage.\n"); 455 456 cpu->deactivateStage(O3CPU::FetchIdx); 457 458 _status = Inactive; 459 } 460} 461 462template <class Impl> 463bool 464DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC) 465{ 466 // Do branch prediction check here. 467 // A bit of a misnomer...next_PC is actually the current PC until 468 // this function updates it. 469 bool predict_taken; 470 471 if (!inst->isControl()) { 472 next_PC = next_PC + instSize; 473 inst->setPredTarg(next_PC); 474 return false; 475 } 476 477 predict_taken = branchPred.predict(inst, next_PC, inst->threadNumber); 478 479 ++fetchedBranches; 480 481 if (predict_taken) { 482 ++predictedBranches; 483 } 484 485 return predict_taken; 486} 487 488template <class Impl> 489bool 490DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid) 491{ 492 Fault fault = NoFault; 493 494#if FULL_SYSTEM 495 // Flag to say whether or not address is physical addr. 496 unsigned flags = cpu->inPalMode(fetch_PC) ? PHYSICAL : 0; 497#else 498 unsigned flags = 0; 499#endif // FULL_SYSTEM 500 501 if (cacheBlocked || (interruptPending && flags == 0) || switchedOut) { 502 // Hold off fetch from getting new instructions when: 503 // Cache is blocked, or 504 // while an interrupt is pending and we're not in PAL mode, or 505 // fetch is switched out. 506 return false; 507 } 508 509 // Align the fetch PC so it's at the start of a cache block. 510 fetch_PC = icacheBlockAlignPC(fetch_PC); 511 512 // Setup the memReq to do a read of the first instruction's address. 513 // Set the appropriate read size and flags as well. 514 // Build request here. 515 RequestPtr mem_req = new Request(tid, fetch_PC, cacheBlkSize, flags, 516 fetch_PC, cpu->readCpuId(), tid); 517 518 memReq[tid] = mem_req; 519 520 // Translate the instruction request. 521 fault = cpu->translateInstReq(mem_req, cpu->thread[tid]); 522 523 // In the case of faults, the fetch stage may need to stall and wait 524 // for the ITB miss to be handled. 525 526 // If translation was successful, attempt to read the first 527 // instruction. 528 if (fault == NoFault) { 529#if 0 530 if (cpu->system->memctrl->badaddr(memReq[tid]->paddr) || 531 memReq[tid]->flags & UNCACHEABLE) { 532 DPRINTF(Fetch, "Fetch: Bad address %#x (hopefully on a " 533 "misspeculating path)!", 534 memReq[tid]->paddr); 535 ret_fault = TheISA::genMachineCheckFault(); 536 return false; 537 } 538#endif 539 540 // Build packet here. 541 PacketPtr data_pkt = new Packet(mem_req, 542 Packet::ReadReq, Packet::Broadcast); 543 data_pkt->dataStatic(cacheData[tid]); 544 545 DPRINTF(Fetch, "Fetch: Doing instruction read.\n"); 546 547 fetchedCacheLines++; 548 549 // Now do the timing access to see whether or not the instruction 550 // exists within the cache. 551 if (!icachePort->sendTiming(data_pkt)) { 552 assert(retryPkt == NULL); 553 assert(retryTid == -1); 554 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid); 555 fetchStatus[tid] = IcacheWaitRetry; 556 retryPkt = data_pkt; 557 retryTid = tid; 558 cacheBlocked = true; 559 return false; 560 } 561 562 DPRINTF(Fetch, "Doing cache access.\n"); 563 564 lastIcacheStall[tid] = curTick; 565 566 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache " 567 "response.\n", tid); 568 569 fetchStatus[tid] = IcacheWaitResponse; 570 } else { 571 delete mem_req; 572 memReq[tid] = NULL; 573 } 574 575 ret_fault = fault; 576 return true; 577} 578 579template <class Impl> 580inline void 581DefaultFetch<Impl>::doSquash(const Addr &new_PC, unsigned tid) 582{ 583 DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x.\n", 584 tid, new_PC); 585 586 PC[tid] = new_PC; 587 nextPC[tid] = new_PC + instSize; 588 589 // Clear the icache miss if it's outstanding. 590 if (fetchStatus[tid] == IcacheWaitResponse) { 591 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n", 592 tid); 593 memReq[tid] = NULL; 594 } 595 596 // Get rid of the retrying packet if it was from this thread. 597 if (retryTid == tid) { 598 assert(cacheBlocked); 599 cacheBlocked = false; 600 retryTid = -1; 601 retryPkt = NULL; 602 delete retryPkt->req; 603 delete retryPkt; 604 } 605 606 fetchStatus[tid] = Squashing; 607 608 ++fetchSquashCycles; 609} 610 611template<class Impl> 612void 613DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC, 614 const InstSeqNum &seq_num, 615 unsigned tid) 616{ 617 DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid); 618 619 doSquash(new_PC, tid); 620 621 // Tell the CPU to remove any instructions that are in flight between 622 // fetch and decode. 623 cpu->removeInstsUntil(seq_num, tid); 624} 625 626template<class Impl> 627bool 628DefaultFetch<Impl>::checkStall(unsigned tid) const 629{ 630 bool ret_val = false; 631 632 if (cpu->contextSwitch) { 633 DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid); 634 ret_val = true; 635 } else if (stalls[tid].decode) { 636 DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid); 637 ret_val = true; 638 } else if (stalls[tid].rename) { 639 DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid); 640 ret_val = true; 641 } else if (stalls[tid].iew) { 642 DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid); 643 ret_val = true; 644 } else if (stalls[tid].commit) { 645 DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid); 646 ret_val = true; 647 } 648 649 return ret_val; 650} 651 652template<class Impl> 653typename DefaultFetch<Impl>::FetchStatus 654DefaultFetch<Impl>::updateFetchStatus() 655{ 656 //Check Running 657 list<unsigned>::iterator threads = (*activeThreads).begin(); 658 659 while (threads != (*activeThreads).end()) { 660 661 unsigned tid = *threads++; 662 663 if (fetchStatus[tid] == Running || 664 fetchStatus[tid] == Squashing || 665 fetchStatus[tid] == IcacheAccessComplete) { 666 667 if (_status == Inactive) { 668 DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid); 669 670 if (fetchStatus[tid] == IcacheAccessComplete) { 671 DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache" 672 "completion\n",tid); 673 } 674 675 cpu->activateStage(O3CPU::FetchIdx); 676 } 677 678 return Active; 679 } 680 } 681 682 // Stage is switching from active to inactive, notify CPU of it. 683 if (_status == Active) { 684 DPRINTF(Activity, "Deactivating stage.\n"); 685 686 cpu->deactivateStage(O3CPU::FetchIdx); 687 } 688 689 return Inactive; 690} 691 692template <class Impl> 693void 694DefaultFetch<Impl>::squash(const Addr &new_PC, unsigned tid) 695{ 696 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid); 697 698 doSquash(new_PC, tid); 699 700 // Tell the CPU to remove any instructions that are not in the ROB. 701 cpu->removeInstsNotInROB(tid); 702} 703 704template <class Impl> 705void 706DefaultFetch<Impl>::tick() 707{ 708 list<unsigned>::iterator threads = (*activeThreads).begin(); 709 bool status_change = false; 710 711 wroteToTimeBuffer = false; 712 713 while (threads != (*activeThreads).end()) { 714 unsigned tid = *threads++; 715 716 // Check the signals for each thread to determine the proper status 717 // for each thread. 718 bool updated_status = checkSignalsAndUpdate(tid); 719 status_change = status_change || updated_status; 720 } 721 722 DPRINTF(Fetch, "Running stage.\n"); 723 724 // Reset the number of the instruction we're fetching. 725 numInst = 0; 726 727 if (fromCommit->commitInfo[0].interruptPending) { 728 interruptPending = true; 729 } 730 if (fromCommit->commitInfo[0].clearInterrupt) { 731 interruptPending = false; 732 } 733 734 for (threadFetched = 0; threadFetched < numFetchingThreads; 735 threadFetched++) { 736 // Fetch each of the actively fetching threads. 737 fetch(status_change); 738 } 739 740 // Record number of instructions fetched this cycle for distribution. 741 fetchNisnDist.sample(numInst); 742 743 if (status_change) { 744 // Change the fetch stage status if there was a status change. 745 _status = updateFetchStatus(); 746 } 747 748 // If there was activity this cycle, inform the CPU of it. 749 if (wroteToTimeBuffer || cpu->contextSwitch) { 750 DPRINTF(Activity, "Activity this cycle.\n"); 751 752 cpu->activityThisCycle(); 753 } 754} 755 756template <class Impl> 757bool 758DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid) 759{ 760 // Update the per thread stall statuses. 761 if (fromDecode->decodeBlock[tid]) { 762 stalls[tid].decode = true; 763 } 764 765 if (fromDecode->decodeUnblock[tid]) { 766 assert(stalls[tid].decode); 767 assert(!fromDecode->decodeBlock[tid]); 768 stalls[tid].decode = false; 769 } 770 771 if (fromRename->renameBlock[tid]) { 772 stalls[tid].rename = true; 773 } 774 775 if (fromRename->renameUnblock[tid]) { 776 assert(stalls[tid].rename); 777 assert(!fromRename->renameBlock[tid]); 778 stalls[tid].rename = false; 779 } 780 781 if (fromIEW->iewBlock[tid]) { 782 stalls[tid].iew = true; 783 } 784 785 if (fromIEW->iewUnblock[tid]) { 786 assert(stalls[tid].iew); 787 assert(!fromIEW->iewBlock[tid]); 788 stalls[tid].iew = false; 789 } 790 791 if (fromCommit->commitBlock[tid]) { 792 stalls[tid].commit = true; 793 } 794 795 if (fromCommit->commitUnblock[tid]) { 796 assert(stalls[tid].commit); 797 assert(!fromCommit->commitBlock[tid]); 798 stalls[tid].commit = false; 799 } 800 801 // Check squash signals from commit. 802 if (fromCommit->commitInfo[tid].squash) { 803 804 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash " 805 "from commit.\n",tid); 806 807 // In any case, squash. 808 squash(fromCommit->commitInfo[tid].nextPC,tid); 809 810 // Also check if there's a mispredict that happened. 811 if (fromCommit->commitInfo[tid].branchMispredict) { 812 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum, 813 fromCommit->commitInfo[tid].nextPC, 814 fromCommit->commitInfo[tid].branchTaken, 815 tid); 816 } else { 817 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum, 818 tid); 819 } 820 821 return true; 822 } else if (fromCommit->commitInfo[tid].doneSeqNum) { 823 // Update the branch predictor if it wasn't a squashed instruction 824 // that was broadcasted. 825 branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid); 826 } 827 828 // Check ROB squash signals from commit. 829 if (fromCommit->commitInfo[tid].robSquashing) { 830 DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid); 831 832 // Continue to squash. 833 fetchStatus[tid] = Squashing; 834 835 return true; 836 } 837 838 // Check squash signals from decode. 839 if (fromDecode->decodeInfo[tid].squash) { 840 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash " 841 "from decode.\n",tid); 842 843 // Update the branch predictor. 844 if (fromDecode->decodeInfo[tid].branchMispredict) { 845 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum, 846 fromDecode->decodeInfo[tid].nextPC, 847 fromDecode->decodeInfo[tid].branchTaken, 848 tid); 849 } else { 850 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum, 851 tid); 852 } 853 854 if (fetchStatus[tid] != Squashing) { 855 // Squash unless we're already squashing 856 squashFromDecode(fromDecode->decodeInfo[tid].nextPC, 857 fromDecode->decodeInfo[tid].doneSeqNum, 858 tid); 859 860 return true; 861 } 862 } 863 864 if (checkStall(tid) && fetchStatus[tid] != IcacheWaitResponse) { 865 DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid); 866 867 fetchStatus[tid] = Blocked; 868 869 return true; 870 } 871 872 if (fetchStatus[tid] == Blocked || 873 fetchStatus[tid] == Squashing) { 874 // Switch status to running if fetch isn't being told to block or 875 // squash this cycle. 876 DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n", 877 tid); 878 879 fetchStatus[tid] = Running; 880 881 return true; 882 } 883 884 // If we've reached this point, we have not gotten any signals that 885 // cause fetch to change its status. Fetch remains the same as before. 886 return false; 887} 888 889template<class Impl> 890void 891DefaultFetch<Impl>::fetch(bool &status_change) 892{ 893 ////////////////////////////////////////// 894 // Start actual fetch 895 ////////////////////////////////////////// 896 int tid = getFetchingThread(fetchPolicy); 897 898 if (tid == -1) { 899 DPRINTF(Fetch,"There are no more threads available to fetch from.\n"); 900 901 // Breaks looping condition in tick() 902 threadFetched = numFetchingThreads; 903 return; 904 } 905 906 // The current PC. 907 Addr &fetch_PC = PC[tid]; 908 909 // Fault code for memory access. 910 Fault fault = NoFault; 911 912 // If returning from the delay of a cache miss, then update the status 913 // to running, otherwise do the cache access. Possibly move this up 914 // to tick() function. 915 if (fetchStatus[tid] == IcacheAccessComplete) { 916 DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n", 917 tid); 918 919 fetchStatus[tid] = Running; 920 status_change = true; 921 } else if (fetchStatus[tid] == Running) { 922 DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read " 923 "instruction, starting at PC %08p.\n", 924 tid, fetch_PC); 925 926 bool fetch_success = fetchCacheLine(fetch_PC, fault, tid); 927 if (!fetch_success) { 928 if (cacheBlocked) { 929 ++icacheStallCycles; 930 } else { 931 ++fetchMiscStallCycles; 932 } 933 return; 934 } 935 } else { 936 if (fetchStatus[tid] == Idle) { 937 ++fetchIdleCycles; 938 } else if (fetchStatus[tid] == Blocked) { 939 ++fetchBlockedCycles; 940 } else if (fetchStatus[tid] == Squashing) { 941 ++fetchSquashCycles; 942 } else if (fetchStatus[tid] == IcacheWaitResponse) { 943 ++icacheStallCycles; 944 } 945 946 // Status is Idle, Squashing, Blocked, or IcacheWaitResponse, so 947 // fetch should do nothing. 948 return; 949 } 950 951 ++fetchCycles; 952 953 // If we had a stall due to an icache miss, then return. 954 if (fetchStatus[tid] == IcacheWaitResponse) { 955 ++icacheStallCycles; 956 status_change = true; 957 return; 958 } 959 960 Addr next_PC = fetch_PC; 961 InstSeqNum inst_seq; 962 MachInst inst; 963 ExtMachInst ext_inst; 964 // @todo: Fix this hack. 965 unsigned offset = (fetch_PC & cacheBlkMask) & ~3; 966 967 if (fault == NoFault) { 968 // If the read of the first instruction was successful, then grab the 969 // instructions from the rest of the cache line and put them into the 970 // queue heading to decode. 971 972 DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to " 973 "decode.\n",tid); 974 975 // Need to keep track of whether or not a predicted branch 976 // ended this fetch block. 977 bool predicted_branch = false; 978 979 for (; 980 offset < cacheBlkSize && 981 numInst < fetchWidth && 982 !predicted_branch; 983 ++numInst) { 984 985 // Get a sequence number. 986 inst_seq = cpu->getAndIncrementInstSeq(); 987 988 // Make sure this is a valid index. 989 assert(offset <= cacheBlkSize - instSize); 990 991 // Get the instruction from the array of the cache line. 992 inst = gtoh(*reinterpret_cast<MachInst *> 993 (&cacheData[tid][offset])); 994 995 ext_inst = TheISA::makeExtMI(inst, fetch_PC); 996 997 // Create a new DynInst from the instruction fetched. 998 DynInstPtr instruction = new DynInst(ext_inst, fetch_PC, 999 next_PC, 1000 inst_seq, cpu); 1001 instruction->setTid(tid); 1002 1003 instruction->setASID(tid); 1004 1005 instruction->setThreadState(cpu->thread[tid]); 1006 1007 DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created " 1008 "[sn:%lli]\n", 1009 tid, instruction->readPC(), inst_seq); 1010 1011 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", 1012 tid, instruction->staticInst->disassemble(fetch_PC)); 1013 1014 instruction->traceData = 1015 Trace::getInstRecord(curTick, cpu->tcBase(tid), cpu, 1016 instruction->staticInst, 1017 instruction->readPC(),tid); 1018 1019 predicted_branch = lookupAndUpdateNextPC(instruction, next_PC); 1020 1021 // Add instruction to the CPU's list of instructions. 1022 instruction->setInstListIt(cpu->addInst(instruction)); 1023 1024 // Write the instruction to the first slot in the queue 1025 // that heads to decode. 1026 toDecode->insts[numInst] = instruction; 1027 1028 toDecode->size++; 1029 1030 // Increment stat of fetched instructions. 1031 ++fetchedInsts; 1032 1033 // Move to the next instruction, unless we have a branch. 1034 fetch_PC = next_PC; 1035 1036 if (instruction->isQuiesce()) { 1037 warn("cycle %lli: Quiesce instruction encountered, halting fetch!", 1038 curTick); 1039 fetchStatus[tid] = QuiescePending; 1040 ++numInst; 1041 status_change = true; 1042 break; 1043 } 1044 1045 offset+= instSize; 1046 } 1047 } 1048 1049 if (numInst > 0) { 1050 wroteToTimeBuffer = true; 1051 } 1052 1053 // Now that fetching is completed, update the PC to signify what the next 1054 // cycle will be. 1055 if (fault == NoFault) { 1056 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n",tid, next_PC); 1057 1058#if THE_ISA == ALPHA_ISA 1059 PC[tid] = next_PC; 1060 nextPC[tid] = next_PC + instSize; 1061#else 1062 PC[tid] = next_PC; 1063 nextPC[tid] = next_PC + instSize; 1064 nextPC[tid] = next_PC + instSize; 1065 1066 thread->setNextPC(thread->readNextNPC()); 1067 thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst)); 1068#endif 1069 } else { 1070 // We shouldn't be in an icache miss and also have a fault (an ITB 1071 // miss) 1072 if (fetchStatus[tid] == IcacheWaitResponse) { 1073 panic("Fetch should have exited prior to this!"); 1074 } 1075 1076 // Send the fault to commit. This thread will not do anything 1077 // until commit handles the fault. The only other way it can 1078 // wake up is if a squash comes along and changes the PC. 1079#if FULL_SYSTEM 1080 assert(numInst != fetchWidth); 1081 // Get a sequence number. 1082 inst_seq = cpu->getAndIncrementInstSeq(); 1083 // We will use a nop in order to carry the fault. 1084 ext_inst = TheISA::NoopMachInst; 1085 1086 // Create a new DynInst from the dummy nop. 1087 DynInstPtr instruction = new DynInst(ext_inst, fetch_PC, 1088 next_PC, 1089 inst_seq, cpu); 1090 instruction->setPredTarg(next_PC + instSize); 1091 instruction->setTid(tid); 1092 1093 instruction->setASID(tid); 1094 1095 instruction->setThreadState(cpu->thread[tid]); 1096 1097 instruction->traceData = NULL; 1098 1099 instruction->setInstListIt(cpu->addInst(instruction)); 1100 1101 instruction->fault = fault; 1102 1103 toDecode->insts[numInst] = instruction; 1104 toDecode->size++; 1105 1106 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid); 1107 1108 fetchStatus[tid] = TrapPending; 1109 status_change = true; 1110 1111 warn("cycle %lli: fault (%d) detected @ PC %08p", curTick, fault, PC[tid]); 1112#else // !FULL_SYSTEM 1113 warn("cycle %lli: fault (%d) detected @ PC %08p", curTick, fault, PC[tid]); 1114#endif // FULL_SYSTEM 1115 } 1116} 1117 1118template<class Impl> 1119void 1120DefaultFetch<Impl>::recvRetry() 1121{ 1122 assert(cacheBlocked); 1123 if (retryPkt != NULL) { 1124 assert(retryTid != -1); 1125 assert(fetchStatus[retryTid] == IcacheWaitRetry); 1126 1127 if (icachePort->sendTiming(retryPkt)) { 1128 fetchStatus[retryTid] = IcacheWaitResponse; 1129 retryPkt = NULL; 1130 retryTid = -1; 1131 cacheBlocked = false; 1132 } 1133 } else { 1134 assert(retryTid == -1); 1135 // Access has been squashed since it was sent out. Just clear 1136 // the cache being blocked. 1137 cacheBlocked = false; 1138 } 1139} 1140 1141/////////////////////////////////////// 1142// // 1143// SMT FETCH POLICY MAINTAINED HERE // 1144// // 1145/////////////////////////////////////// 1146template<class Impl> 1147int 1148DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority) 1149{ 1150 if (numThreads > 1) { 1151 switch (fetch_priority) { 1152 1153 case SingleThread: 1154 return 0; 1155 1156 case RoundRobin: 1157 return roundRobin(); 1158 1159 case IQ: 1160 return iqCount(); 1161 1162 case LSQ: 1163 return lsqCount(); 1164 1165 case Branch: 1166 return branchCount(); 1167 1168 default: 1169 return -1; 1170 } 1171 } else { 1172 int tid = *((*activeThreads).begin()); 1173 1174 if (fetchStatus[tid] == Running || 1175 fetchStatus[tid] == IcacheAccessComplete || 1176 fetchStatus[tid] == Idle) { 1177 return tid; 1178 } else { 1179 return -1; 1180 } 1181 } 1182 1183} 1184 1185 1186template<class Impl> 1187int 1188DefaultFetch<Impl>::roundRobin() 1189{ 1190 list<unsigned>::iterator pri_iter = priorityList.begin(); 1191 list<unsigned>::iterator end = priorityList.end(); 1192 1193 int high_pri; 1194 1195 while (pri_iter != end) { 1196 high_pri = *pri_iter; 1197 1198 assert(high_pri <= numThreads); 1199 1200 if (fetchStatus[high_pri] == Running || 1201 fetchStatus[high_pri] == IcacheAccessComplete || 1202 fetchStatus[high_pri] == Idle) { 1203 1204 priorityList.erase(pri_iter); 1205 priorityList.push_back(high_pri); 1206 1207 return high_pri; 1208 } 1209 1210 pri_iter++; 1211 } 1212 1213 return -1; 1214} 1215 1216template<class Impl> 1217int 1218DefaultFetch<Impl>::iqCount() 1219{ 1220 priority_queue<unsigned> PQ; 1221 1222 list<unsigned>::iterator threads = (*activeThreads).begin(); 1223 1224 while (threads != (*activeThreads).end()) { 1225 unsigned tid = *threads++; 1226 1227 PQ.push(fromIEW->iewInfo[tid].iqCount); 1228 } 1229 1230 while (!PQ.empty()) { 1231 1232 unsigned high_pri = PQ.top(); 1233 1234 if (fetchStatus[high_pri] == Running || 1235 fetchStatus[high_pri] == IcacheAccessComplete || 1236 fetchStatus[high_pri] == Idle) 1237 return high_pri; 1238 else 1239 PQ.pop(); 1240 1241 } 1242 1243 return -1; 1244} 1245 1246template<class Impl> 1247int 1248DefaultFetch<Impl>::lsqCount() 1249{ 1250 priority_queue<unsigned> PQ; 1251 1252 1253 list<unsigned>::iterator threads = (*activeThreads).begin(); 1254 1255 while (threads != (*activeThreads).end()) { 1256 unsigned tid = *threads++; 1257 1258 PQ.push(fromIEW->iewInfo[tid].ldstqCount); 1259 } 1260 1261 while (!PQ.empty()) { 1262 1263 unsigned high_pri = PQ.top(); 1264 1265 if (fetchStatus[high_pri] == Running || 1266 fetchStatus[high_pri] == IcacheAccessComplete || 1267 fetchStatus[high_pri] == Idle) 1268 return high_pri; 1269 else 1270 PQ.pop(); 1271 1272 } 1273 1274 return -1; 1275} 1276 1277template<class Impl> 1278int 1279DefaultFetch<Impl>::branchCount() 1280{ 1281 list<unsigned>::iterator threads = (*activeThreads).begin(); 1282 warn("Branch Count Fetch policy unimplemented\n"); 1283 return *threads; 1284} 1285