fetch_impl.hh revision 2733:e0eac8fc5774 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include "config/use_checker.hh"
32
33#include "arch/isa_traits.hh"
34#include "arch/utility.hh"
35#include "cpu/checker/cpu.hh"
36#include "cpu/exetrace.hh"
37#include "cpu/o3/fetch.hh"
38#include "mem/packet.hh"
39#include "mem/request.hh"
40#include "sim/byteswap.hh"
41#include "sim/host.hh"
42#include "sim/root.hh"
43
44#if FULL_SYSTEM
45#include "arch/tlb.hh"
46#include "arch/vtophys.hh"
47#include "base/remote_gdb.hh"
48#include "sim/system.hh"
49#endif // FULL_SYSTEM
50
51#include <algorithm>
52
53using namespace std;
54using namespace TheISA;
55
56template<class Impl>
57Tick
58DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt)
59{
60    panic("DefaultFetch doesn't expect recvAtomic callback!");
61    return curTick;
62}
63
64template<class Impl>
65void
66DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
67{
68    panic("DefaultFetch doesn't expect recvFunctional callback!");
69}
70
71template<class Impl>
72void
73DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status)
74{
75    if (status == RangeChange)
76        return;
77
78    panic("DefaultFetch doesn't expect recvStatusChange callback!");
79}
80
81template<class Impl>
82bool
83DefaultFetch<Impl>::IcachePort::recvTiming(Packet *pkt)
84{
85    fetch->processCacheCompletion(pkt);
86    return true;
87}
88
89template<class Impl>
90void
91DefaultFetch<Impl>::IcachePort::recvRetry()
92{
93    fetch->recvRetry();
94}
95
96template<class Impl>
97DefaultFetch<Impl>::DefaultFetch(Params *params)
98    : mem(params->mem),
99      branchPred(params),
100      decodeToFetchDelay(params->decodeToFetchDelay),
101      renameToFetchDelay(params->renameToFetchDelay),
102      iewToFetchDelay(params->iewToFetchDelay),
103      commitToFetchDelay(params->commitToFetchDelay),
104      fetchWidth(params->fetchWidth),
105      cacheBlocked(false),
106      retryPkt(NULL),
107      retryTid(-1),
108      numThreads(params->numberOfThreads),
109      numFetchingThreads(params->smtNumFetchingThreads),
110      interruptPending(false),
111      switchedOut(false)
112{
113    if (numThreads > Impl::MaxThreads)
114        fatal("numThreads is not a valid value\n");
115
116    DPRINTF(Fetch, "Fetch constructor called\n");
117
118    // Set fetch stage's status to inactive.
119    _status = Inactive;
120
121    string policy = params->smtFetchPolicy;
122
123    // Convert string to lowercase
124    std::transform(policy.begin(), policy.end(), policy.begin(),
125                   (int(*)(int)) tolower);
126
127    // Figure out fetch policy
128    if (policy == "singlethread") {
129        fetchPolicy = SingleThread;
130    } else if (policy == "roundrobin") {
131        fetchPolicy = RoundRobin;
132        DPRINTF(Fetch, "Fetch policy set to Round Robin\n");
133    } else if (policy == "branch") {
134        fetchPolicy = Branch;
135        DPRINTF(Fetch, "Fetch policy set to Branch Count\n");
136    } else if (policy == "iqcount") {
137        fetchPolicy = IQ;
138        DPRINTF(Fetch, "Fetch policy set to IQ count\n");
139    } else if (policy == "lsqcount") {
140        fetchPolicy = LSQ;
141        DPRINTF(Fetch, "Fetch policy set to LSQ count\n");
142    } else {
143        fatal("Invalid Fetch Policy. Options Are: {SingleThread,"
144              " RoundRobin,LSQcount,IQcount}\n");
145    }
146
147    // Size of cache block.
148    cacheBlkSize = 64;
149
150    // Create mask to get rid of offset bits.
151    cacheBlkMask = (cacheBlkSize - 1);
152
153    for (int tid=0; tid < numThreads; tid++) {
154
155        fetchStatus[tid] = Running;
156
157        priorityList.push_back(tid);
158
159        memReq[tid] = NULL;
160
161        // Create space to store a cache line.
162        cacheData[tid] = new uint8_t[cacheBlkSize];
163
164        stalls[tid].decode = 0;
165        stalls[tid].rename = 0;
166        stalls[tid].iew = 0;
167        stalls[tid].commit = 0;
168    }
169
170    // Get the size of an instruction.
171    instSize = sizeof(MachInst);
172}
173
174template <class Impl>
175std::string
176DefaultFetch<Impl>::name() const
177{
178    return cpu->name() + ".fetch";
179}
180
181template <class Impl>
182void
183DefaultFetch<Impl>::regStats()
184{
185    icacheStallCycles
186        .name(name() + ".icacheStallCycles")
187        .desc("Number of cycles fetch is stalled on an Icache miss")
188        .prereq(icacheStallCycles);
189
190    fetchedInsts
191        .name(name() + ".Insts")
192        .desc("Number of instructions fetch has processed")
193        .prereq(fetchedInsts);
194
195    fetchedBranches
196        .name(name() + ".Branches")
197        .desc("Number of branches that fetch encountered")
198        .prereq(fetchedBranches);
199
200    predictedBranches
201        .name(name() + ".predictedBranches")
202        .desc("Number of branches that fetch has predicted taken")
203        .prereq(predictedBranches);
204
205    fetchCycles
206        .name(name() + ".Cycles")
207        .desc("Number of cycles fetch has run and was not squashing or"
208              " blocked")
209        .prereq(fetchCycles);
210
211    fetchSquashCycles
212        .name(name() + ".SquashCycles")
213        .desc("Number of cycles fetch has spent squashing")
214        .prereq(fetchSquashCycles);
215
216    fetchIdleCycles
217        .name(name() + ".IdleCycles")
218        .desc("Number of cycles fetch was idle")
219        .prereq(fetchIdleCycles);
220
221    fetchBlockedCycles
222        .name(name() + ".BlockedCycles")
223        .desc("Number of cycles fetch has spent blocked")
224        .prereq(fetchBlockedCycles);
225
226    fetchedCacheLines
227        .name(name() + ".CacheLines")
228        .desc("Number of cache lines fetched")
229        .prereq(fetchedCacheLines);
230
231    fetchMiscStallCycles
232        .name(name() + ".MiscStallCycles")
233        .desc("Number of cycles fetch has spent waiting on interrupts, or "
234              "bad addresses, or out of MSHRs")
235        .prereq(fetchMiscStallCycles);
236
237    fetchIcacheSquashes
238        .name(name() + ".IcacheSquashes")
239        .desc("Number of outstanding Icache misses that were squashed")
240        .prereq(fetchIcacheSquashes);
241
242    fetchNisnDist
243        .init(/* base value */ 0,
244              /* last value */ fetchWidth,
245              /* bucket size */ 1)
246        .name(name() + ".rateDist")
247        .desc("Number of instructions fetched each cycle (Total)")
248        .flags(Stats::pdf);
249
250    idleRate
251        .name(name() + ".idleRate")
252        .desc("Percent of cycles fetch was idle")
253        .prereq(idleRate);
254    idleRate = fetchIdleCycles * 100 / cpu->numCycles;
255
256    branchRate
257        .name(name() + ".branchRate")
258        .desc("Number of branch fetches per cycle")
259        .flags(Stats::total);
260    branchRate = fetchedBranches / cpu->numCycles;
261
262    fetchRate
263        .name(name() + ".rate")
264        .desc("Number of inst fetches per cycle")
265        .flags(Stats::total);
266    fetchRate = fetchedInsts / cpu->numCycles;
267
268    branchPred.regStats();
269}
270
271template<class Impl>
272void
273DefaultFetch<Impl>::setCPU(O3CPU *cpu_ptr)
274{
275    DPRINTF(Fetch, "Setting the CPU pointer.\n");
276    cpu = cpu_ptr;
277
278    // Name is finally available, so create the port.
279    icachePort = new IcachePort(this);
280
281    Port *mem_dport = mem->getPort("");
282    icachePort->setPeer(mem_dport);
283    mem_dport->setPeer(icachePort);
284
285#if USE_CHECKER
286    if (cpu->checker) {
287        cpu->checker->setIcachePort(icachePort);
288    }
289#endif
290
291    // Fetch needs to start fetching instructions at the very beginning,
292    // so it must start up in active state.
293    switchToActive();
294}
295
296template<class Impl>
297void
298DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
299{
300    DPRINTF(Fetch, "Setting the time buffer pointer.\n");
301    timeBuffer = time_buffer;
302
303    // Create wires to get information from proper places in time buffer.
304    fromDecode = timeBuffer->getWire(-decodeToFetchDelay);
305    fromRename = timeBuffer->getWire(-renameToFetchDelay);
306    fromIEW = timeBuffer->getWire(-iewToFetchDelay);
307    fromCommit = timeBuffer->getWire(-commitToFetchDelay);
308}
309
310template<class Impl>
311void
312DefaultFetch<Impl>::setActiveThreads(list<unsigned> *at_ptr)
313{
314    DPRINTF(Fetch, "Setting active threads list pointer.\n");
315    activeThreads = at_ptr;
316}
317
318template<class Impl>
319void
320DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
321{
322    DPRINTF(Fetch, "Setting the fetch queue pointer.\n");
323    fetchQueue = fq_ptr;
324
325    // Create wire to write information to proper place in fetch queue.
326    toDecode = fetchQueue->getWire(0);
327}
328
329template<class Impl>
330void
331DefaultFetch<Impl>::initStage()
332{
333    // Setup PC and nextPC with initial state.
334    for (int tid = 0; tid < numThreads; tid++) {
335        PC[tid] = cpu->readPC(tid);
336        nextPC[tid] = cpu->readNextPC(tid);
337    }
338}
339
340template<class Impl>
341void
342DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
343{
344    unsigned tid = pkt->req->getThreadNum();
345
346    DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid);
347
348    // Only change the status if it's still waiting on the icache access
349    // to return.
350    if (fetchStatus[tid] != IcacheWaitResponse ||
351        pkt->req != memReq[tid] ||
352        isSwitchedOut()) {
353        ++fetchIcacheSquashes;
354        delete pkt->req;
355        delete pkt;
356        memReq[tid] = NULL;
357        return;
358    }
359
360    // Wake up the CPU (if it went to sleep and was waiting on this completion
361    // event).
362    cpu->wakeCPU();
363
364    DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",
365            tid);
366
367    switchToActive();
368
369    // Only switch to IcacheAccessComplete if we're not stalled as well.
370    if (checkStall(tid)) {
371        fetchStatus[tid] = Blocked;
372    } else {
373        fetchStatus[tid] = IcacheAccessComplete;
374    }
375
376    // Reset the mem req to NULL.
377    delete pkt->req;
378    delete pkt;
379    memReq[tid] = NULL;
380}
381
382template <class Impl>
383void
384DefaultFetch<Impl>::switchOut()
385{
386    // Fetch is ready to switch out at any time.
387    switchedOut = true;
388    cpu->signalSwitched();
389}
390
391template <class Impl>
392void
393DefaultFetch<Impl>::doSwitchOut()
394{
395    // Branch predictor needs to have its state cleared.
396    branchPred.switchOut();
397}
398
399template <class Impl>
400void
401DefaultFetch<Impl>::takeOverFrom()
402{
403    // Reset all state
404    for (int i = 0; i < Impl::MaxThreads; ++i) {
405        stalls[i].decode = 0;
406        stalls[i].rename = 0;
407        stalls[i].iew = 0;
408        stalls[i].commit = 0;
409        PC[i] = cpu->readPC(i);
410        nextPC[i] = cpu->readNextPC(i);
411        fetchStatus[i] = Running;
412    }
413    numInst = 0;
414    wroteToTimeBuffer = false;
415    _status = Inactive;
416    switchedOut = false;
417    branchPred.takeOverFrom();
418}
419
420template <class Impl>
421void
422DefaultFetch<Impl>::wakeFromQuiesce()
423{
424    DPRINTF(Fetch, "Waking up from quiesce\n");
425    // Hopefully this is safe
426    // @todo: Allow other threads to wake from quiesce.
427    fetchStatus[0] = Running;
428}
429
430template <class Impl>
431inline void
432DefaultFetch<Impl>::switchToActive()
433{
434    if (_status == Inactive) {
435        DPRINTF(Activity, "Activating stage.\n");
436
437        cpu->activateStage(O3CPU::FetchIdx);
438
439        _status = Active;
440    }
441}
442
443template <class Impl>
444inline void
445DefaultFetch<Impl>::switchToInactive()
446{
447    if (_status == Active) {
448        DPRINTF(Activity, "Deactivating stage.\n");
449
450        cpu->deactivateStage(O3CPU::FetchIdx);
451
452        _status = Inactive;
453    }
454}
455
456template <class Impl>
457bool
458DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC)
459{
460    // Do branch prediction check here.
461    // A bit of a misnomer...next_PC is actually the current PC until
462    // this function updates it.
463    bool predict_taken;
464
465    if (!inst->isControl()) {
466        next_PC = next_PC + instSize;
467        inst->setPredTarg(next_PC);
468        return false;
469    }
470
471    predict_taken = branchPred.predict(inst, next_PC, inst->threadNumber);
472
473    ++fetchedBranches;
474
475    if (predict_taken) {
476        ++predictedBranches;
477    }
478
479    return predict_taken;
480}
481
482template <class Impl>
483bool
484DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid)
485{
486    Fault fault = NoFault;
487
488#if FULL_SYSTEM
489    // Flag to say whether or not address is physical addr.
490    unsigned flags = cpu->inPalMode(fetch_PC) ? PHYSICAL : 0;
491#else
492    unsigned flags = 0;
493#endif // FULL_SYSTEM
494
495    if (cacheBlocked || (interruptPending && flags == 0) || switchedOut) {
496        // Hold off fetch from getting new instructions when:
497        // Cache is blocked, or
498        // while an interrupt is pending and we're not in PAL mode, or
499        // fetch is switched out.
500        return false;
501    }
502
503    // Align the fetch PC so it's at the start of a cache block.
504    fetch_PC = icacheBlockAlignPC(fetch_PC);
505
506    // Setup the memReq to do a read of the first instruction's address.
507    // Set the appropriate read size and flags as well.
508    // Build request here.
509    RequestPtr mem_req = new Request(tid, fetch_PC, cacheBlkSize, flags,
510                                     fetch_PC, cpu->readCpuId(), tid);
511
512    memReq[tid] = mem_req;
513
514    // Translate the instruction request.
515    fault = cpu->translateInstReq(mem_req, cpu->thread[tid]);
516
517    // In the case of faults, the fetch stage may need to stall and wait
518    // for the ITB miss to be handled.
519
520    // If translation was successful, attempt to read the first
521    // instruction.
522    if (fault == NoFault) {
523#if 0
524        if (cpu->system->memctrl->badaddr(memReq[tid]->paddr) ||
525            memReq[tid]->flags & UNCACHEABLE) {
526            DPRINTF(Fetch, "Fetch: Bad address %#x (hopefully on a "
527                    "misspeculating path)!",
528                    memReq[tid]->paddr);
529            ret_fault = TheISA::genMachineCheckFault();
530            return false;
531        }
532#endif
533
534        // Build packet here.
535        PacketPtr data_pkt = new Packet(mem_req,
536                                        Packet::ReadReq, Packet::Broadcast);
537        data_pkt->dataStatic(cacheData[tid]);
538
539        DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
540
541        fetchedCacheLines++;
542
543        // Now do the timing access to see whether or not the instruction
544        // exists within the cache.
545        if (!icachePort->sendTiming(data_pkt)) {
546            assert(retryPkt == NULL);
547            assert(retryTid == -1);
548            DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
549            fetchStatus[tid] = IcacheWaitRetry;
550            retryPkt = data_pkt;
551            retryTid = tid;
552            cacheBlocked = true;
553            return false;
554        }
555
556        DPRINTF(Fetch, "Doing cache access.\n");
557
558        lastIcacheStall[tid] = curTick;
559
560        DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
561                "response.\n", tid);
562
563        fetchStatus[tid] = IcacheWaitResponse;
564    } else {
565        delete mem_req;
566        memReq[tid] = NULL;
567    }
568
569    ret_fault = fault;
570    return true;
571}
572
573template <class Impl>
574inline void
575DefaultFetch<Impl>::doSquash(const Addr &new_PC, unsigned tid)
576{
577    DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x.\n",
578            tid, new_PC);
579
580    PC[tid] = new_PC;
581    nextPC[tid] = new_PC + instSize;
582
583    // Clear the icache miss if it's outstanding.
584    if (fetchStatus[tid] == IcacheWaitResponse) {
585        DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
586                tid);
587        memReq[tid] = NULL;
588    }
589
590    // Get rid of the retrying packet if it was from this thread.
591    if (retryTid == tid) {
592        assert(cacheBlocked);
593        cacheBlocked = false;
594        retryTid = -1;
595        retryPkt = NULL;
596        delete retryPkt->req;
597        delete retryPkt;
598    }
599
600    fetchStatus[tid] = Squashing;
601
602    ++fetchSquashCycles;
603}
604
605template<class Impl>
606void
607DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC,
608                                     const InstSeqNum &seq_num,
609                                     unsigned tid)
610{
611    DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid);
612
613    doSquash(new_PC, tid);
614
615    // Tell the CPU to remove any instructions that are in flight between
616    // fetch and decode.
617    cpu->removeInstsUntil(seq_num, tid);
618}
619
620template<class Impl>
621bool
622DefaultFetch<Impl>::checkStall(unsigned tid) const
623{
624    bool ret_val = false;
625
626    if (cpu->contextSwitch) {
627        DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid);
628        ret_val = true;
629    } else if (stalls[tid].decode) {
630        DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid);
631        ret_val = true;
632    } else if (stalls[tid].rename) {
633        DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid);
634        ret_val = true;
635    } else if (stalls[tid].iew) {
636        DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid);
637        ret_val = true;
638    } else if (stalls[tid].commit) {
639        DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid);
640        ret_val = true;
641    }
642
643    return ret_val;
644}
645
646template<class Impl>
647typename DefaultFetch<Impl>::FetchStatus
648DefaultFetch<Impl>::updateFetchStatus()
649{
650    //Check Running
651    list<unsigned>::iterator threads = (*activeThreads).begin();
652
653    while (threads != (*activeThreads).end()) {
654
655        unsigned tid = *threads++;
656
657        if (fetchStatus[tid] == Running ||
658            fetchStatus[tid] == Squashing ||
659            fetchStatus[tid] == IcacheAccessComplete) {
660
661            if (_status == Inactive) {
662                DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid);
663
664                if (fetchStatus[tid] == IcacheAccessComplete) {
665                    DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache"
666                            "completion\n",tid);
667                }
668
669                cpu->activateStage(O3CPU::FetchIdx);
670            }
671
672            return Active;
673        }
674    }
675
676    // Stage is switching from active to inactive, notify CPU of it.
677    if (_status == Active) {
678        DPRINTF(Activity, "Deactivating stage.\n");
679
680        cpu->deactivateStage(O3CPU::FetchIdx);
681    }
682
683    return Inactive;
684}
685
686template <class Impl>
687void
688DefaultFetch<Impl>::squash(const Addr &new_PC, unsigned tid)
689{
690    DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid);
691
692    doSquash(new_PC, tid);
693
694    // Tell the CPU to remove any instructions that are not in the ROB.
695    cpu->removeInstsNotInROB(tid);
696}
697
698template <class Impl>
699void
700DefaultFetch<Impl>::tick()
701{
702    list<unsigned>::iterator threads = (*activeThreads).begin();
703    bool status_change = false;
704
705    wroteToTimeBuffer = false;
706
707    while (threads != (*activeThreads).end()) {
708        unsigned tid = *threads++;
709
710        // Check the signals for each thread to determine the proper status
711        // for each thread.
712        bool updated_status = checkSignalsAndUpdate(tid);
713        status_change =  status_change || updated_status;
714    }
715
716    DPRINTF(Fetch, "Running stage.\n");
717
718    // Reset the number of the instruction we're fetching.
719    numInst = 0;
720
721    if (fromCommit->commitInfo[0].interruptPending) {
722        interruptPending = true;
723    }
724    if (fromCommit->commitInfo[0].clearInterrupt) {
725        interruptPending = false;
726    }
727
728    for (threadFetched = 0; threadFetched < numFetchingThreads;
729         threadFetched++) {
730        // Fetch each of the actively fetching threads.
731        fetch(status_change);
732    }
733
734    // Record number of instructions fetched this cycle for distribution.
735    fetchNisnDist.sample(numInst);
736
737    if (status_change) {
738        // Change the fetch stage status if there was a status change.
739        _status = updateFetchStatus();
740    }
741
742    // If there was activity this cycle, inform the CPU of it.
743    if (wroteToTimeBuffer || cpu->contextSwitch) {
744        DPRINTF(Activity, "Activity this cycle.\n");
745
746        cpu->activityThisCycle();
747    }
748}
749
750template <class Impl>
751bool
752DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid)
753{
754    // Update the per thread stall statuses.
755    if (fromDecode->decodeBlock[tid]) {
756        stalls[tid].decode = true;
757    }
758
759    if (fromDecode->decodeUnblock[tid]) {
760        assert(stalls[tid].decode);
761        assert(!fromDecode->decodeBlock[tid]);
762        stalls[tid].decode = false;
763    }
764
765    if (fromRename->renameBlock[tid]) {
766        stalls[tid].rename = true;
767    }
768
769    if (fromRename->renameUnblock[tid]) {
770        assert(stalls[tid].rename);
771        assert(!fromRename->renameBlock[tid]);
772        stalls[tid].rename = false;
773    }
774
775    if (fromIEW->iewBlock[tid]) {
776        stalls[tid].iew = true;
777    }
778
779    if (fromIEW->iewUnblock[tid]) {
780        assert(stalls[tid].iew);
781        assert(!fromIEW->iewBlock[tid]);
782        stalls[tid].iew = false;
783    }
784
785    if (fromCommit->commitBlock[tid]) {
786        stalls[tid].commit = true;
787    }
788
789    if (fromCommit->commitUnblock[tid]) {
790        assert(stalls[tid].commit);
791        assert(!fromCommit->commitBlock[tid]);
792        stalls[tid].commit = false;
793    }
794
795    // Check squash signals from commit.
796    if (fromCommit->commitInfo[tid].squash) {
797
798        DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
799                "from commit.\n",tid);
800
801        // In any case, squash.
802        squash(fromCommit->commitInfo[tid].nextPC,tid);
803
804        // Also check if there's a mispredict that happened.
805        if (fromCommit->commitInfo[tid].branchMispredict) {
806            branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
807                              fromCommit->commitInfo[tid].nextPC,
808                              fromCommit->commitInfo[tid].branchTaken,
809                              tid);
810        } else {
811            branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
812                              tid);
813        }
814
815        return true;
816    } else if (fromCommit->commitInfo[tid].doneSeqNum) {
817        // Update the branch predictor if it wasn't a squashed instruction
818        // that was broadcasted.
819        branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid);
820    }
821
822    // Check ROB squash signals from commit.
823    if (fromCommit->commitInfo[tid].robSquashing) {
824        DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid);
825
826        // Continue to squash.
827        fetchStatus[tid] = Squashing;
828
829        return true;
830    }
831
832    // Check squash signals from decode.
833    if (fromDecode->decodeInfo[tid].squash) {
834        DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
835                "from decode.\n",tid);
836
837        // Update the branch predictor.
838        if (fromDecode->decodeInfo[tid].branchMispredict) {
839            branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
840                              fromDecode->decodeInfo[tid].nextPC,
841                              fromDecode->decodeInfo[tid].branchTaken,
842                              tid);
843        } else {
844            branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
845                              tid);
846        }
847
848        if (fetchStatus[tid] != Squashing) {
849            // Squash unless we're already squashing
850            squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
851                             fromDecode->decodeInfo[tid].doneSeqNum,
852                             tid);
853
854            return true;
855        }
856    }
857
858    if (checkStall(tid) && fetchStatus[tid] != IcacheWaitResponse) {
859        DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid);
860
861        fetchStatus[tid] = Blocked;
862
863        return true;
864    }
865
866    if (fetchStatus[tid] == Blocked ||
867        fetchStatus[tid] == Squashing) {
868        // Switch status to running if fetch isn't being told to block or
869        // squash this cycle.
870        DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n",
871                tid);
872
873        fetchStatus[tid] = Running;
874
875        return true;
876    }
877
878    // If we've reached this point, we have not gotten any signals that
879    // cause fetch to change its status.  Fetch remains the same as before.
880    return false;
881}
882
883template<class Impl>
884void
885DefaultFetch<Impl>::fetch(bool &status_change)
886{
887    //////////////////////////////////////////
888    // Start actual fetch
889    //////////////////////////////////////////
890    int tid = getFetchingThread(fetchPolicy);
891
892    if (tid == -1) {
893        DPRINTF(Fetch,"There are no more threads available to fetch from.\n");
894
895        // Breaks looping condition in tick()
896        threadFetched = numFetchingThreads;
897        return;
898    }
899
900    // The current PC.
901    Addr &fetch_PC = PC[tid];
902
903    // Fault code for memory access.
904    Fault fault = NoFault;
905
906    // If returning from the delay of a cache miss, then update the status
907    // to running, otherwise do the cache access.  Possibly move this up
908    // to tick() function.
909    if (fetchStatus[tid] == IcacheAccessComplete) {
910        DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n",
911                tid);
912
913        fetchStatus[tid] = Running;
914        status_change = true;
915    } else if (fetchStatus[tid] == Running) {
916        DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
917                "instruction, starting at PC %08p.\n",
918                tid, fetch_PC);
919
920        bool fetch_success = fetchCacheLine(fetch_PC, fault, tid);
921        if (!fetch_success) {
922            if (cacheBlocked) {
923                ++icacheStallCycles;
924            } else {
925                ++fetchMiscStallCycles;
926            }
927            return;
928        }
929    } else {
930        if (fetchStatus[tid] == Idle) {
931            ++fetchIdleCycles;
932        } else if (fetchStatus[tid] == Blocked) {
933            ++fetchBlockedCycles;
934        } else if (fetchStatus[tid] == Squashing) {
935            ++fetchSquashCycles;
936        } else if (fetchStatus[tid] == IcacheWaitResponse) {
937            ++icacheStallCycles;
938        }
939
940        // Status is Idle, Squashing, Blocked, or IcacheWaitResponse, so
941        // fetch should do nothing.
942        return;
943    }
944
945    ++fetchCycles;
946
947    // If we had a stall due to an icache miss, then return.
948    if (fetchStatus[tid] == IcacheWaitResponse) {
949        ++icacheStallCycles;
950        status_change = true;
951        return;
952    }
953
954    Addr next_PC = fetch_PC;
955    InstSeqNum inst_seq;
956    MachInst inst;
957    ExtMachInst ext_inst;
958    // @todo: Fix this hack.
959    unsigned offset = (fetch_PC & cacheBlkMask) & ~3;
960
961    if (fault == NoFault) {
962        // If the read of the first instruction was successful, then grab the
963        // instructions from the rest of the cache line and put them into the
964        // queue heading to decode.
965
966        DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
967                "decode.\n",tid);
968
969        // Need to keep track of whether or not a predicted branch
970        // ended this fetch block.
971        bool predicted_branch = false;
972
973        for (;
974             offset < cacheBlkSize &&
975                 numInst < fetchWidth &&
976                 !predicted_branch;
977             ++numInst) {
978
979            // Get a sequence number.
980            inst_seq = cpu->getAndIncrementInstSeq();
981
982            // Make sure this is a valid index.
983            assert(offset <= cacheBlkSize - instSize);
984
985            // Get the instruction from the array of the cache line.
986            inst = gtoh(*reinterpret_cast<MachInst *>
987                        (&cacheData[tid][offset]));
988
989            ext_inst = TheISA::makeExtMI(inst, fetch_PC);
990
991            // Create a new DynInst from the instruction fetched.
992            DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
993                                                 next_PC,
994                                                 inst_seq, cpu);
995            instruction->setTid(tid);
996
997            instruction->setASID(tid);
998
999            instruction->setThreadState(cpu->thread[tid]);
1000
1001            DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created "
1002                    "[sn:%lli]\n",
1003                    tid, instruction->readPC(), inst_seq);
1004
1005            DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n",
1006                    tid, instruction->staticInst->disassemble(fetch_PC));
1007
1008            instruction->traceData =
1009                Trace::getInstRecord(curTick, cpu->tcBase(tid), cpu,
1010                                     instruction->staticInst,
1011                                     instruction->readPC(),tid);
1012
1013            predicted_branch = lookupAndUpdateNextPC(instruction, next_PC);
1014
1015            // Add instruction to the CPU's list of instructions.
1016            instruction->setInstListIt(cpu->addInst(instruction));
1017
1018            // Write the instruction to the first slot in the queue
1019            // that heads to decode.
1020            toDecode->insts[numInst] = instruction;
1021
1022            toDecode->size++;
1023
1024            // Increment stat of fetched instructions.
1025            ++fetchedInsts;
1026
1027            // Move to the next instruction, unless we have a branch.
1028            fetch_PC = next_PC;
1029
1030            if (instruction->isQuiesce()) {
1031                warn("%lli: Quiesce instruction encountered, halting fetch!",
1032                     curTick);
1033                fetchStatus[tid] = QuiescePending;
1034                ++numInst;
1035                status_change = true;
1036                break;
1037            }
1038
1039            offset+= instSize;
1040        }
1041    }
1042
1043    if (numInst > 0) {
1044        wroteToTimeBuffer = true;
1045    }
1046
1047    // Now that fetching is completed, update the PC to signify what the next
1048    // cycle will be.
1049    if (fault == NoFault) {
1050        DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n",tid, next_PC);
1051
1052        PC[tid] = next_PC;
1053        nextPC[tid] = next_PC + instSize;
1054    } else {
1055        // We shouldn't be in an icache miss and also have a fault (an ITB
1056        // miss)
1057        if (fetchStatus[tid] == IcacheWaitResponse) {
1058            panic("Fetch should have exited prior to this!");
1059        }
1060
1061        // Send the fault to commit.  This thread will not do anything
1062        // until commit handles the fault.  The only other way it can
1063        // wake up is if a squash comes along and changes the PC.
1064#if FULL_SYSTEM
1065        assert(numInst != fetchWidth);
1066        // Get a sequence number.
1067        inst_seq = cpu->getAndIncrementInstSeq();
1068        // We will use a nop in order to carry the fault.
1069        ext_inst = TheISA::NoopMachInst;
1070
1071        // Create a new DynInst from the dummy nop.
1072        DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
1073                                             next_PC,
1074                                             inst_seq, cpu);
1075        instruction->setPredTarg(next_PC + instSize);
1076        instruction->setTid(tid);
1077
1078        instruction->setASID(tid);
1079
1080        instruction->setThreadState(cpu->thread[tid]);
1081
1082        instruction->traceData = NULL;
1083
1084        instruction->setInstListIt(cpu->addInst(instruction));
1085
1086        instruction->fault = fault;
1087
1088        toDecode->insts[numInst] = instruction;
1089        toDecode->size++;
1090
1091        DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid);
1092
1093        fetchStatus[tid] = TrapPending;
1094        status_change = true;
1095
1096        warn("%lli fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
1097#else // !FULL_SYSTEM
1098        warn("%lli fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
1099#endif // FULL_SYSTEM
1100    }
1101}
1102
1103template<class Impl>
1104void
1105DefaultFetch<Impl>::recvRetry()
1106{
1107    assert(cacheBlocked);
1108    if (retryPkt != NULL) {
1109        assert(retryTid != -1);
1110        assert(fetchStatus[retryTid] == IcacheWaitRetry);
1111
1112        if (icachePort->sendTiming(retryPkt)) {
1113            fetchStatus[retryTid] = IcacheWaitResponse;
1114            retryPkt = NULL;
1115            retryTid = -1;
1116            cacheBlocked = false;
1117        }
1118    } else {
1119        assert(retryTid == -1);
1120        // Access has been squashed since it was sent out.  Just clear
1121        // the cache being blocked.
1122        cacheBlocked = false;
1123    }
1124}
1125
1126///////////////////////////////////////
1127//                                   //
1128//  SMT FETCH POLICY MAINTAINED HERE //
1129//                                   //
1130///////////////////////////////////////
1131template<class Impl>
1132int
1133DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority)
1134{
1135    if (numThreads > 1) {
1136        switch (fetch_priority) {
1137
1138          case SingleThread:
1139            return 0;
1140
1141          case RoundRobin:
1142            return roundRobin();
1143
1144          case IQ:
1145            return iqCount();
1146
1147          case LSQ:
1148            return lsqCount();
1149
1150          case Branch:
1151            return branchCount();
1152
1153          default:
1154            return -1;
1155        }
1156    } else {
1157        int tid = *((*activeThreads).begin());
1158
1159        if (fetchStatus[tid] == Running ||
1160            fetchStatus[tid] == IcacheAccessComplete ||
1161            fetchStatus[tid] == Idle) {
1162            return tid;
1163        } else {
1164            return -1;
1165        }
1166    }
1167
1168}
1169
1170
1171template<class Impl>
1172int
1173DefaultFetch<Impl>::roundRobin()
1174{
1175    list<unsigned>::iterator pri_iter = priorityList.begin();
1176    list<unsigned>::iterator end      = priorityList.end();
1177
1178    int high_pri;
1179
1180    while (pri_iter != end) {
1181        high_pri = *pri_iter;
1182
1183        assert(high_pri <= numThreads);
1184
1185        if (fetchStatus[high_pri] == Running ||
1186            fetchStatus[high_pri] == IcacheAccessComplete ||
1187            fetchStatus[high_pri] == Idle) {
1188
1189            priorityList.erase(pri_iter);
1190            priorityList.push_back(high_pri);
1191
1192            return high_pri;
1193        }
1194
1195        pri_iter++;
1196    }
1197
1198    return -1;
1199}
1200
1201template<class Impl>
1202int
1203DefaultFetch<Impl>::iqCount()
1204{
1205    priority_queue<unsigned> PQ;
1206
1207    list<unsigned>::iterator threads = (*activeThreads).begin();
1208
1209    while (threads != (*activeThreads).end()) {
1210        unsigned tid = *threads++;
1211
1212        PQ.push(fromIEW->iewInfo[tid].iqCount);
1213    }
1214
1215    while (!PQ.empty()) {
1216
1217        unsigned high_pri = PQ.top();
1218
1219        if (fetchStatus[high_pri] == Running ||
1220            fetchStatus[high_pri] == IcacheAccessComplete ||
1221            fetchStatus[high_pri] == Idle)
1222            return high_pri;
1223        else
1224            PQ.pop();
1225
1226    }
1227
1228    return -1;
1229}
1230
1231template<class Impl>
1232int
1233DefaultFetch<Impl>::lsqCount()
1234{
1235    priority_queue<unsigned> PQ;
1236
1237
1238    list<unsigned>::iterator threads = (*activeThreads).begin();
1239
1240    while (threads != (*activeThreads).end()) {
1241        unsigned tid = *threads++;
1242
1243        PQ.push(fromIEW->iewInfo[tid].ldstqCount);
1244    }
1245
1246    while (!PQ.empty()) {
1247
1248        unsigned high_pri = PQ.top();
1249
1250        if (fetchStatus[high_pri] == Running ||
1251            fetchStatus[high_pri] == IcacheAccessComplete ||
1252            fetchStatus[high_pri] == Idle)
1253            return high_pri;
1254        else
1255            PQ.pop();
1256
1257    }
1258
1259    return -1;
1260}
1261
1262template<class Impl>
1263int
1264DefaultFetch<Impl>::branchCount()
1265{
1266    list<unsigned>::iterator threads = (*activeThreads).begin();
1267
1268    return *threads;
1269}
1270