fetch_impl.hh revision 13831:4fba790d88be
1/* 2 * Copyright (c) 2010-2014 ARM Limited 3 * Copyright (c) 2012-2013 AMD 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2004-2006 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 * Korey Sewell 43 */ 44 45#ifndef __CPU_O3_FETCH_IMPL_HH__ 46#define __CPU_O3_FETCH_IMPL_HH__ 47 48#include <algorithm> 49#include <cstring> 50#include <list> 51#include <map> 52#include <queue> 53 54#include "arch/generic/tlb.hh" 55#include "arch/isa_traits.hh" 56#include "arch/utility.hh" 57#include "arch/vtophys.hh" 58#include "base/random.hh" 59#include "base/types.hh" 60#include "config/the_isa.hh" 61#include "cpu/base.hh" 62//#include "cpu/checker/cpu.hh" 63#include "cpu/o3/fetch.hh" 64#include "cpu/exetrace.hh" 65#include "debug/Activity.hh" 66#include "debug/Drain.hh" 67#include "debug/Fetch.hh" 68#include "debug/O3PipeView.hh" 69#include "mem/packet.hh" 70#include "params/DerivO3CPU.hh" 71#include "sim/byteswap.hh" 72#include "sim/core.hh" 73#include "sim/eventq.hh" 74#include "sim/full_system.hh" 75#include "sim/system.hh" 76#include "cpu/o3/isa_specific.hh" 77 78using namespace std; 79 80template<class Impl> 81DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params) 82 : fetchPolicy(params->smtFetchPolicy), 83 cpu(_cpu), 84 branchPred(nullptr), 85 decodeToFetchDelay(params->decodeToFetchDelay), 86 renameToFetchDelay(params->renameToFetchDelay), 87 iewToFetchDelay(params->iewToFetchDelay), 88 commitToFetchDelay(params->commitToFetchDelay), 89 fetchWidth(params->fetchWidth), 90 decodeWidth(params->decodeWidth), 91 retryPkt(NULL), 92 retryTid(InvalidThreadID), 93 cacheBlkSize(cpu->cacheLineSize()), 94 fetchBufferSize(params->fetchBufferSize), 95 fetchBufferMask(fetchBufferSize - 1), 96 fetchQueueSize(params->fetchQueueSize), 97 numThreads(params->numThreads), 98 numFetchingThreads(params->smtNumFetchingThreads), 99 finishTranslationEvent(this) 100{ 101 if (numThreads > Impl::MaxThreads) 102 fatal("numThreads (%d) is larger than compiled limit (%d),\n" 103 "\tincrease MaxThreads in src/cpu/o3/impl.hh\n", 104 numThreads, static_cast<int>(Impl::MaxThreads)); 105 if (fetchWidth > Impl::MaxWidth) 106 fatal("fetchWidth (%d) is larger than compiled limit (%d),\n" 107 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 108 fetchWidth, static_cast<int>(Impl::MaxWidth)); 109 if (fetchBufferSize > cacheBlkSize) 110 fatal("fetch buffer size (%u bytes) is greater than the cache " 111 "block size (%u bytes)\n", fetchBufferSize, cacheBlkSize); 112 if (cacheBlkSize % fetchBufferSize) 113 fatal("cache block (%u bytes) is not a multiple of the " 114 "fetch buffer (%u bytes)\n", cacheBlkSize, fetchBufferSize); 115 116 // Figure out fetch policy 117 panic_if(fetchPolicy == FetchPolicy::SingleThread && numThreads > 1, 118 "Invalid Fetch Policy for a SMT workload."); 119 120 // Get the size of an instruction. 121 instSize = sizeof(TheISA::MachInst); 122 123 for (int i = 0; i < Impl::MaxThreads; i++) { 124 fetchStatus[i] = Idle; 125 decoder[i] = nullptr; 126 pc[i] = 0; 127 fetchOffset[i] = 0; 128 macroop[i] = nullptr; 129 delayedCommit[i] = false; 130 memReq[i] = nullptr; 131 stalls[i] = {false, false}; 132 fetchBuffer[i] = NULL; 133 fetchBufferPC[i] = 0; 134 fetchBufferValid[i] = false; 135 lastIcacheStall[i] = 0; 136 issuePipelinedIfetch[i] = false; 137 } 138 139 branchPred = params->branchPred; 140 141 for (ThreadID tid = 0; tid < numThreads; tid++) { 142 decoder[tid] = new TheISA::Decoder(params->isa[tid]); 143 // Create space to buffer the cache line data, 144 // which may not hold the entire cache line. 145 fetchBuffer[tid] = new uint8_t[fetchBufferSize]; 146 } 147} 148 149template <class Impl> 150std::string 151DefaultFetch<Impl>::name() const 152{ 153 return cpu->name() + ".fetch"; 154} 155 156template <class Impl> 157void 158DefaultFetch<Impl>::regProbePoints() 159{ 160 ppFetch = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Fetch"); 161 ppFetchRequestSent = new ProbePointArg<RequestPtr>(cpu->getProbeManager(), 162 "FetchRequest"); 163 164} 165 166template <class Impl> 167void 168DefaultFetch<Impl>::regStats() 169{ 170 icacheStallCycles 171 .name(name() + ".icacheStallCycles") 172 .desc("Number of cycles fetch is stalled on an Icache miss") 173 .prereq(icacheStallCycles); 174 175 fetchedInsts 176 .name(name() + ".Insts") 177 .desc("Number of instructions fetch has processed") 178 .prereq(fetchedInsts); 179 180 fetchedBranches 181 .name(name() + ".Branches") 182 .desc("Number of branches that fetch encountered") 183 .prereq(fetchedBranches); 184 185 predictedBranches 186 .name(name() + ".predictedBranches") 187 .desc("Number of branches that fetch has predicted taken") 188 .prereq(predictedBranches); 189 190 fetchCycles 191 .name(name() + ".Cycles") 192 .desc("Number of cycles fetch has run and was not squashing or" 193 " blocked") 194 .prereq(fetchCycles); 195 196 fetchSquashCycles 197 .name(name() + ".SquashCycles") 198 .desc("Number of cycles fetch has spent squashing") 199 .prereq(fetchSquashCycles); 200 201 fetchTlbCycles 202 .name(name() + ".TlbCycles") 203 .desc("Number of cycles fetch has spent waiting for tlb") 204 .prereq(fetchTlbCycles); 205 206 fetchIdleCycles 207 .name(name() + ".IdleCycles") 208 .desc("Number of cycles fetch was idle") 209 .prereq(fetchIdleCycles); 210 211 fetchBlockedCycles 212 .name(name() + ".BlockedCycles") 213 .desc("Number of cycles fetch has spent blocked") 214 .prereq(fetchBlockedCycles); 215 216 fetchedCacheLines 217 .name(name() + ".CacheLines") 218 .desc("Number of cache lines fetched") 219 .prereq(fetchedCacheLines); 220 221 fetchMiscStallCycles 222 .name(name() + ".MiscStallCycles") 223 .desc("Number of cycles fetch has spent waiting on interrupts, or " 224 "bad addresses, or out of MSHRs") 225 .prereq(fetchMiscStallCycles); 226 227 fetchPendingDrainCycles 228 .name(name() + ".PendingDrainCycles") 229 .desc("Number of cycles fetch has spent waiting on pipes to drain") 230 .prereq(fetchPendingDrainCycles); 231 232 fetchNoActiveThreadStallCycles 233 .name(name() + ".NoActiveThreadStallCycles") 234 .desc("Number of stall cycles due to no active thread to fetch from") 235 .prereq(fetchNoActiveThreadStallCycles); 236 237 fetchPendingTrapStallCycles 238 .name(name() + ".PendingTrapStallCycles") 239 .desc("Number of stall cycles due to pending traps") 240 .prereq(fetchPendingTrapStallCycles); 241 242 fetchPendingQuiesceStallCycles 243 .name(name() + ".PendingQuiesceStallCycles") 244 .desc("Number of stall cycles due to pending quiesce instructions") 245 .prereq(fetchPendingQuiesceStallCycles); 246 247 fetchIcacheWaitRetryStallCycles 248 .name(name() + ".IcacheWaitRetryStallCycles") 249 .desc("Number of stall cycles due to full MSHR") 250 .prereq(fetchIcacheWaitRetryStallCycles); 251 252 fetchIcacheSquashes 253 .name(name() + ".IcacheSquashes") 254 .desc("Number of outstanding Icache misses that were squashed") 255 .prereq(fetchIcacheSquashes); 256 257 fetchTlbSquashes 258 .name(name() + ".ItlbSquashes") 259 .desc("Number of outstanding ITLB misses that were squashed") 260 .prereq(fetchTlbSquashes); 261 262 fetchNisnDist 263 .init(/* base value */ 0, 264 /* last value */ fetchWidth, 265 /* bucket size */ 1) 266 .name(name() + ".rateDist") 267 .desc("Number of instructions fetched each cycle (Total)") 268 .flags(Stats::pdf); 269 270 idleRate 271 .name(name() + ".idleRate") 272 .desc("Percent of cycles fetch was idle") 273 .prereq(idleRate); 274 idleRate = fetchIdleCycles * 100 / cpu->numCycles; 275 276 branchRate 277 .name(name() + ".branchRate") 278 .desc("Number of branch fetches per cycle") 279 .flags(Stats::total); 280 branchRate = fetchedBranches / cpu->numCycles; 281 282 fetchRate 283 .name(name() + ".rate") 284 .desc("Number of inst fetches per cycle") 285 .flags(Stats::total); 286 fetchRate = fetchedInsts / cpu->numCycles; 287} 288 289template<class Impl> 290void 291DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer) 292{ 293 timeBuffer = time_buffer; 294 295 // Create wires to get information from proper places in time buffer. 296 fromDecode = timeBuffer->getWire(-decodeToFetchDelay); 297 fromRename = timeBuffer->getWire(-renameToFetchDelay); 298 fromIEW = timeBuffer->getWire(-iewToFetchDelay); 299 fromCommit = timeBuffer->getWire(-commitToFetchDelay); 300} 301 302template<class Impl> 303void 304DefaultFetch<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr) 305{ 306 activeThreads = at_ptr; 307} 308 309template<class Impl> 310void 311DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *ftb_ptr) 312{ 313 // Create wire to write information to proper place in fetch time buf. 314 toDecode = ftb_ptr->getWire(0); 315} 316 317template<class Impl> 318void 319DefaultFetch<Impl>::startupStage() 320{ 321 assert(priorityList.empty()); 322 resetStage(); 323 324 // Fetch needs to start fetching instructions at the very beginning, 325 // so it must start up in active state. 326 switchToActive(); 327} 328 329template<class Impl> 330void 331DefaultFetch<Impl>::clearStates(ThreadID tid) 332{ 333 fetchStatus[tid] = Running; 334 pc[tid] = cpu->pcState(tid); 335 fetchOffset[tid] = 0; 336 macroop[tid] = NULL; 337 delayedCommit[tid] = false; 338 memReq[tid] = NULL; 339 stalls[tid].decode = false; 340 stalls[tid].drain = false; 341 fetchBufferPC[tid] = 0; 342 fetchBufferValid[tid] = false; 343 fetchQueue[tid].clear(); 344 345 // TODO not sure what to do with priorityList for now 346 // priorityList.push_back(tid); 347} 348 349template<class Impl> 350void 351DefaultFetch<Impl>::resetStage() 352{ 353 numInst = 0; 354 interruptPending = false; 355 cacheBlocked = false; 356 357 priorityList.clear(); 358 359 // Setup PC and nextPC with initial state. 360 for (ThreadID tid = 0; tid < numThreads; ++tid) { 361 fetchStatus[tid] = Running; 362 pc[tid] = cpu->pcState(tid); 363 fetchOffset[tid] = 0; 364 macroop[tid] = NULL; 365 366 delayedCommit[tid] = false; 367 memReq[tid] = NULL; 368 369 stalls[tid].decode = false; 370 stalls[tid].drain = false; 371 372 fetchBufferPC[tid] = 0; 373 fetchBufferValid[tid] = false; 374 375 fetchQueue[tid].clear(); 376 377 priorityList.push_back(tid); 378 } 379 380 wroteToTimeBuffer = false; 381 _status = Inactive; 382} 383 384template<class Impl> 385void 386DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt) 387{ 388 ThreadID tid = cpu->contextToThread(pkt->req->contextId()); 389 390 DPRINTF(Fetch, "[tid:%i] Waking up from cache miss.\n", tid); 391 assert(!cpu->switchedOut()); 392 393 // Only change the status if it's still waiting on the icache access 394 // to return. 395 if (fetchStatus[tid] != IcacheWaitResponse || 396 pkt->req != memReq[tid]) { 397 ++fetchIcacheSquashes; 398 delete pkt; 399 return; 400 } 401 402 memcpy(fetchBuffer[tid], pkt->getConstPtr<uint8_t>(), fetchBufferSize); 403 fetchBufferValid[tid] = true; 404 405 // Wake up the CPU (if it went to sleep and was waiting on 406 // this completion event). 407 cpu->wakeCPU(); 408 409 DPRINTF(Activity, "[tid:%i] Activating fetch due to cache completion\n", 410 tid); 411 412 switchToActive(); 413 414 // Only switch to IcacheAccessComplete if we're not stalled as well. 415 if (checkStall(tid)) { 416 fetchStatus[tid] = Blocked; 417 } else { 418 fetchStatus[tid] = IcacheAccessComplete; 419 } 420 421 pkt->req->setAccessLatency(); 422 cpu->ppInstAccessComplete->notify(pkt); 423 // Reset the mem req to NULL. 424 delete pkt; 425 memReq[tid] = NULL; 426} 427 428template <class Impl> 429void 430DefaultFetch<Impl>::drainResume() 431{ 432 for (ThreadID i = 0; i < numThreads; ++i) { 433 stalls[i].decode = false; 434 stalls[i].drain = false; 435 } 436} 437 438template <class Impl> 439void 440DefaultFetch<Impl>::drainSanityCheck() const 441{ 442 assert(isDrained()); 443 assert(retryPkt == NULL); 444 assert(retryTid == InvalidThreadID); 445 assert(!cacheBlocked); 446 assert(!interruptPending); 447 448 for (ThreadID i = 0; i < numThreads; ++i) { 449 assert(!memReq[i]); 450 assert(fetchStatus[i] == Idle || stalls[i].drain); 451 } 452 453 branchPred->drainSanityCheck(); 454} 455 456template <class Impl> 457bool 458DefaultFetch<Impl>::isDrained() const 459{ 460 /* Make sure that threads are either idle of that the commit stage 461 * has signaled that draining has completed by setting the drain 462 * stall flag. This effectively forces the pipeline to be disabled 463 * until the whole system is drained (simulation may continue to 464 * drain other components). 465 */ 466 for (ThreadID i = 0; i < numThreads; ++i) { 467 // Verify fetch queues are drained 468 if (!fetchQueue[i].empty()) 469 return false; 470 471 // Return false if not idle or drain stalled 472 if (fetchStatus[i] != Idle) { 473 if (fetchStatus[i] == Blocked && stalls[i].drain) 474 continue; 475 else 476 return false; 477 } 478 } 479 480 /* The pipeline might start up again in the middle of the drain 481 * cycle if the finish translation event is scheduled, so make 482 * sure that's not the case. 483 */ 484 return !finishTranslationEvent.scheduled(); 485} 486 487template <class Impl> 488void 489DefaultFetch<Impl>::takeOverFrom() 490{ 491 assert(cpu->getInstPort().isConnected()); 492 resetStage(); 493 494} 495 496template <class Impl> 497void 498DefaultFetch<Impl>::drainStall(ThreadID tid) 499{ 500 assert(cpu->isDraining()); 501 assert(!stalls[tid].drain); 502 DPRINTF(Drain, "%i: Thread drained.\n", tid); 503 stalls[tid].drain = true; 504} 505 506template <class Impl> 507void 508DefaultFetch<Impl>::wakeFromQuiesce() 509{ 510 DPRINTF(Fetch, "Waking up from quiesce\n"); 511 // Hopefully this is safe 512 // @todo: Allow other threads to wake from quiesce. 513 fetchStatus[0] = Running; 514} 515 516template <class Impl> 517inline void 518DefaultFetch<Impl>::switchToActive() 519{ 520 if (_status == Inactive) { 521 DPRINTF(Activity, "Activating stage.\n"); 522 523 cpu->activateStage(O3CPU::FetchIdx); 524 525 _status = Active; 526 } 527} 528 529template <class Impl> 530inline void 531DefaultFetch<Impl>::switchToInactive() 532{ 533 if (_status == Active) { 534 DPRINTF(Activity, "Deactivating stage.\n"); 535 536 cpu->deactivateStage(O3CPU::FetchIdx); 537 538 _status = Inactive; 539 } 540} 541 542template <class Impl> 543void 544DefaultFetch<Impl>::deactivateThread(ThreadID tid) 545{ 546 // Update priority list 547 auto thread_it = std::find(priorityList.begin(), priorityList.end(), tid); 548 if (thread_it != priorityList.end()) { 549 priorityList.erase(thread_it); 550 } 551} 552 553template <class Impl> 554bool 555DefaultFetch<Impl>::lookupAndUpdateNextPC( 556 const DynInstPtr &inst, TheISA::PCState &nextPC) 557{ 558 // Do branch prediction check here. 559 // A bit of a misnomer...next_PC is actually the current PC until 560 // this function updates it. 561 bool predict_taken; 562 563 if (!inst->isControl()) { 564 TheISA::advancePC(nextPC, inst->staticInst); 565 inst->setPredTarg(nextPC); 566 inst->setPredTaken(false); 567 return false; 568 } 569 570 ThreadID tid = inst->threadNumber; 571 predict_taken = branchPred->predict(inst->staticInst, inst->seqNum, 572 nextPC, tid); 573 574 if (predict_taken) { 575 DPRINTF(Fetch, "[tid:%i] [sn:%llu] Branch at PC %#x " 576 "predicted to be taken to %s\n", 577 tid, inst->seqNum, inst->pcState().instAddr(), nextPC); 578 } else { 579 DPRINTF(Fetch, "[tid:%i] [sn:%llu] Branch at PC %#x " 580 "predicted to be not taken\n", 581 tid, inst->seqNum, inst->pcState().instAddr()); 582 } 583 584 DPRINTF(Fetch, "[tid:%i] [sn:%llu] Branch at PC %#x " 585 "predicted to go to %s\n", 586 tid, inst->seqNum, inst->pcState().instAddr(), nextPC); 587 inst->setPredTarg(nextPC); 588 inst->setPredTaken(predict_taken); 589 590 ++fetchedBranches; 591 592 if (predict_taken) { 593 ++predictedBranches; 594 } 595 596 return predict_taken; 597} 598 599template <class Impl> 600bool 601DefaultFetch<Impl>::fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc) 602{ 603 Fault fault = NoFault; 604 605 assert(!cpu->switchedOut()); 606 607 // @todo: not sure if these should block translation. 608 //AlphaDep 609 if (cacheBlocked) { 610 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n", 611 tid); 612 return false; 613 } else if (checkInterrupt(pc) && !delayedCommit[tid]) { 614 // Hold off fetch from getting new instructions when: 615 // Cache is blocked, or 616 // while an interrupt is pending and we're not in PAL mode, or 617 // fetch is switched out. 618 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n", 619 tid); 620 return false; 621 } 622 623 // Align the fetch address to the start of a fetch buffer segment. 624 Addr fetchBufferBlockPC = fetchBufferAlignPC(vaddr); 625 626 DPRINTF(Fetch, "[tid:%i] Fetching cache line %#x for addr %#x\n", 627 tid, fetchBufferBlockPC, vaddr); 628 629 // Setup the memReq to do a read of the first instruction's address. 630 // Set the appropriate read size and flags as well. 631 // Build request here. 632 RequestPtr mem_req = std::make_shared<Request>( 633 tid, fetchBufferBlockPC, fetchBufferSize, 634 Request::INST_FETCH, cpu->instMasterId(), pc, 635 cpu->thread[tid]->contextId()); 636 637 mem_req->taskId(cpu->taskId()); 638 639 memReq[tid] = mem_req; 640 641 // Initiate translation of the icache block 642 fetchStatus[tid] = ItlbWait; 643 FetchTranslation *trans = new FetchTranslation(this); 644 cpu->itb->translateTiming(mem_req, cpu->thread[tid]->getTC(), 645 trans, BaseTLB::Execute); 646 return true; 647} 648 649template <class Impl> 650void 651DefaultFetch<Impl>::finishTranslation(const Fault &fault, 652 const RequestPtr &mem_req) 653{ 654 ThreadID tid = cpu->contextToThread(mem_req->contextId()); 655 Addr fetchBufferBlockPC = mem_req->getVaddr(); 656 657 assert(!cpu->switchedOut()); 658 659 // Wake up CPU if it was idle 660 cpu->wakeCPU(); 661 662 if (fetchStatus[tid] != ItlbWait || mem_req != memReq[tid] || 663 mem_req->getVaddr() != memReq[tid]->getVaddr()) { 664 DPRINTF(Fetch, "[tid:%i] Ignoring itlb completed after squash\n", 665 tid); 666 ++fetchTlbSquashes; 667 return; 668 } 669 670 671 // If translation was successful, attempt to read the icache block. 672 if (fault == NoFault) { 673 // Check that we're not going off into random memory 674 // If we have, just wait around for commit to squash something and put 675 // us on the right track 676 if (!cpu->system->isMemAddr(mem_req->getPaddr())) { 677 warn("Address %#x is outside of physical memory, stopping fetch\n", 678 mem_req->getPaddr()); 679 fetchStatus[tid] = NoGoodAddr; 680 memReq[tid] = NULL; 681 return; 682 } 683 684 // Build packet here. 685 PacketPtr data_pkt = new Packet(mem_req, MemCmd::ReadReq); 686 data_pkt->dataDynamic(new uint8_t[fetchBufferSize]); 687 688 fetchBufferPC[tid] = fetchBufferBlockPC; 689 fetchBufferValid[tid] = false; 690 DPRINTF(Fetch, "Fetch: Doing instruction read.\n"); 691 692 fetchedCacheLines++; 693 694 // Access the cache. 695 if (!cpu->getInstPort().sendTimingReq(data_pkt)) { 696 assert(retryPkt == NULL); 697 assert(retryTid == InvalidThreadID); 698 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid); 699 700 fetchStatus[tid] = IcacheWaitRetry; 701 retryPkt = data_pkt; 702 retryTid = tid; 703 cacheBlocked = true; 704 } else { 705 DPRINTF(Fetch, "[tid:%i] Doing Icache access.\n", tid); 706 DPRINTF(Activity, "[tid:%i] Activity: Waiting on I-cache " 707 "response.\n", tid); 708 lastIcacheStall[tid] = curTick(); 709 fetchStatus[tid] = IcacheWaitResponse; 710 // Notify Fetch Request probe when a packet containing a fetch 711 // request is successfully sent 712 ppFetchRequestSent->notify(mem_req); 713 } 714 } else { 715 // Don't send an instruction to decode if we can't handle it. 716 if (!(numInst < fetchWidth) || !(fetchQueue[tid].size() < fetchQueueSize)) { 717 assert(!finishTranslationEvent.scheduled()); 718 finishTranslationEvent.setFault(fault); 719 finishTranslationEvent.setReq(mem_req); 720 cpu->schedule(finishTranslationEvent, 721 cpu->clockEdge(Cycles(1))); 722 return; 723 } 724 DPRINTF(Fetch, "[tid:%i] Got back req with addr %#x but expected %#x\n", 725 tid, mem_req->getVaddr(), memReq[tid]->getVaddr()); 726 // Translation faulted, icache request won't be sent. 727 memReq[tid] = NULL; 728 729 // Send the fault to commit. This thread will not do anything 730 // until commit handles the fault. The only other way it can 731 // wake up is if a squash comes along and changes the PC. 732 TheISA::PCState fetchPC = pc[tid]; 733 734 DPRINTF(Fetch, "[tid:%i] Translation faulted, building noop.\n", tid); 735 // We will use a nop in ordier to carry the fault. 736 DynInstPtr instruction = buildInst(tid, StaticInst::nopStaticInstPtr, 737 NULL, fetchPC, fetchPC, false); 738 instruction->setNotAnInst(); 739 740 instruction->setPredTarg(fetchPC); 741 instruction->fault = fault; 742 wroteToTimeBuffer = true; 743 744 DPRINTF(Activity, "Activity this cycle.\n"); 745 cpu->activityThisCycle(); 746 747 fetchStatus[tid] = TrapPending; 748 749 DPRINTF(Fetch, "[tid:%i] Blocked, need to handle the trap.\n", tid); 750 DPRINTF(Fetch, "[tid:%i] fault (%s) detected @ PC %s.\n", 751 tid, fault->name(), pc[tid]); 752 } 753 _status = updateFetchStatus(); 754} 755 756template <class Impl> 757inline void 758DefaultFetch<Impl>::doSquash(const TheISA::PCState &newPC, 759 const DynInstPtr squashInst, ThreadID tid) 760{ 761 DPRINTF(Fetch, "[tid:%i] Squashing, setting PC to: %s.\n", 762 tid, newPC); 763 764 pc[tid] = newPC; 765 fetchOffset[tid] = 0; 766 if (squashInst && squashInst->pcState().instAddr() == newPC.instAddr()) 767 macroop[tid] = squashInst->macroop; 768 else 769 macroop[tid] = NULL; 770 decoder[tid]->reset(); 771 772 // Clear the icache miss if it's outstanding. 773 if (fetchStatus[tid] == IcacheWaitResponse) { 774 DPRINTF(Fetch, "[tid:%i] Squashing outstanding Icache miss.\n", 775 tid); 776 memReq[tid] = NULL; 777 } else if (fetchStatus[tid] == ItlbWait) { 778 DPRINTF(Fetch, "[tid:%i] Squashing outstanding ITLB miss.\n", 779 tid); 780 memReq[tid] = NULL; 781 } 782 783 // Get rid of the retrying packet if it was from this thread. 784 if (retryTid == tid) { 785 assert(cacheBlocked); 786 if (retryPkt) { 787 delete retryPkt; 788 } 789 retryPkt = NULL; 790 retryTid = InvalidThreadID; 791 } 792 793 fetchStatus[tid] = Squashing; 794 795 // Empty fetch queue 796 fetchQueue[tid].clear(); 797 798 // microops are being squashed, it is not known wheather the 799 // youngest non-squashed microop was marked delayed commit 800 // or not. Setting the flag to true ensures that the 801 // interrupts are not handled when they cannot be, though 802 // some opportunities to handle interrupts may be missed. 803 delayedCommit[tid] = true; 804 805 ++fetchSquashCycles; 806} 807 808template<class Impl> 809void 810DefaultFetch<Impl>::squashFromDecode(const TheISA::PCState &newPC, 811 const DynInstPtr squashInst, 812 const InstSeqNum seq_num, ThreadID tid) 813{ 814 DPRINTF(Fetch, "[tid:%i] Squashing from decode.\n", tid); 815 816 doSquash(newPC, squashInst, tid); 817 818 // Tell the CPU to remove any instructions that are in flight between 819 // fetch and decode. 820 cpu->removeInstsUntil(seq_num, tid); 821} 822 823template<class Impl> 824bool 825DefaultFetch<Impl>::checkStall(ThreadID tid) const 826{ 827 bool ret_val = false; 828 829 if (stalls[tid].drain) { 830 assert(cpu->isDraining()); 831 DPRINTF(Fetch,"[tid:%i] Drain stall detected.\n",tid); 832 ret_val = true; 833 } 834 835 return ret_val; 836} 837 838template<class Impl> 839typename DefaultFetch<Impl>::FetchStatus 840DefaultFetch<Impl>::updateFetchStatus() 841{ 842 //Check Running 843 list<ThreadID>::iterator threads = activeThreads->begin(); 844 list<ThreadID>::iterator end = activeThreads->end(); 845 846 while (threads != end) { 847 ThreadID tid = *threads++; 848 849 if (fetchStatus[tid] == Running || 850 fetchStatus[tid] == Squashing || 851 fetchStatus[tid] == IcacheAccessComplete) { 852 853 if (_status == Inactive) { 854 DPRINTF(Activity, "[tid:%i] Activating stage.\n",tid); 855 856 if (fetchStatus[tid] == IcacheAccessComplete) { 857 DPRINTF(Activity, "[tid:%i] Activating fetch due to cache" 858 "completion\n",tid); 859 } 860 861 cpu->activateStage(O3CPU::FetchIdx); 862 } 863 864 return Active; 865 } 866 } 867 868 // Stage is switching from active to inactive, notify CPU of it. 869 if (_status == Active) { 870 DPRINTF(Activity, "Deactivating stage.\n"); 871 872 cpu->deactivateStage(O3CPU::FetchIdx); 873 } 874 875 return Inactive; 876} 877 878template <class Impl> 879void 880DefaultFetch<Impl>::squash(const TheISA::PCState &newPC, 881 const InstSeqNum seq_num, DynInstPtr squashInst, 882 ThreadID tid) 883{ 884 DPRINTF(Fetch, "[tid:%i] Squash from commit.\n", tid); 885 886 doSquash(newPC, squashInst, tid); 887 888 // Tell the CPU to remove any instructions that are not in the ROB. 889 cpu->removeInstsNotInROB(tid); 890} 891 892template <class Impl> 893void 894DefaultFetch<Impl>::tick() 895{ 896 list<ThreadID>::iterator threads = activeThreads->begin(); 897 list<ThreadID>::iterator end = activeThreads->end(); 898 bool status_change = false; 899 900 wroteToTimeBuffer = false; 901 902 for (ThreadID i = 0; i < numThreads; ++i) { 903 issuePipelinedIfetch[i] = false; 904 } 905 906 while (threads != end) { 907 ThreadID tid = *threads++; 908 909 // Check the signals for each thread to determine the proper status 910 // for each thread. 911 bool updated_status = checkSignalsAndUpdate(tid); 912 status_change = status_change || updated_status; 913 } 914 915 DPRINTF(Fetch, "Running stage.\n"); 916 917 if (FullSystem) { 918 if (fromCommit->commitInfo[0].interruptPending) { 919 interruptPending = true; 920 } 921 922 if (fromCommit->commitInfo[0].clearInterrupt) { 923 interruptPending = false; 924 } 925 } 926 927 for (threadFetched = 0; threadFetched < numFetchingThreads; 928 threadFetched++) { 929 // Fetch each of the actively fetching threads. 930 fetch(status_change); 931 } 932 933 // Record number of instructions fetched this cycle for distribution. 934 fetchNisnDist.sample(numInst); 935 936 if (status_change) { 937 // Change the fetch stage status if there was a status change. 938 _status = updateFetchStatus(); 939 } 940 941 // Issue the next I-cache request if possible. 942 for (ThreadID i = 0; i < numThreads; ++i) { 943 if (issuePipelinedIfetch[i]) { 944 pipelineIcacheAccesses(i); 945 } 946 } 947 948 // Send instructions enqueued into the fetch queue to decode. 949 // Limit rate by fetchWidth. Stall if decode is stalled. 950 unsigned insts_to_decode = 0; 951 unsigned available_insts = 0; 952 953 for (auto tid : *activeThreads) { 954 if (!stalls[tid].decode) { 955 available_insts += fetchQueue[tid].size(); 956 } 957 } 958 959 // Pick a random thread to start trying to grab instructions from 960 auto tid_itr = activeThreads->begin(); 961 std::advance(tid_itr, random_mt.random<uint8_t>(0, activeThreads->size() - 1)); 962 963 while (available_insts != 0 && insts_to_decode < decodeWidth) { 964 ThreadID tid = *tid_itr; 965 if (!stalls[tid].decode && !fetchQueue[tid].empty()) { 966 const auto& inst = fetchQueue[tid].front(); 967 toDecode->insts[toDecode->size++] = inst; 968 DPRINTF(Fetch, "[tid:%i] [sn:%llu] Sending instruction to decode " 969 "from fetch queue. Fetch queue size: %i.\n", 970 tid, inst->seqNum, fetchQueue[tid].size()); 971 972 wroteToTimeBuffer = true; 973 fetchQueue[tid].pop_front(); 974 insts_to_decode++; 975 available_insts--; 976 } 977 978 tid_itr++; 979 // Wrap around if at end of active threads list 980 if (tid_itr == activeThreads->end()) 981 tid_itr = activeThreads->begin(); 982 } 983 984 // If there was activity this cycle, inform the CPU of it. 985 if (wroteToTimeBuffer) { 986 DPRINTF(Activity, "Activity this cycle.\n"); 987 cpu->activityThisCycle(); 988 } 989 990 // Reset the number of the instruction we've fetched. 991 numInst = 0; 992} 993 994template <class Impl> 995bool 996DefaultFetch<Impl>::checkSignalsAndUpdate(ThreadID tid) 997{ 998 // Update the per thread stall statuses. 999 if (fromDecode->decodeBlock[tid]) { 1000 stalls[tid].decode = true; 1001 } 1002 1003 if (fromDecode->decodeUnblock[tid]) { 1004 assert(stalls[tid].decode); 1005 assert(!fromDecode->decodeBlock[tid]); 1006 stalls[tid].decode = false; 1007 } 1008 1009 // Check squash signals from commit. 1010 if (fromCommit->commitInfo[tid].squash) { 1011 1012 DPRINTF(Fetch, "[tid:%i] Squashing instructions due to squash " 1013 "from commit.\n",tid); 1014 // In any case, squash. 1015 squash(fromCommit->commitInfo[tid].pc, 1016 fromCommit->commitInfo[tid].doneSeqNum, 1017 fromCommit->commitInfo[tid].squashInst, tid); 1018 1019 // If it was a branch mispredict on a control instruction, update the 1020 // branch predictor with that instruction, otherwise just kill the 1021 // invalid state we generated in after sequence number 1022 if (fromCommit->commitInfo[tid].mispredictInst && 1023 fromCommit->commitInfo[tid].mispredictInst->isControl()) { 1024 branchPred->squash(fromCommit->commitInfo[tid].doneSeqNum, 1025 fromCommit->commitInfo[tid].pc, 1026 fromCommit->commitInfo[tid].branchTaken, 1027 tid); 1028 } else { 1029 branchPred->squash(fromCommit->commitInfo[tid].doneSeqNum, 1030 tid); 1031 } 1032 1033 return true; 1034 } else if (fromCommit->commitInfo[tid].doneSeqNum) { 1035 // Update the branch predictor if it wasn't a squashed instruction 1036 // that was broadcasted. 1037 branchPred->update(fromCommit->commitInfo[tid].doneSeqNum, tid); 1038 } 1039 1040 // Check squash signals from decode. 1041 if (fromDecode->decodeInfo[tid].squash) { 1042 DPRINTF(Fetch, "[tid:%i] Squashing instructions due to squash " 1043 "from decode.\n",tid); 1044 1045 // Update the branch predictor. 1046 if (fromDecode->decodeInfo[tid].branchMispredict) { 1047 branchPred->squash(fromDecode->decodeInfo[tid].doneSeqNum, 1048 fromDecode->decodeInfo[tid].nextPC, 1049 fromDecode->decodeInfo[tid].branchTaken, 1050 tid); 1051 } else { 1052 branchPred->squash(fromDecode->decodeInfo[tid].doneSeqNum, 1053 tid); 1054 } 1055 1056 if (fetchStatus[tid] != Squashing) { 1057 1058 DPRINTF(Fetch, "Squashing from decode with PC = %s\n", 1059 fromDecode->decodeInfo[tid].nextPC); 1060 // Squash unless we're already squashing 1061 squashFromDecode(fromDecode->decodeInfo[tid].nextPC, 1062 fromDecode->decodeInfo[tid].squashInst, 1063 fromDecode->decodeInfo[tid].doneSeqNum, 1064 tid); 1065 1066 return true; 1067 } 1068 } 1069 1070 if (checkStall(tid) && 1071 fetchStatus[tid] != IcacheWaitResponse && 1072 fetchStatus[tid] != IcacheWaitRetry && 1073 fetchStatus[tid] != ItlbWait && 1074 fetchStatus[tid] != QuiescePending) { 1075 DPRINTF(Fetch, "[tid:%i] Setting to blocked\n",tid); 1076 1077 fetchStatus[tid] = Blocked; 1078 1079 return true; 1080 } 1081 1082 if (fetchStatus[tid] == Blocked || 1083 fetchStatus[tid] == Squashing) { 1084 // Switch status to running if fetch isn't being told to block or 1085 // squash this cycle. 1086 DPRINTF(Fetch, "[tid:%i] Done squashing, switching to running.\n", 1087 tid); 1088 1089 fetchStatus[tid] = Running; 1090 1091 return true; 1092 } 1093 1094 // If we've reached this point, we have not gotten any signals that 1095 // cause fetch to change its status. Fetch remains the same as before. 1096 return false; 1097} 1098 1099template<class Impl> 1100typename Impl::DynInstPtr 1101DefaultFetch<Impl>::buildInst(ThreadID tid, StaticInstPtr staticInst, 1102 StaticInstPtr curMacroop, TheISA::PCState thisPC, 1103 TheISA::PCState nextPC, bool trace) 1104{ 1105 // Get a sequence number. 1106 InstSeqNum seq = cpu->getAndIncrementInstSeq(); 1107 1108 // Create a new DynInst from the instruction fetched. 1109 DynInstPtr instruction = 1110 new DynInst(staticInst, curMacroop, thisPC, nextPC, seq, cpu); 1111 instruction->setTid(tid); 1112 1113 instruction->setASID(tid); 1114 1115 instruction->setThreadState(cpu->thread[tid]); 1116 1117 DPRINTF(Fetch, "[tid:%i] Instruction PC %#x (%d) created " 1118 "[sn:%lli].\n", tid, thisPC.instAddr(), 1119 thisPC.microPC(), seq); 1120 1121 DPRINTF(Fetch, "[tid:%i] Instruction is: %s\n", tid, 1122 instruction->staticInst-> 1123 disassemble(thisPC.instAddr())); 1124 1125#if TRACING_ON 1126 if (trace) { 1127 instruction->traceData = 1128 cpu->getTracer()->getInstRecord(curTick(), cpu->tcBase(tid), 1129 instruction->staticInst, thisPC, curMacroop); 1130 } 1131#else 1132 instruction->traceData = NULL; 1133#endif 1134 1135 // Add instruction to the CPU's list of instructions. 1136 instruction->setInstListIt(cpu->addInst(instruction)); 1137 1138 // Write the instruction to the first slot in the queue 1139 // that heads to decode. 1140 assert(numInst < fetchWidth); 1141 fetchQueue[tid].push_back(instruction); 1142 assert(fetchQueue[tid].size() <= fetchQueueSize); 1143 DPRINTF(Fetch, "[tid:%i] Fetch queue entry created (%i/%i).\n", 1144 tid, fetchQueue[tid].size(), fetchQueueSize); 1145 //toDecode->insts[toDecode->size++] = instruction; 1146 1147 // Keep track of if we can take an interrupt at this boundary 1148 delayedCommit[tid] = instruction->isDelayedCommit(); 1149 1150 return instruction; 1151} 1152 1153template<class Impl> 1154void 1155DefaultFetch<Impl>::fetch(bool &status_change) 1156{ 1157 ////////////////////////////////////////// 1158 // Start actual fetch 1159 ////////////////////////////////////////// 1160 ThreadID tid = getFetchingThread(); 1161 1162 assert(!cpu->switchedOut()); 1163 1164 if (tid == InvalidThreadID) { 1165 // Breaks looping condition in tick() 1166 threadFetched = numFetchingThreads; 1167 1168 if (numThreads == 1) { // @todo Per-thread stats 1169 profileStall(0); 1170 } 1171 1172 return; 1173 } 1174 1175 DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid); 1176 1177 // The current PC. 1178 TheISA::PCState thisPC = pc[tid]; 1179 1180 Addr pcOffset = fetchOffset[tid]; 1181 Addr fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask; 1182 1183 bool inRom = isRomMicroPC(thisPC.microPC()); 1184 1185 // If returning from the delay of a cache miss, then update the status 1186 // to running, otherwise do the cache access. Possibly move this up 1187 // to tick() function. 1188 if (fetchStatus[tid] == IcacheAccessComplete) { 1189 DPRINTF(Fetch, "[tid:%i] Icache miss is complete.\n", tid); 1190 1191 fetchStatus[tid] = Running; 1192 status_change = true; 1193 } else if (fetchStatus[tid] == Running) { 1194 // Align the fetch PC so its at the start of a fetch buffer segment. 1195 Addr fetchBufferBlockPC = fetchBufferAlignPC(fetchAddr); 1196 1197 // If buffer is no longer valid or fetchAddr has moved to point 1198 // to the next cache block, AND we have no remaining ucode 1199 // from a macro-op, then start fetch from icache. 1200 if (!(fetchBufferValid[tid] && fetchBufferBlockPC == fetchBufferPC[tid]) 1201 && !inRom && !macroop[tid]) { 1202 DPRINTF(Fetch, "[tid:%i] Attempting to translate and read " 1203 "instruction, starting at PC %s.\n", tid, thisPC); 1204 1205 fetchCacheLine(fetchAddr, tid, thisPC.instAddr()); 1206 1207 if (fetchStatus[tid] == IcacheWaitResponse) 1208 ++icacheStallCycles; 1209 else if (fetchStatus[tid] == ItlbWait) 1210 ++fetchTlbCycles; 1211 else 1212 ++fetchMiscStallCycles; 1213 return; 1214 } else if ((checkInterrupt(thisPC.instAddr()) && !delayedCommit[tid])) { 1215 // Stall CPU if an interrupt is posted and we're not issuing 1216 // an delayed commit micro-op currently (delayed commit instructions 1217 // are not interruptable by interrupts, only faults) 1218 ++fetchMiscStallCycles; 1219 DPRINTF(Fetch, "[tid:%i] Fetch is stalled!\n", tid); 1220 return; 1221 } 1222 } else { 1223 if (fetchStatus[tid] == Idle) { 1224 ++fetchIdleCycles; 1225 DPRINTF(Fetch, "[tid:%i] Fetch is idle!\n", tid); 1226 } 1227 1228 // Status is Idle, so fetch should do nothing. 1229 return; 1230 } 1231 1232 ++fetchCycles; 1233 1234 TheISA::PCState nextPC = thisPC; 1235 1236 StaticInstPtr staticInst = NULL; 1237 StaticInstPtr curMacroop = macroop[tid]; 1238 1239 // If the read of the first instruction was successful, then grab the 1240 // instructions from the rest of the cache line and put them into the 1241 // queue heading to decode. 1242 1243 DPRINTF(Fetch, "[tid:%i] Adding instructions to queue to " 1244 "decode.\n", tid); 1245 1246 // Need to keep track of whether or not a predicted branch 1247 // ended this fetch block. 1248 bool predictedBranch = false; 1249 1250 // Need to halt fetch if quiesce instruction detected 1251 bool quiesce = false; 1252 1253 TheISA::MachInst *cacheInsts = 1254 reinterpret_cast<TheISA::MachInst *>(fetchBuffer[tid]); 1255 1256 const unsigned numInsts = fetchBufferSize / instSize; 1257 unsigned blkOffset = (fetchAddr - fetchBufferPC[tid]) / instSize; 1258 1259 // Loop through instruction memory from the cache. 1260 // Keep issuing while fetchWidth is available and branch is not 1261 // predicted taken 1262 while (numInst < fetchWidth && fetchQueue[tid].size() < fetchQueueSize 1263 && !predictedBranch && !quiesce) { 1264 // We need to process more memory if we aren't going to get a 1265 // StaticInst from the rom, the current macroop, or what's already 1266 // in the decoder. 1267 bool needMem = !inRom && !curMacroop && 1268 !decoder[tid]->instReady(); 1269 fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask; 1270 Addr fetchBufferBlockPC = fetchBufferAlignPC(fetchAddr); 1271 1272 if (needMem) { 1273 // If buffer is no longer valid or fetchAddr has moved to point 1274 // to the next cache block then start fetch from icache. 1275 if (!fetchBufferValid[tid] || 1276 fetchBufferBlockPC != fetchBufferPC[tid]) 1277 break; 1278 1279 if (blkOffset >= numInsts) { 1280 // We need to process more memory, but we've run out of the 1281 // current block. 1282 break; 1283 } 1284 1285 MachInst inst = TheISA::gtoh(cacheInsts[blkOffset]); 1286 decoder[tid]->moreBytes(thisPC, fetchAddr, inst); 1287 1288 if (decoder[tid]->needMoreBytes()) { 1289 blkOffset++; 1290 fetchAddr += instSize; 1291 pcOffset += instSize; 1292 } 1293 } 1294 1295 // Extract as many instructions and/or microops as we can from 1296 // the memory we've processed so far. 1297 do { 1298 if (!(curMacroop || inRom)) { 1299 if (decoder[tid]->instReady()) { 1300 staticInst = decoder[tid]->decode(thisPC); 1301 1302 // Increment stat of fetched instructions. 1303 ++fetchedInsts; 1304 1305 if (staticInst->isMacroop()) { 1306 curMacroop = staticInst; 1307 } else { 1308 pcOffset = 0; 1309 } 1310 } else { 1311 // We need more bytes for this instruction so blkOffset and 1312 // pcOffset will be updated 1313 break; 1314 } 1315 } 1316 // Whether we're moving to a new macroop because we're at the 1317 // end of the current one, or the branch predictor incorrectly 1318 // thinks we are... 1319 bool newMacro = false; 1320 if (curMacroop || inRom) { 1321 if (inRom) { 1322 staticInst = cpu->microcodeRom.fetchMicroop( 1323 thisPC.microPC(), curMacroop); 1324 } else { 1325 staticInst = curMacroop->fetchMicroop(thisPC.microPC()); 1326 } 1327 newMacro |= staticInst->isLastMicroop(); 1328 } 1329 1330 DynInstPtr instruction = 1331 buildInst(tid, staticInst, curMacroop, 1332 thisPC, nextPC, true); 1333 1334 ppFetch->notify(instruction); 1335 numInst++; 1336 1337#if TRACING_ON 1338 if (DTRACE(O3PipeView)) { 1339 instruction->fetchTick = curTick(); 1340 } 1341#endif 1342 1343 nextPC = thisPC; 1344 1345 // If we're branching after this instruction, quit fetching 1346 // from the same block. 1347 predictedBranch |= thisPC.branching(); 1348 predictedBranch |= 1349 lookupAndUpdateNextPC(instruction, nextPC); 1350 if (predictedBranch) { 1351 DPRINTF(Fetch, "Branch detected with PC = %s\n", thisPC); 1352 } 1353 1354 newMacro |= thisPC.instAddr() != nextPC.instAddr(); 1355 1356 // Move to the next instruction, unless we have a branch. 1357 thisPC = nextPC; 1358 inRom = isRomMicroPC(thisPC.microPC()); 1359 1360 if (newMacro) { 1361 fetchAddr = thisPC.instAddr() & BaseCPU::PCMask; 1362 blkOffset = (fetchAddr - fetchBufferPC[tid]) / instSize; 1363 pcOffset = 0; 1364 curMacroop = NULL; 1365 } 1366 1367 if (instruction->isQuiesce()) { 1368 DPRINTF(Fetch, 1369 "Quiesce instruction encountered, halting fetch!\n"); 1370 fetchStatus[tid] = QuiescePending; 1371 status_change = true; 1372 quiesce = true; 1373 break; 1374 } 1375 } while ((curMacroop || decoder[tid]->instReady()) && 1376 numInst < fetchWidth && 1377 fetchQueue[tid].size() < fetchQueueSize); 1378 1379 // Re-evaluate whether the next instruction to fetch is in micro-op ROM 1380 // or not. 1381 inRom = isRomMicroPC(thisPC.microPC()); 1382 } 1383 1384 if (predictedBranch) { 1385 DPRINTF(Fetch, "[tid:%i] Done fetching, predicted branch " 1386 "instruction encountered.\n", tid); 1387 } else if (numInst >= fetchWidth) { 1388 DPRINTF(Fetch, "[tid:%i] Done fetching, reached fetch bandwidth " 1389 "for this cycle.\n", tid); 1390 } else if (blkOffset >= fetchBufferSize) { 1391 DPRINTF(Fetch, "[tid:%i] Done fetching, reached the end of the" 1392 "fetch buffer.\n", tid); 1393 } 1394 1395 macroop[tid] = curMacroop; 1396 fetchOffset[tid] = pcOffset; 1397 1398 if (numInst > 0) { 1399 wroteToTimeBuffer = true; 1400 } 1401 1402 pc[tid] = thisPC; 1403 1404 // pipeline a fetch if we're crossing a fetch buffer boundary and not in 1405 // a state that would preclude fetching 1406 fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask; 1407 Addr fetchBufferBlockPC = fetchBufferAlignPC(fetchAddr); 1408 issuePipelinedIfetch[tid] = fetchBufferBlockPC != fetchBufferPC[tid] && 1409 fetchStatus[tid] != IcacheWaitResponse && 1410 fetchStatus[tid] != ItlbWait && 1411 fetchStatus[tid] != IcacheWaitRetry && 1412 fetchStatus[tid] != QuiescePending && 1413 !curMacroop; 1414} 1415 1416template<class Impl> 1417void 1418DefaultFetch<Impl>::recvReqRetry() 1419{ 1420 if (retryPkt != NULL) { 1421 assert(cacheBlocked); 1422 assert(retryTid != InvalidThreadID); 1423 assert(fetchStatus[retryTid] == IcacheWaitRetry); 1424 1425 if (cpu->getInstPort().sendTimingReq(retryPkt)) { 1426 fetchStatus[retryTid] = IcacheWaitResponse; 1427 // Notify Fetch Request probe when a retryPkt is successfully sent. 1428 // Note that notify must be called before retryPkt is set to NULL. 1429 ppFetchRequestSent->notify(retryPkt->req); 1430 retryPkt = NULL; 1431 retryTid = InvalidThreadID; 1432 cacheBlocked = false; 1433 } 1434 } else { 1435 assert(retryTid == InvalidThreadID); 1436 // Access has been squashed since it was sent out. Just clear 1437 // the cache being blocked. 1438 cacheBlocked = false; 1439 } 1440} 1441 1442/////////////////////////////////////// 1443// // 1444// SMT FETCH POLICY MAINTAINED HERE // 1445// // 1446/////////////////////////////////////// 1447template<class Impl> 1448ThreadID 1449DefaultFetch<Impl>::getFetchingThread() 1450{ 1451 if (numThreads > 1) { 1452 switch (fetchPolicy) { 1453 case FetchPolicy::RoundRobin: 1454 return roundRobin(); 1455 case FetchPolicy::IQCount: 1456 return iqCount(); 1457 case FetchPolicy::LSQCount: 1458 return lsqCount(); 1459 case FetchPolicy::Branch: 1460 return branchCount(); 1461 default: 1462 return InvalidThreadID; 1463 } 1464 } else { 1465 list<ThreadID>::iterator thread = activeThreads->begin(); 1466 if (thread == activeThreads->end()) { 1467 return InvalidThreadID; 1468 } 1469 1470 ThreadID tid = *thread; 1471 1472 if (fetchStatus[tid] == Running || 1473 fetchStatus[tid] == IcacheAccessComplete || 1474 fetchStatus[tid] == Idle) { 1475 return tid; 1476 } else { 1477 return InvalidThreadID; 1478 } 1479 } 1480} 1481 1482 1483template<class Impl> 1484ThreadID 1485DefaultFetch<Impl>::roundRobin() 1486{ 1487 list<ThreadID>::iterator pri_iter = priorityList.begin(); 1488 list<ThreadID>::iterator end = priorityList.end(); 1489 1490 ThreadID high_pri; 1491 1492 while (pri_iter != end) { 1493 high_pri = *pri_iter; 1494 1495 assert(high_pri <= numThreads); 1496 1497 if (fetchStatus[high_pri] == Running || 1498 fetchStatus[high_pri] == IcacheAccessComplete || 1499 fetchStatus[high_pri] == Idle) { 1500 1501 priorityList.erase(pri_iter); 1502 priorityList.push_back(high_pri); 1503 1504 return high_pri; 1505 } 1506 1507 pri_iter++; 1508 } 1509 1510 return InvalidThreadID; 1511} 1512 1513template<class Impl> 1514ThreadID 1515DefaultFetch<Impl>::iqCount() 1516{ 1517 //sorted from lowest->highest 1518 std::priority_queue<unsigned,vector<unsigned>, 1519 std::greater<unsigned> > PQ; 1520 std::map<unsigned, ThreadID> threadMap; 1521 1522 list<ThreadID>::iterator threads = activeThreads->begin(); 1523 list<ThreadID>::iterator end = activeThreads->end(); 1524 1525 while (threads != end) { 1526 ThreadID tid = *threads++; 1527 unsigned iqCount = fromIEW->iewInfo[tid].iqCount; 1528 1529 //we can potentially get tid collisions if two threads 1530 //have the same iqCount, but this should be rare. 1531 PQ.push(iqCount); 1532 threadMap[iqCount] = tid; 1533 } 1534 1535 while (!PQ.empty()) { 1536 ThreadID high_pri = threadMap[PQ.top()]; 1537 1538 if (fetchStatus[high_pri] == Running || 1539 fetchStatus[high_pri] == IcacheAccessComplete || 1540 fetchStatus[high_pri] == Idle) 1541 return high_pri; 1542 else 1543 PQ.pop(); 1544 1545 } 1546 1547 return InvalidThreadID; 1548} 1549 1550template<class Impl> 1551ThreadID 1552DefaultFetch<Impl>::lsqCount() 1553{ 1554 //sorted from lowest->highest 1555 std::priority_queue<unsigned,vector<unsigned>, 1556 std::greater<unsigned> > PQ; 1557 std::map<unsigned, ThreadID> threadMap; 1558 1559 list<ThreadID>::iterator threads = activeThreads->begin(); 1560 list<ThreadID>::iterator end = activeThreads->end(); 1561 1562 while (threads != end) { 1563 ThreadID tid = *threads++; 1564 unsigned ldstqCount = fromIEW->iewInfo[tid].ldstqCount; 1565 1566 //we can potentially get tid collisions if two threads 1567 //have the same iqCount, but this should be rare. 1568 PQ.push(ldstqCount); 1569 threadMap[ldstqCount] = tid; 1570 } 1571 1572 while (!PQ.empty()) { 1573 ThreadID high_pri = threadMap[PQ.top()]; 1574 1575 if (fetchStatus[high_pri] == Running || 1576 fetchStatus[high_pri] == IcacheAccessComplete || 1577 fetchStatus[high_pri] == Idle) 1578 return high_pri; 1579 else 1580 PQ.pop(); 1581 } 1582 1583 return InvalidThreadID; 1584} 1585 1586template<class Impl> 1587ThreadID 1588DefaultFetch<Impl>::branchCount() 1589{ 1590#if 0 1591 list<ThreadID>::iterator thread = activeThreads->begin(); 1592 assert(thread != activeThreads->end()); 1593 ThreadID tid = *thread; 1594#endif 1595 1596 panic("Branch Count Fetch policy unimplemented\n"); 1597 return InvalidThreadID; 1598} 1599 1600template<class Impl> 1601void 1602DefaultFetch<Impl>::pipelineIcacheAccesses(ThreadID tid) 1603{ 1604 if (!issuePipelinedIfetch[tid]) { 1605 return; 1606 } 1607 1608 // The next PC to access. 1609 TheISA::PCState thisPC = pc[tid]; 1610 1611 if (isRomMicroPC(thisPC.microPC())) { 1612 return; 1613 } 1614 1615 Addr pcOffset = fetchOffset[tid]; 1616 Addr fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask; 1617 1618 // Align the fetch PC so its at the start of a fetch buffer segment. 1619 Addr fetchBufferBlockPC = fetchBufferAlignPC(fetchAddr); 1620 1621 // Unless buffer already got the block, fetch it from icache. 1622 if (!(fetchBufferValid[tid] && fetchBufferBlockPC == fetchBufferPC[tid])) { 1623 DPRINTF(Fetch, "[tid:%i] Issuing a pipelined I-cache access, " 1624 "starting at PC %s.\n", tid, thisPC); 1625 1626 fetchCacheLine(fetchAddr, tid, thisPC.instAddr()); 1627 } 1628} 1629 1630template<class Impl> 1631void 1632DefaultFetch<Impl>::profileStall(ThreadID tid) { 1633 DPRINTF(Fetch,"There are no more threads available to fetch from.\n"); 1634 1635 // @todo Per-thread stats 1636 1637 if (stalls[tid].drain) { 1638 ++fetchPendingDrainCycles; 1639 DPRINTF(Fetch, "Fetch is waiting for a drain!\n"); 1640 } else if (activeThreads->empty()) { 1641 ++fetchNoActiveThreadStallCycles; 1642 DPRINTF(Fetch, "Fetch has no active thread!\n"); 1643 } else if (fetchStatus[tid] == Blocked) { 1644 ++fetchBlockedCycles; 1645 DPRINTF(Fetch, "[tid:%i] Fetch is blocked!\n", tid); 1646 } else if (fetchStatus[tid] == Squashing) { 1647 ++fetchSquashCycles; 1648 DPRINTF(Fetch, "[tid:%i] Fetch is squashing!\n", tid); 1649 } else if (fetchStatus[tid] == IcacheWaitResponse) { 1650 ++icacheStallCycles; 1651 DPRINTF(Fetch, "[tid:%i] Fetch is waiting cache response!\n", 1652 tid); 1653 } else if (fetchStatus[tid] == ItlbWait) { 1654 ++fetchTlbCycles; 1655 DPRINTF(Fetch, "[tid:%i] Fetch is waiting ITLB walk to " 1656 "finish!\n", tid); 1657 } else if (fetchStatus[tid] == TrapPending) { 1658 ++fetchPendingTrapStallCycles; 1659 DPRINTF(Fetch, "[tid:%i] Fetch is waiting for a pending trap!\n", 1660 tid); 1661 } else if (fetchStatus[tid] == QuiescePending) { 1662 ++fetchPendingQuiesceStallCycles; 1663 DPRINTF(Fetch, "[tid:%i] Fetch is waiting for a pending quiesce " 1664 "instruction!\n", tid); 1665 } else if (fetchStatus[tid] == IcacheWaitRetry) { 1666 ++fetchIcacheWaitRetryStallCycles; 1667 DPRINTF(Fetch, "[tid:%i] Fetch is waiting for an I-cache retry!\n", 1668 tid); 1669 } else if (fetchStatus[tid] == NoGoodAddr) { 1670 DPRINTF(Fetch, "[tid:%i] Fetch predicted non-executable address\n", 1671 tid); 1672 } else { 1673 DPRINTF(Fetch, "[tid:%i] Unexpected fetch stall reason " 1674 "(Status: %i)\n", 1675 tid, fetchStatus[tid]); 1676 } 1677} 1678 1679#endif//__CPU_O3_FETCH_IMPL_HH__ 1680