fetch.hh revision 7849:2290428b5f04 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 *          Korey Sewell
42 */
43
44#ifndef __CPU_O3_FETCH_HH__
45#define __CPU_O3_FETCH_HH__
46
47#include "arch/utility.hh"
48#include "arch/predecoder.hh"
49#include "base/statistics.hh"
50#include "cpu/timebuf.hh"
51#include "config/the_isa.hh"
52#include "cpu/pc_event.hh"
53#include "cpu/translation.hh"
54#include "mem/packet.hh"
55#include "mem/port.hh"
56#include "sim/eventq.hh"
57
58class DerivO3CPUParams;
59
60/**
61 * DefaultFetch class handles both single threaded and SMT fetch. Its
62 * width is specified by the parameters; each cycle it tries to fetch
63 * that many instructions. It supports using a branch predictor to
64 * predict direction and targets.
65 * It supports the idling functionality of the CPU by indicating to
66 * the CPU when it is active and inactive.
67 */
68template <class Impl>
69class DefaultFetch
70{
71  public:
72    /** Typedefs from Impl. */
73    typedef typename Impl::CPUPol CPUPol;
74    typedef typename Impl::DynInst DynInst;
75    typedef typename Impl::DynInstPtr DynInstPtr;
76    typedef typename Impl::O3CPU O3CPU;
77
78    /** Typedefs from the CPU policy. */
79    typedef typename CPUPol::BPredUnit BPredUnit;
80    typedef typename CPUPol::FetchStruct FetchStruct;
81    typedef typename CPUPol::TimeStruct TimeStruct;
82
83    /** Typedefs from ISA. */
84    typedef TheISA::MachInst MachInst;
85    typedef TheISA::ExtMachInst ExtMachInst;
86
87    /** IcachePort class for DefaultFetch.  Handles doing the
88     * communication with the cache/memory.
89     */
90    class IcachePort : public Port
91    {
92      protected:
93        /** Pointer to fetch. */
94        DefaultFetch<Impl> *fetch;
95
96      public:
97        /** Default constructor. */
98        IcachePort(DefaultFetch<Impl> *_fetch)
99            : Port(_fetch->name() + "-iport", _fetch->cpu), fetch(_fetch)
100        { }
101
102        bool snoopRangeSent;
103
104        virtual void setPeer(Port *port);
105
106      protected:
107        /** Atomic version of receive.  Panics. */
108        virtual Tick recvAtomic(PacketPtr pkt);
109
110        /** Functional version of receive.  Panics. */
111        virtual void recvFunctional(PacketPtr pkt);
112
113        /** Receives status change.  Other than range changing, panics. */
114        virtual void recvStatusChange(Status status);
115
116        /** Returns the address ranges of this device. */
117        virtual void getDeviceAddressRanges(AddrRangeList &resp,
118                                            bool &snoop)
119        { resp.clear(); snoop = true; }
120
121        /** Timing version of receive.  Handles setting fetch to the
122         * proper status to start fetching. */
123        virtual bool recvTiming(PacketPtr pkt);
124
125        /** Handles doing a retry of a failed fetch. */
126        virtual void recvRetry();
127    };
128
129    class FetchTranslation : public BaseTLB::Translation
130    {
131      protected:
132        DefaultFetch<Impl> *fetch;
133
134      public:
135        FetchTranslation(DefaultFetch<Impl> *_fetch)
136            : fetch(_fetch)
137        {}
138
139        void
140        finish(Fault fault, RequestPtr req, ThreadContext *tc,
141               BaseTLB::Mode mode)
142        {
143            assert(mode == BaseTLB::Execute);
144            fetch->finishTranslation(fault, req);
145            delete this;
146        }
147    };
148
149  public:
150    /** Overall fetch status. Used to determine if the CPU can
151     * deschedule itsef due to a lack of activity.
152     */
153    enum FetchStatus {
154        Active,
155        Inactive
156    };
157
158    /** Individual thread status. */
159    enum ThreadStatus {
160        Running,
161        Idle,
162        Squashing,
163        Blocked,
164        Fetching,
165        TrapPending,
166        QuiescePending,
167        SwitchOut,
168        ItlbWait,
169        IcacheWaitResponse,
170        IcacheWaitRetry,
171        IcacheAccessComplete
172    };
173
174    /** Fetching Policy, Add new policies here.*/
175    enum FetchPriority {
176        SingleThread,
177        RoundRobin,
178        Branch,
179        IQ,
180        LSQ
181    };
182
183  private:
184    /** Fetch status. */
185    FetchStatus _status;
186
187    /** Per-thread status. */
188    ThreadStatus fetchStatus[Impl::MaxThreads];
189
190    /** Fetch policy. */
191    FetchPriority fetchPolicy;
192
193    /** List that has the threads organized by priority. */
194    std::list<ThreadID> priorityList;
195
196  public:
197    /** DefaultFetch constructor. */
198    DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params);
199
200    /** Returns the name of fetch. */
201    std::string name() const;
202
203    /** Registers statistics. */
204    void regStats();
205
206    /** Returns the icache port. */
207    Port *getIcachePort() { return icachePort; }
208
209    /** Sets the main backwards communication time buffer pointer. */
210    void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
211
212    /** Sets pointer to list of active threads. */
213    void setActiveThreads(std::list<ThreadID> *at_ptr);
214
215    /** Sets pointer to time buffer used to communicate to the next stage. */
216    void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
217
218    /** Initialize stage. */
219    void initStage();
220
221    /** Tells the fetch stage that the Icache is set. */
222    void setIcache();
223
224    /** Processes cache completion event. */
225    void processCacheCompletion(PacketPtr pkt);
226
227    /** Begins the drain of the fetch stage. */
228    bool drain();
229
230    /** Resumes execution after a drain. */
231    void resume();
232
233    /** Tells fetch stage to prepare to be switched out. */
234    void switchOut();
235
236    /** Takes over from another CPU's thread. */
237    void takeOverFrom();
238
239    /** Checks if the fetch stage is switched out. */
240    bool isSwitchedOut() { return switchedOut; }
241
242    /** Tells fetch to wake up from a quiesce instruction. */
243    void wakeFromQuiesce();
244
245  private:
246    /** Changes the status of this stage to active, and indicates this
247     * to the CPU.
248     */
249    inline void switchToActive();
250
251    /** Changes the status of this stage to inactive, and indicates
252     * this to the CPU.
253     */
254    inline void switchToInactive();
255
256    /**
257     * Looks up in the branch predictor to see if the next PC should be
258     * either next PC+=MachInst or a branch target.
259     * @param next_PC Next PC variable passed in by reference.  It is
260     * expected to be set to the current PC; it will be updated with what
261     * the next PC will be.
262     * @param next_NPC Used for ISAs which use delay slots.
263     * @return Whether or not a branch was predicted as taken.
264     */
265    bool lookupAndUpdateNextPC(DynInstPtr &inst, TheISA::PCState &pc);
266
267    /**
268     * Fetches the cache line that contains fetch_PC.  Returns any
269     * fault that happened.  Puts the data into the class variable
270     * cacheData.
271     * @param vaddr The memory address that is being fetched from.
272     * @param ret_fault The fault reference that will be set to the result of
273     * the icache access.
274     * @param tid Thread id.
275     * @param pc The actual PC of the current instruction.
276     * @return Any fault that occured.
277     */
278    bool fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc);
279    void finishTranslation(Fault fault, RequestPtr mem_req);
280
281
282    /** Check if an interrupt is pending and that we need to handle
283     */
284    bool
285    checkInterrupt(Addr pc)
286    {
287        return (interruptPending && (THE_ISA != ALPHA_ISA || !(pc & 0x3)));
288    }
289
290    /** Squashes a specific thread and resets the PC. */
291    inline void doSquash(const TheISA::PCState &newPC, ThreadID tid);
292
293    /** Squashes a specific thread and resets the PC. Also tells the CPU to
294     * remove any instructions between fetch and decode that should be sqaushed.
295     */
296    void squashFromDecode(const TheISA::PCState &newPC,
297                          const InstSeqNum &seq_num, ThreadID tid);
298
299    /** Checks if a thread is stalled. */
300    bool checkStall(ThreadID tid) const;
301
302    /** Updates overall fetch stage status; to be called at the end of each
303     * cycle. */
304    FetchStatus updateFetchStatus();
305
306  public:
307    /** Squashes a specific thread and resets the PC. Also tells the CPU to
308     * remove any instructions that are not in the ROB. The source of this
309     * squash should be the commit stage.
310     */
311    void squash(const TheISA::PCState &newPC,
312                const InstSeqNum &seq_num, ThreadID tid);
313
314    /** Ticks the fetch stage, processing all inputs signals and fetching
315     * as many instructions as possible.
316     */
317    void tick();
318
319    /** Checks all input signals and updates the status as necessary.
320     *  @return: Returns if the status has changed due to input signals.
321     */
322    bool checkSignalsAndUpdate(ThreadID tid);
323
324    /** Does the actual fetching of instructions and passing them on to the
325     * next stage.
326     * @param status_change fetch() sets this variable if there was a status
327     * change (ie switching to IcacheMissStall).
328     */
329    void fetch(bool &status_change);
330
331    /** Align a PC to the start of an I-cache block. */
332    Addr icacheBlockAlignPC(Addr addr)
333    {
334        return (addr & ~(cacheBlkMask));
335    }
336
337  private:
338    DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst,
339                         StaticInstPtr curMacroop, TheISA::PCState thisPC,
340                         TheISA::PCState nextPC, bool trace);
341
342    /** Handles retrying the fetch access. */
343    void recvRetry();
344
345    /** Returns the appropriate thread to fetch, given the fetch policy. */
346    ThreadID getFetchingThread(FetchPriority &fetch_priority);
347
348    /** Returns the appropriate thread to fetch using a round robin policy. */
349    ThreadID roundRobin();
350
351    /** Returns the appropriate thread to fetch using the IQ count policy. */
352    ThreadID iqCount();
353
354    /** Returns the appropriate thread to fetch using the LSQ count policy. */
355    ThreadID lsqCount();
356
357    /** Returns the appropriate thread to fetch using the branch count
358     * policy. */
359    ThreadID branchCount();
360
361  private:
362    /** Pointer to the O3CPU. */
363    O3CPU *cpu;
364
365    /** Time buffer interface. */
366    TimeBuffer<TimeStruct> *timeBuffer;
367
368    /** Wire to get decode's information from backwards time buffer. */
369    typename TimeBuffer<TimeStruct>::wire fromDecode;
370
371    /** Wire to get rename's information from backwards time buffer. */
372    typename TimeBuffer<TimeStruct>::wire fromRename;
373
374    /** Wire to get iew's information from backwards time buffer. */
375    typename TimeBuffer<TimeStruct>::wire fromIEW;
376
377    /** Wire to get commit's information from backwards time buffer. */
378    typename TimeBuffer<TimeStruct>::wire fromCommit;
379
380    /** Internal fetch instruction queue. */
381    TimeBuffer<FetchStruct> *fetchQueue;
382
383    //Might be annoying how this name is different than the queue.
384    /** Wire used to write any information heading to decode. */
385    typename TimeBuffer<FetchStruct>::wire toDecode;
386
387    /** Icache interface. */
388    IcachePort *icachePort;
389
390    /** BPredUnit. */
391    BPredUnit branchPred;
392
393    /** Predecoder. */
394    TheISA::Predecoder predecoder;
395
396    TheISA::PCState pc[Impl::MaxThreads];
397
398    Addr fetchOffset[Impl::MaxThreads];
399
400    StaticInstPtr macroop[Impl::MaxThreads];
401
402    /** Memory request used to access cache. */
403    RequestPtr memReq[Impl::MaxThreads];
404
405    /** Variable that tracks if fetch has written to the time buffer this
406     * cycle. Used to tell CPU if there is activity this cycle.
407     */
408    bool wroteToTimeBuffer;
409
410    /** Tracks how many instructions has been fetched this cycle. */
411    int numInst;
412
413    /** Source of possible stalls. */
414    struct Stalls {
415        bool decode;
416        bool rename;
417        bool iew;
418        bool commit;
419    };
420
421    /** Tracks which stages are telling fetch to stall. */
422    Stalls stalls[Impl::MaxThreads];
423
424    /** Decode to fetch delay, in ticks. */
425    unsigned decodeToFetchDelay;
426
427    /** Rename to fetch delay, in ticks. */
428    unsigned renameToFetchDelay;
429
430    /** IEW to fetch delay, in ticks. */
431    unsigned iewToFetchDelay;
432
433    /** Commit to fetch delay, in ticks. */
434    unsigned commitToFetchDelay;
435
436    /** The width of fetch in instructions. */
437    unsigned fetchWidth;
438
439    /** Is the cache blocked?  If so no threads can access it. */
440    bool cacheBlocked;
441
442    /** The packet that is waiting to be retried. */
443    PacketPtr retryPkt;
444
445    /** The thread that is waiting on the cache to tell fetch to retry. */
446    ThreadID retryTid;
447
448    /** Cache block size. */
449    int cacheBlkSize;
450
451    /** Mask to get a cache block's address. */
452    Addr cacheBlkMask;
453
454    /** The cache line being fetched. */
455    uint8_t *cacheData[Impl::MaxThreads];
456
457    /** The PC of the cacheline that has been loaded. */
458    Addr cacheDataPC[Impl::MaxThreads];
459
460    /** Whether or not the cache data is valid. */
461    bool cacheDataValid[Impl::MaxThreads];
462
463    /** Size of instructions. */
464    int instSize;
465
466    /** Icache stall statistics. */
467    Counter lastIcacheStall[Impl::MaxThreads];
468
469    /** List of Active Threads */
470    std::list<ThreadID> *activeThreads;
471
472    /** Number of threads. */
473    ThreadID numThreads;
474
475    /** Number of threads that are actively fetching. */
476    ThreadID numFetchingThreads;
477
478    /** Thread ID being fetched. */
479    ThreadID threadFetched;
480
481    /** Checks if there is an interrupt pending.  If there is, fetch
482     * must stop once it is not fetching PAL instructions.
483     */
484    bool interruptPending;
485
486    /** Is there a drain pending. */
487    bool drainPending;
488
489    /** Records if fetch is switched out. */
490    bool switchedOut;
491
492    // @todo: Consider making these vectors and tracking on a per thread basis.
493    /** Stat for total number of cycles stalled due to an icache miss. */
494    Stats::Scalar icacheStallCycles;
495    /** Stat for total number of fetched instructions. */
496    Stats::Scalar fetchedInsts;
497    /** Total number of fetched branches. */
498    Stats::Scalar fetchedBranches;
499    /** Stat for total number of predicted branches. */
500    Stats::Scalar predictedBranches;
501    /** Stat for total number of cycles spent fetching. */
502    Stats::Scalar fetchCycles;
503    /** Stat for total number of cycles spent squashing. */
504    Stats::Scalar fetchSquashCycles;
505    /** Stat for total number of cycles spent waiting for translation */
506    Stats::Scalar fetchTlbCycles;
507    /** Stat for total number of cycles spent blocked due to other stages in
508     * the pipeline.
509     */
510    Stats::Scalar fetchIdleCycles;
511    /** Total number of cycles spent blocked. */
512    Stats::Scalar fetchBlockedCycles;
513    /** Total number of cycles spent in any other state. */
514    Stats::Scalar fetchMiscStallCycles;
515    /** Stat for total number of fetched cache lines. */
516    Stats::Scalar fetchedCacheLines;
517    /** Total number of outstanding icache accesses that were dropped
518     * due to a squash.
519     */
520    Stats::Scalar fetchIcacheSquashes;
521    /** Distribution of number of instructions fetched each cycle. */
522    Stats::Distribution fetchNisnDist;
523    /** Rate of how often fetch was idle. */
524    Stats::Formula idleRate;
525    /** Number of branch fetches per cycle. */
526    Stats::Formula branchRate;
527    /** Number of instruction fetched per cycle. */
528    Stats::Formula fetchRate;
529};
530
531#endif //__CPU_O3_FETCH_HH__
532