fetch.hh revision 4632:be5b8f67b8fb
110816SN/A/* 29288SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 39288SN/A * All rights reserved. 49288SN/A * 59288SN/A * Redistribution and use in source and binary forms, with or without 69288SN/A * modification, are permitted provided that the following conditions are 79288SN/A * met: redistributions of source code must retain the above copyright 89288SN/A * notice, this list of conditions and the following disclaimer; 99288SN/A * redistributions in binary form must reproduce the above copyright 109288SN/A * notice, this list of conditions and the following disclaimer in the 119288SN/A * documentation and/or other materials provided with the distribution; 129288SN/A * neither the name of the copyright holders nor the names of its 134486SN/A * contributors may be used to endorse or promote products derived from 144486SN/A * this software without specific prior written permission. 154486SN/A * 164486SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 174486SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 184486SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 194486SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 204486SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 214486SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 224486SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 234486SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 244486SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 254486SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 264486SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 274486SN/A * 284486SN/A * Authors: Kevin Lim 294486SN/A * Korey Sewell 304486SN/A */ 314486SN/A 324486SN/A#ifndef __CPU_O3_FETCH_HH__ 334486SN/A#define __CPU_O3_FETCH_HH__ 344486SN/A 354486SN/A#include "arch/utility.hh" 364486SN/A#include "arch/predecoder.hh" 374486SN/A#include "base/statistics.hh" 384486SN/A#include "base/timebuf.hh" 394486SN/A#include "cpu/pc_event.hh" 4011053Sandreas.hansson@arm.com#include "mem/packet.hh" 414486SN/A#include "mem/port.hh" 423102SN/A#include "sim/eventq.hh" 438833SN/A 442826SN/A/** 458831SN/A * DefaultFetch class handles both single threaded and SMT fetch. Its 469796SN/A * width is specified by the parameters; each cycle it tries to fetch 471615SN/A * that many instructions. It supports using a branch predictor to 482826SN/A * predict direction and targets. 491366SN/A * It supports the idling functionality of the CPU by indicating to 5011053Sandreas.hansson@arm.com * the CPU when it is active and inactive. 519338SN/A */ 5210816SN/Atemplate <class Impl> 5310816SN/Aclass DefaultFetch 5410816SN/A{ 5510816SN/A public: 5610816SN/A /** Typedefs from Impl. */ 5710816SN/A typedef typename Impl::CPUPol CPUPol; 5810816SN/A typedef typename Impl::DynInst DynInst; 591310SN/A typedef typename Impl::DynInstPtr DynInstPtr; 6010816SN/A typedef typename Impl::O3CPU O3CPU; 6110816SN/A typedef typename Impl::Params Params; 6210816SN/A 6310816SN/A /** Typedefs from the CPU policy. */ 6410816SN/A typedef typename CPUPol::BPredUnit BPredUnit; 6510816SN/A typedef typename CPUPol::FetchStruct FetchStruct; 6610816SN/A typedef typename CPUPol::TimeStruct TimeStruct; 676122SN/A 6810816SN/A /** Typedefs from ISA. */ 6910884SN/A typedef TheISA::MachInst MachInst; 7010816SN/A typedef TheISA::ExtMachInst ExtMachInst; 7110816SN/A 725875SN/A /** IcachePort class for DefaultFetch. Handles doing the 7310816SN/A * communication with the cache/memory. 7410816SN/A */ 7510816SN/A class IcachePort : public Port 7610025SN/A { 7710025SN/A protected: 7810816SN/A /** Pointer to fetch. */ 7910816SN/A DefaultFetch<Impl> *fetch; 8010816SN/A 8110816SN/A public: 8210816SN/A /** Default constructor. */ 8310816SN/A IcachePort(DefaultFetch<Impl> *_fetch) 8410816SN/A : Port(_fetch->name() + "-iport"), fetch(_fetch) 8510816SN/A { } 8611053Sandreas.hansson@arm.com 8711197Sandreas.hansson@arm.com bool snoopRangeSent; 8811197Sandreas.hansson@arm.com 8911197Sandreas.hansson@arm.com virtual void setPeer(Port *port); 9011197Sandreas.hansson@arm.com 9111053Sandreas.hansson@arm.com protected: 9211053Sandreas.hansson@arm.com /** Atomic version of receive. Panics. */ 9311053Sandreas.hansson@arm.com virtual Tick recvAtomic(PacketPtr pkt); 9411197Sandreas.hansson@arm.com 9511197Sandreas.hansson@arm.com /** Functional version of receive. Panics. */ 9611197Sandreas.hansson@arm.com virtual void recvFunctional(PacketPtr pkt); 9711197Sandreas.hansson@arm.com 9811197Sandreas.hansson@arm.com /** Receives status change. Other than range changing, panics. */ 9911197Sandreas.hansson@arm.com virtual void recvStatusChange(Status status); 10011197Sandreas.hansson@arm.com 10111197Sandreas.hansson@arm.com /** Returns the address ranges of this device. */ 10211197Sandreas.hansson@arm.com virtual void getDeviceAddressRanges(AddrRangeList &resp, 10311197Sandreas.hansson@arm.com AddrRangeList &snoop) 10411197Sandreas.hansson@arm.com { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,0)); } 10511197Sandreas.hansson@arm.com 106 /** Timing version of receive. Handles setting fetch to the 107 * proper status to start fetching. */ 108 virtual bool recvTiming(PacketPtr pkt); 109 110 /** Handles doing a retry of a failed fetch. */ 111 virtual void recvRetry(); 112 }; 113 114 115 public: 116 /** Overall fetch status. Used to determine if the CPU can 117 * deschedule itsef due to a lack of activity. 118 */ 119 enum FetchStatus { 120 Active, 121 Inactive 122 }; 123 124 /** Individual thread status. */ 125 enum ThreadStatus { 126 Running, 127 Idle, 128 Squashing, 129 Blocked, 130 Fetching, 131 TrapPending, 132 QuiescePending, 133 SwitchOut, 134 IcacheWaitResponse, 135 IcacheWaitRetry, 136 IcacheAccessComplete 137 }; 138 139 /** Fetching Policy, Add new policies here.*/ 140 enum FetchPriority { 141 SingleThread, 142 RoundRobin, 143 Branch, 144 IQ, 145 LSQ 146 }; 147 148 private: 149 /** Fetch status. */ 150 FetchStatus _status; 151 152 /** Per-thread status. */ 153 ThreadStatus fetchStatus[Impl::MaxThreads]; 154 155 /** Fetch policy. */ 156 FetchPriority fetchPolicy; 157 158 /** List that has the threads organized by priority. */ 159 std::list<unsigned> priorityList; 160 161 public: 162 /** DefaultFetch constructor. */ 163 DefaultFetch(O3CPU *_cpu, Params *params); 164 165 /** Returns the name of fetch. */ 166 std::string name() const; 167 168 /** Registers statistics. */ 169 void regStats(); 170 171 /** Returns the icache port. */ 172 Port *getIcachePort() { return icachePort; } 173 174 /** Sets the main backwards communication time buffer pointer. */ 175 void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer); 176 177 /** Sets pointer to list of active threads. */ 178 void setActiveThreads(std::list<unsigned> *at_ptr); 179 180 /** Sets pointer to time buffer used to communicate to the next stage. */ 181 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 182 183 /** Initialize stage. */ 184 void initStage(); 185 186 /** Tells the fetch stage that the Icache is set. */ 187 void setIcache(); 188 189 /** Processes cache completion event. */ 190 void processCacheCompletion(PacketPtr pkt); 191 192 /** Begins the drain of the fetch stage. */ 193 bool drain(); 194 195 /** Resumes execution after a drain. */ 196 void resume(); 197 198 /** Tells fetch stage to prepare to be switched out. */ 199 void switchOut(); 200 201 /** Takes over from another CPU's thread. */ 202 void takeOverFrom(); 203 204 /** Checks if the fetch stage is switched out. */ 205 bool isSwitchedOut() { return switchedOut; } 206 207 /** Tells fetch to wake up from a quiesce instruction. */ 208 void wakeFromQuiesce(); 209 210 private: 211 /** Changes the status of this stage to active, and indicates this 212 * to the CPU. 213 */ 214 inline void switchToActive(); 215 216 /** Changes the status of this stage to inactive, and indicates 217 * this to the CPU. 218 */ 219 inline void switchToInactive(); 220 221 /** 222 * Looks up in the branch predictor to see if the next PC should be 223 * either next PC+=MachInst or a branch target. 224 * @param next_PC Next PC variable passed in by reference. It is 225 * expected to be set to the current PC; it will be updated with what 226 * the next PC will be. 227 * @param next_NPC Used for ISAs which use delay slots. 228 * @return Whether or not a branch was predicted as taken. 229 */ 230 bool lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC, Addr &next_NPC); 231 232 /** 233 * Fetches the cache line that contains fetch_PC. Returns any 234 * fault that happened. Puts the data into the class variable 235 * cacheData. 236 * @param fetch_PC The PC address that is being fetched from. 237 * @param ret_fault The fault reference that will be set to the result of 238 * the icache access. 239 * @param tid Thread id. 240 * @return Any fault that occured. 241 */ 242 bool fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid); 243 244 /** Squashes a specific thread and resets the PC. */ 245 inline void doSquash(const Addr &new_PC, const Addr &new_NPC, unsigned tid); 246 247 /** Squashes a specific thread and resets the PC. Also tells the CPU to 248 * remove any instructions between fetch and decode that should be sqaushed. 249 */ 250 void squashFromDecode(const Addr &new_PC, const Addr &new_NPC, 251 const InstSeqNum &seq_num, unsigned tid); 252 253 /** Checks if a thread is stalled. */ 254 bool checkStall(unsigned tid) const; 255 256 /** Updates overall fetch stage status; to be called at the end of each 257 * cycle. */ 258 FetchStatus updateFetchStatus(); 259 260 public: 261 /** Squashes a specific thread and resets the PC. Also tells the CPU to 262 * remove any instructions that are not in the ROB. The source of this 263 * squash should be the commit stage. 264 */ 265 void squash(const Addr &new_PC, const Addr &new_NPC, 266 const InstSeqNum &seq_num, unsigned tid); 267 268 /** Ticks the fetch stage, processing all inputs signals and fetching 269 * as many instructions as possible. 270 */ 271 void tick(); 272 273 /** Checks all input signals and updates the status as necessary. 274 * @return: Returns if the status has changed due to input signals. 275 */ 276 bool checkSignalsAndUpdate(unsigned tid); 277 278 /** Does the actual fetching of instructions and passing them on to the 279 * next stage. 280 * @param status_change fetch() sets this variable if there was a status 281 * change (ie switching to IcacheMissStall). 282 */ 283 void fetch(bool &status_change); 284 285 /** Align a PC to the start of an I-cache block. */ 286 Addr icacheBlockAlignPC(Addr addr) 287 { 288 addr = TheISA::realPCToFetchPC(addr); 289 return (addr & ~(cacheBlkMask)); 290 } 291 292 private: 293 /** Handles retrying the fetch access. */ 294 void recvRetry(); 295 296 /** Returns the appropriate thread to fetch, given the fetch policy. */ 297 int getFetchingThread(FetchPriority &fetch_priority); 298 299 /** Returns the appropriate thread to fetch using a round robin policy. */ 300 int roundRobin(); 301 302 /** Returns the appropriate thread to fetch using the IQ count policy. */ 303 int iqCount(); 304 305 /** Returns the appropriate thread to fetch using the LSQ count policy. */ 306 int lsqCount(); 307 308 /** Returns the appropriate thread to fetch using the branch count policy. */ 309 int branchCount(); 310 311 private: 312 /** Pointer to the O3CPU. */ 313 O3CPU *cpu; 314 315 /** Time buffer interface. */ 316 TimeBuffer<TimeStruct> *timeBuffer; 317 318 /** Wire to get decode's information from backwards time buffer. */ 319 typename TimeBuffer<TimeStruct>::wire fromDecode; 320 321 /** Wire to get rename's information from backwards time buffer. */ 322 typename TimeBuffer<TimeStruct>::wire fromRename; 323 324 /** Wire to get iew's information from backwards time buffer. */ 325 typename TimeBuffer<TimeStruct>::wire fromIEW; 326 327 /** Wire to get commit's information from backwards time buffer. */ 328 typename TimeBuffer<TimeStruct>::wire fromCommit; 329 330 /** Internal fetch instruction queue. */ 331 TimeBuffer<FetchStruct> *fetchQueue; 332 333 //Might be annoying how this name is different than the queue. 334 /** Wire used to write any information heading to decode. */ 335 typename TimeBuffer<FetchStruct>::wire toDecode; 336 337 /** Icache interface. */ 338 IcachePort *icachePort; 339 340 /** BPredUnit. */ 341 BPredUnit branchPred; 342 343 /** Predecoder. */ 344 TheISA::Predecoder predecoder; 345 346 /** Per-thread fetch PC. */ 347 Addr PC[Impl::MaxThreads]; 348 349 /** Per-thread next PC. */ 350 Addr nextPC[Impl::MaxThreads]; 351 352 /** Per-thread next Next PC. 353 * This is not a real register but is used for 354 * architectures that use a branch-delay slot. 355 * (such as MIPS or Sparc) 356 */ 357 Addr nextNPC[Impl::MaxThreads]; 358 359 /** Memory request used to access cache. */ 360 RequestPtr memReq[Impl::MaxThreads]; 361 362 /** Variable that tracks if fetch has written to the time buffer this 363 * cycle. Used to tell CPU if there is activity this cycle. 364 */ 365 bool wroteToTimeBuffer; 366 367 /** Tracks how many instructions has been fetched this cycle. */ 368 int numInst; 369 370 /** Source of possible stalls. */ 371 struct Stalls { 372 bool decode; 373 bool rename; 374 bool iew; 375 bool commit; 376 }; 377 378 /** Tracks which stages are telling fetch to stall. */ 379 Stalls stalls[Impl::MaxThreads]; 380 381 /** Decode to fetch delay, in ticks. */ 382 unsigned decodeToFetchDelay; 383 384 /** Rename to fetch delay, in ticks. */ 385 unsigned renameToFetchDelay; 386 387 /** IEW to fetch delay, in ticks. */ 388 unsigned iewToFetchDelay; 389 390 /** Commit to fetch delay, in ticks. */ 391 unsigned commitToFetchDelay; 392 393 /** The width of fetch in instructions. */ 394 unsigned fetchWidth; 395 396 /** Is the cache blocked? If so no threads can access it. */ 397 bool cacheBlocked; 398 399 /** The packet that is waiting to be retried. */ 400 PacketPtr retryPkt; 401 402 /** The thread that is waiting on the cache to tell fetch to retry. */ 403 int retryTid; 404 405 /** Cache block size. */ 406 int cacheBlkSize; 407 408 /** Mask to get a cache block's address. */ 409 Addr cacheBlkMask; 410 411 /** The cache line being fetched. */ 412 uint8_t *cacheData[Impl::MaxThreads]; 413 414 /** The PC of the cacheline that has been loaded. */ 415 Addr cacheDataPC[Impl::MaxThreads]; 416 417 /** Whether or not the cache data is valid. */ 418 bool cacheDataValid[Impl::MaxThreads]; 419 420 /** Size of instructions. */ 421 int instSize; 422 423 /** Icache stall statistics. */ 424 Counter lastIcacheStall[Impl::MaxThreads]; 425 426 /** List of Active Threads */ 427 std::list<unsigned> *activeThreads; 428 429 /** Number of threads. */ 430 unsigned numThreads; 431 432 /** Number of threads that are actively fetching. */ 433 unsigned numFetchingThreads; 434 435 /** Thread ID being fetched. */ 436 int threadFetched; 437 438 /** Checks if there is an interrupt pending. If there is, fetch 439 * must stop once it is not fetching PAL instructions. 440 */ 441 bool interruptPending; 442 443 /** Is there a drain pending. */ 444 bool drainPending; 445 446 /** Records if fetch is switched out. */ 447 bool switchedOut; 448 449 // @todo: Consider making these vectors and tracking on a per thread basis. 450 /** Stat for total number of cycles stalled due to an icache miss. */ 451 Stats::Scalar<> icacheStallCycles; 452 /** Stat for total number of fetched instructions. */ 453 Stats::Scalar<> fetchedInsts; 454 /** Total number of fetched branches. */ 455 Stats::Scalar<> fetchedBranches; 456 /** Stat for total number of predicted branches. */ 457 Stats::Scalar<> predictedBranches; 458 /** Stat for total number of cycles spent fetching. */ 459 Stats::Scalar<> fetchCycles; 460 /** Stat for total number of cycles spent squashing. */ 461 Stats::Scalar<> fetchSquashCycles; 462 /** Stat for total number of cycles spent blocked due to other stages in 463 * the pipeline. 464 */ 465 Stats::Scalar<> fetchIdleCycles; 466 /** Total number of cycles spent blocked. */ 467 Stats::Scalar<> fetchBlockedCycles; 468 /** Total number of cycles spent in any other state. */ 469 Stats::Scalar<> fetchMiscStallCycles; 470 /** Stat for total number of fetched cache lines. */ 471 Stats::Scalar<> fetchedCacheLines; 472 /** Total number of outstanding icache accesses that were dropped 473 * due to a squash. 474 */ 475 Stats::Scalar<> fetchIcacheSquashes; 476 /** Distribution of number of instructions fetched each cycle. */ 477 Stats::Distribution<> fetchNisnDist; 478 /** Rate of how often fetch was idle. */ 479 Stats::Formula idleRate; 480 /** Number of branch fetches per cycle. */ 481 Stats::Formula branchRate; 482 /** Number of instruction fetched per cycle. */ 483 Stats::Formula fetchRate; 484}; 485 486#endif //__CPU_O3_FETCH_HH__ 487