fetch.hh revision 11246:93d2a1526103
13938Ssaidi@eecs.umich.edu/* 212225Sgiacomo.travaglini@arm.com * Copyright (c) 2010-2012, 2014 ARM Limited 39419Sandreas.hansson@arm.com * All rights reserved 49419Sandreas.hansson@arm.com * 59419Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 69419Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 79419Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 89419Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 99419Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 109419Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 119419Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 129419Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 139419Sandreas.hansson@arm.com * 143938Ssaidi@eecs.umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 153938Ssaidi@eecs.umich.edu * All rights reserved. 163938Ssaidi@eecs.umich.edu * 173938Ssaidi@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 183938Ssaidi@eecs.umich.edu * modification, are permitted provided that the following conditions are 193938Ssaidi@eecs.umich.edu * met: redistributions of source code must retain the above copyright 203938Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 213938Ssaidi@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 223938Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 233938Ssaidi@eecs.umich.edu * documentation and/or other materials provided with the distribution; 243938Ssaidi@eecs.umich.edu * neither the name of the copyright holders nor the names of its 253938Ssaidi@eecs.umich.edu * contributors may be used to endorse or promote products derived from 263938Ssaidi@eecs.umich.edu * this software without specific prior written permission. 273938Ssaidi@eecs.umich.edu * 283938Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 293938Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 303938Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 313938Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 323938Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 333938Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 343938Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 353938Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 363938Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 373938Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 383938Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 393938Ssaidi@eecs.umich.edu * 403938Ssaidi@eecs.umich.edu * Authors: Kevin Lim 413938Ssaidi@eecs.umich.edu * Korey Sewell 423938Ssaidi@eecs.umich.edu */ 433938Ssaidi@eecs.umich.edu 443938Ssaidi@eecs.umich.edu#ifndef __CPU_O3_FETCH_HH__ 453938Ssaidi@eecs.umich.edu#define __CPU_O3_FETCH_HH__ 4612225Sgiacomo.travaglini@arm.com 4712225Sgiacomo.travaglini@arm.com#include "arch/decoder.hh" 489419Sandreas.hansson@arm.com#include "arch/utility.hh" 493938Ssaidi@eecs.umich.edu#include "base/statistics.hh" 5010291SAndreas.Sandberg@ARM.com#include "config/the_isa.hh" 5110291SAndreas.Sandberg@ARM.com#include "cpu/pc_event.hh" 5210291SAndreas.Sandberg@ARM.com#include "cpu/pred/bpred_unit.hh" 5310291SAndreas.Sandberg@ARM.com#include "cpu/timebuf.hh" 5410291SAndreas.Sandberg@ARM.com#include "cpu/translation.hh" 5510291SAndreas.Sandberg@ARM.com#include "mem/packet.hh" 5610686SAndreas.Sandberg@ARM.com#include "mem/port.hh" 5710686SAndreas.Sandberg@ARM.com#include "sim/eventq.hh" 5812595Ssiddhesh.poyarekar@gmail.com#include "sim/probe/probe.hh" 5910291SAndreas.Sandberg@ARM.com 6010104Smitch.hayenga@arm.comstruct DerivO3CPUParams; 6110104Smitch.hayenga@arm.com 6210291SAndreas.Sandberg@ARM.com/** 6310104Smitch.hayenga@arm.com * DefaultFetch class handles both single threaded and SMT fetch. Its 6410291SAndreas.Sandberg@ARM.com * width is specified by the parameters; each cycle it tries to fetch 653938Ssaidi@eecs.umich.edu * that many instructions. It supports using a branch predictor to 663938Ssaidi@eecs.umich.edu * predict direction and targets. 6712392Sjason@lowepower.com * It supports the idling functionality of the CPU by indicating to 6812392Sjason@lowepower.com * the CPU when it is active and inactive. 6912392Sjason@lowepower.com */ 7012392Sjason@lowepower.comtemplate <class Impl> 7112392Sjason@lowepower.comclass DefaultFetch 7212392Sjason@lowepower.com{ 7312392Sjason@lowepower.com public: 7412392Sjason@lowepower.com /** Typedefs from Impl. */ 7512392Sjason@lowepower.com typedef typename Impl::CPUPol CPUPol; 7612392Sjason@lowepower.com typedef typename Impl::DynInst DynInst; 7712392Sjason@lowepower.com typedef typename Impl::DynInstPtr DynInstPtr; 7812392Sjason@lowepower.com typedef typename Impl::O3CPU O3CPU; 7912392Sjason@lowepower.com 8012392Sjason@lowepower.com /** Typedefs from the CPU policy. */ 8112225Sgiacomo.travaglini@arm.com typedef typename CPUPol::FetchStruct FetchStruct; 8212225Sgiacomo.travaglini@arm.com typedef typename CPUPol::TimeStruct TimeStruct; 8312225Sgiacomo.travaglini@arm.com 8412225Sgiacomo.travaglini@arm.com /** Typedefs from ISA. */ 8512225Sgiacomo.travaglini@arm.com typedef TheISA::MachInst MachInst; 8612225Sgiacomo.travaglini@arm.com typedef TheISA::ExtMachInst ExtMachInst; 8712225Sgiacomo.travaglini@arm.com 8812225Sgiacomo.travaglini@arm.com class FetchTranslation : public BaseTLB::Translation 8912225Sgiacomo.travaglini@arm.com { 9012225Sgiacomo.travaglini@arm.com protected: 9112225Sgiacomo.travaglini@arm.com DefaultFetch<Impl> *fetch; 9212225Sgiacomo.travaglini@arm.com 9312225Sgiacomo.travaglini@arm.com public: 9412225Sgiacomo.travaglini@arm.com FetchTranslation(DefaultFetch<Impl> *_fetch) 9512225Sgiacomo.travaglini@arm.com : fetch(_fetch) 9612225Sgiacomo.travaglini@arm.com {} 9712225Sgiacomo.travaglini@arm.com 9812225Sgiacomo.travaglini@arm.com void 9912225Sgiacomo.travaglini@arm.com markDelayed() 10012225Sgiacomo.travaglini@arm.com {} 10112225Sgiacomo.travaglini@arm.com 10212225Sgiacomo.travaglini@arm.com void 10312225Sgiacomo.travaglini@arm.com finish(const Fault &fault, RequestPtr req, ThreadContext *tc, 10412225Sgiacomo.travaglini@arm.com BaseTLB::Mode mode) 1053938Ssaidi@eecs.umich.edu { 106 assert(mode == BaseTLB::Execute); 107 fetch->finishTranslation(fault, req); 108 delete this; 109 } 110 }; 111 112 private: 113 /* Event to delay delivery of a fetch translation result in case of 114 * a fault and the nop to carry the fault cannot be generated 115 * immediately */ 116 class FinishTranslationEvent : public Event 117 { 118 private: 119 DefaultFetch<Impl> *fetch; 120 Fault fault; 121 RequestPtr req; 122 123 public: 124 FinishTranslationEvent(DefaultFetch<Impl> *_fetch) 125 : fetch(_fetch) 126 {} 127 128 void setFault(Fault _fault) 129 { 130 fault = _fault; 131 } 132 133 void setReq(RequestPtr _req) 134 { 135 req = _req; 136 } 137 138 /** Process the delayed finish translation */ 139 void process() 140 { 141 assert(fetch->numInst < fetch->fetchWidth); 142 fetch->finishTranslation(fault, req); 143 } 144 145 const char *description() const 146 { 147 return "FullO3CPU FetchFinishTranslation"; 148 } 149 }; 150 151 public: 152 /** Overall fetch status. Used to determine if the CPU can 153 * deschedule itsef due to a lack of activity. 154 */ 155 enum FetchStatus { 156 Active, 157 Inactive 158 }; 159 160 /** Individual thread status. */ 161 enum ThreadStatus { 162 Running, 163 Idle, 164 Squashing, 165 Blocked, 166 Fetching, 167 TrapPending, 168 QuiescePending, 169 ItlbWait, 170 IcacheWaitResponse, 171 IcacheWaitRetry, 172 IcacheAccessComplete, 173 NoGoodAddr 174 }; 175 176 /** Fetching Policy, Add new policies here.*/ 177 enum FetchPriority { 178 SingleThread, 179 RoundRobin, 180 Branch, 181 IQ, 182 LSQ 183 }; 184 185 private: 186 /** Fetch status. */ 187 FetchStatus _status; 188 189 /** Per-thread status. */ 190 ThreadStatus fetchStatus[Impl::MaxThreads]; 191 192 /** Fetch policy. */ 193 FetchPriority fetchPolicy; 194 195 /** List that has the threads organized by priority. */ 196 std::list<ThreadID> priorityList; 197 198 /** Probe points. */ 199 ProbePointArg<DynInstPtr> *ppFetch; 200 /** To probe when a fetch request is successfully sent. */ 201 ProbePointArg<RequestPtr> *ppFetchRequestSent; 202 203 public: 204 /** DefaultFetch constructor. */ 205 DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params); 206 207 /** Returns the name of fetch. */ 208 std::string name() const; 209 210 /** Registers statistics. */ 211 void regStats(); 212 213 /** Registers probes. */ 214 void regProbePoints(); 215 216 /** Sets the main backwards communication time buffer pointer. */ 217 void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer); 218 219 /** Sets pointer to list of active threads. */ 220 void setActiveThreads(std::list<ThreadID> *at_ptr); 221 222 /** Sets pointer to time buffer used to communicate to the next stage. */ 223 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 224 225 /** Initialize stage. */ 226 void startupStage(); 227 228 /** Handles retrying the fetch access. */ 229 void recvReqRetry(); 230 231 /** Processes cache completion event. */ 232 void processCacheCompletion(PacketPtr pkt); 233 234 /** Resume after a drain. */ 235 void drainResume(); 236 237 /** Perform sanity checks after a drain. */ 238 void drainSanityCheck() const; 239 240 /** Has the stage drained? */ 241 bool isDrained() const; 242 243 /** Takes over from another CPU's thread. */ 244 void takeOverFrom(); 245 246 /** 247 * Stall the fetch stage after reaching a safe drain point. 248 * 249 * The CPU uses this method to stop fetching instructions from a 250 * thread that has been drained. The drain stall is different from 251 * all other stalls in that it is signaled instantly from the 252 * commit stage (without the normal communication delay) when it 253 * has reached a safe point to drain from. 254 */ 255 void drainStall(ThreadID tid); 256 257 /** Tells fetch to wake up from a quiesce instruction. */ 258 void wakeFromQuiesce(); 259 260 /** For priority-based fetch policies, need to keep update priorityList */ 261 void deactivateThread(ThreadID tid); 262 private: 263 /** Reset this pipeline stage */ 264 void resetStage(); 265 266 /** Changes the status of this stage to active, and indicates this 267 * to the CPU. 268 */ 269 inline void switchToActive(); 270 271 /** Changes the status of this stage to inactive, and indicates 272 * this to the CPU. 273 */ 274 inline void switchToInactive(); 275 276 /** 277 * Looks up in the branch predictor to see if the next PC should be 278 * either next PC+=MachInst or a branch target. 279 * @param next_PC Next PC variable passed in by reference. It is 280 * expected to be set to the current PC; it will be updated with what 281 * the next PC will be. 282 * @param next_NPC Used for ISAs which use delay slots. 283 * @return Whether or not a branch was predicted as taken. 284 */ 285 bool lookupAndUpdateNextPC(DynInstPtr &inst, TheISA::PCState &pc); 286 287 /** 288 * Fetches the cache line that contains the fetch PC. Returns any 289 * fault that happened. Puts the data into the class variable 290 * fetchBuffer, which may not hold the entire fetched cache line. 291 * @param vaddr The memory address that is being fetched from. 292 * @param ret_fault The fault reference that will be set to the result of 293 * the icache access. 294 * @param tid Thread id. 295 * @param pc The actual PC of the current instruction. 296 * @return Any fault that occured. 297 */ 298 bool fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc); 299 void finishTranslation(const Fault &fault, RequestPtr mem_req); 300 301 302 /** Check if an interrupt is pending and that we need to handle 303 */ 304 bool 305 checkInterrupt(Addr pc) 306 { 307 return (interruptPending && (THE_ISA != ALPHA_ISA || !(pc & 0x3))); 308 } 309 310 /** Squashes a specific thread and resets the PC. */ 311 inline void doSquash(const TheISA::PCState &newPC, 312 const DynInstPtr squashInst, ThreadID tid); 313 314 /** Squashes a specific thread and resets the PC. Also tells the CPU to 315 * remove any instructions between fetch and decode that should be sqaushed. 316 */ 317 void squashFromDecode(const TheISA::PCState &newPC, 318 const DynInstPtr squashInst, 319 const InstSeqNum seq_num, ThreadID tid); 320 321 /** Checks if a thread is stalled. */ 322 bool checkStall(ThreadID tid) const; 323 324 /** Updates overall fetch stage status; to be called at the end of each 325 * cycle. */ 326 FetchStatus updateFetchStatus(); 327 328 public: 329 /** Squashes a specific thread and resets the PC. Also tells the CPU to 330 * remove any instructions that are not in the ROB. The source of this 331 * squash should be the commit stage. 332 */ 333 void squash(const TheISA::PCState &newPC, const InstSeqNum seq_num, 334 DynInstPtr squashInst, ThreadID tid); 335 336 /** Ticks the fetch stage, processing all inputs signals and fetching 337 * as many instructions as possible. 338 */ 339 void tick(); 340 341 /** Checks all input signals and updates the status as necessary. 342 * @return: Returns if the status has changed due to input signals. 343 */ 344 bool checkSignalsAndUpdate(ThreadID tid); 345 346 /** Does the actual fetching of instructions and passing them on to the 347 * next stage. 348 * @param status_change fetch() sets this variable if there was a status 349 * change (ie switching to IcacheMissStall). 350 */ 351 void fetch(bool &status_change); 352 353 /** Align a PC to the start of a fetch buffer block. */ 354 Addr fetchBufferAlignPC(Addr addr) 355 { 356 return (addr & ~(fetchBufferMask)); 357 } 358 359 /** The decoder. */ 360 TheISA::Decoder *decoder[Impl::MaxThreads]; 361 362 private: 363 DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst, 364 StaticInstPtr curMacroop, TheISA::PCState thisPC, 365 TheISA::PCState nextPC, bool trace); 366 367 /** Returns the appropriate thread to fetch, given the fetch policy. */ 368 ThreadID getFetchingThread(FetchPriority &fetch_priority); 369 370 /** Returns the appropriate thread to fetch using a round robin policy. */ 371 ThreadID roundRobin(); 372 373 /** Returns the appropriate thread to fetch using the IQ count policy. */ 374 ThreadID iqCount(); 375 376 /** Returns the appropriate thread to fetch using the LSQ count policy. */ 377 ThreadID lsqCount(); 378 379 /** Returns the appropriate thread to fetch using the branch count 380 * policy. */ 381 ThreadID branchCount(); 382 383 /** Pipeline the next I-cache access to the current one. */ 384 void pipelineIcacheAccesses(ThreadID tid); 385 386 /** Profile the reasons of fetch stall. */ 387 void profileStall(ThreadID tid); 388 389 private: 390 /** Pointer to the O3CPU. */ 391 O3CPU *cpu; 392 393 /** Time buffer interface. */ 394 TimeBuffer<TimeStruct> *timeBuffer; 395 396 /** Wire to get decode's information from backwards time buffer. */ 397 typename TimeBuffer<TimeStruct>::wire fromDecode; 398 399 /** Wire to get rename's information from backwards time buffer. */ 400 typename TimeBuffer<TimeStruct>::wire fromRename; 401 402 /** Wire to get iew's information from backwards time buffer. */ 403 typename TimeBuffer<TimeStruct>::wire fromIEW; 404 405 /** Wire to get commit's information from backwards time buffer. */ 406 typename TimeBuffer<TimeStruct>::wire fromCommit; 407 408 //Might be annoying how this name is different than the queue. 409 /** Wire used to write any information heading to decode. */ 410 typename TimeBuffer<FetchStruct>::wire toDecode; 411 412 /** BPredUnit. */ 413 BPredUnit *branchPred; 414 415 TheISA::PCState pc[Impl::MaxThreads]; 416 417 Addr fetchOffset[Impl::MaxThreads]; 418 419 StaticInstPtr macroop[Impl::MaxThreads]; 420 421 /** Can the fetch stage redirect from an interrupt on this instruction? */ 422 bool delayedCommit[Impl::MaxThreads]; 423 424 /** Memory request used to access cache. */ 425 RequestPtr memReq[Impl::MaxThreads]; 426 427 /** Variable that tracks if fetch has written to the time buffer this 428 * cycle. Used to tell CPU if there is activity this cycle. 429 */ 430 bool wroteToTimeBuffer; 431 432 /** Tracks how many instructions has been fetched this cycle. */ 433 int numInst; 434 435 /** Source of possible stalls. */ 436 struct Stalls { 437 bool decode; 438 bool drain; 439 }; 440 441 /** Tracks which stages are telling fetch to stall. */ 442 Stalls stalls[Impl::MaxThreads]; 443 444 /** Decode to fetch delay. */ 445 Cycles decodeToFetchDelay; 446 447 /** Rename to fetch delay. */ 448 Cycles renameToFetchDelay; 449 450 /** IEW to fetch delay. */ 451 Cycles iewToFetchDelay; 452 453 /** Commit to fetch delay. */ 454 Cycles commitToFetchDelay; 455 456 /** The width of fetch in instructions. */ 457 unsigned fetchWidth; 458 459 /** The width of decode in instructions. */ 460 unsigned decodeWidth; 461 462 /** Is the cache blocked? If so no threads can access it. */ 463 bool cacheBlocked; 464 465 /** The packet that is waiting to be retried. */ 466 PacketPtr retryPkt; 467 468 /** The thread that is waiting on the cache to tell fetch to retry. */ 469 ThreadID retryTid; 470 471 /** Cache block size. */ 472 unsigned int cacheBlkSize; 473 474 /** The size of the fetch buffer in bytes. The fetch buffer 475 * itself may be smaller than a cache line. 476 */ 477 unsigned fetchBufferSize; 478 479 /** Mask to align a fetch address to a fetch buffer boundary. */ 480 Addr fetchBufferMask; 481 482 /** The fetch data that is being fetched and buffered. */ 483 uint8_t *fetchBuffer[Impl::MaxThreads]; 484 485 /** The PC of the first instruction loaded into the fetch buffer. */ 486 Addr fetchBufferPC[Impl::MaxThreads]; 487 488 /** The size of the fetch queue in micro-ops */ 489 unsigned fetchQueueSize; 490 491 /** Queue of fetched instructions. Per-thread to prevent HoL blocking. */ 492 std::deque<DynInstPtr> fetchQueue[Impl::MaxThreads]; 493 494 /** Whether or not the fetch buffer data is valid. */ 495 bool fetchBufferValid[Impl::MaxThreads]; 496 497 /** Size of instructions. */ 498 int instSize; 499 500 /** Icache stall statistics. */ 501 Counter lastIcacheStall[Impl::MaxThreads]; 502 503 /** List of Active Threads */ 504 std::list<ThreadID> *activeThreads; 505 506 /** Number of threads. */ 507 ThreadID numThreads; 508 509 /** Number of threads that are actively fetching. */ 510 ThreadID numFetchingThreads; 511 512 /** Thread ID being fetched. */ 513 ThreadID threadFetched; 514 515 /** Checks if there is an interrupt pending. If there is, fetch 516 * must stop once it is not fetching PAL instructions. 517 */ 518 bool interruptPending; 519 520 /** Set to true if a pipelined I-cache request should be issued. */ 521 bool issuePipelinedIfetch[Impl::MaxThreads]; 522 523 /** Event used to delay fault generation of translation faults */ 524 FinishTranslationEvent finishTranslationEvent; 525 526 // @todo: Consider making these vectors and tracking on a per thread basis. 527 /** Stat for total number of cycles stalled due to an icache miss. */ 528 Stats::Scalar icacheStallCycles; 529 /** Stat for total number of fetched instructions. */ 530 Stats::Scalar fetchedInsts; 531 /** Total number of fetched branches. */ 532 Stats::Scalar fetchedBranches; 533 /** Stat for total number of predicted branches. */ 534 Stats::Scalar predictedBranches; 535 /** Stat for total number of cycles spent fetching. */ 536 Stats::Scalar fetchCycles; 537 /** Stat for total number of cycles spent squashing. */ 538 Stats::Scalar fetchSquashCycles; 539 /** Stat for total number of cycles spent waiting for translation */ 540 Stats::Scalar fetchTlbCycles; 541 /** Stat for total number of cycles spent blocked due to other stages in 542 * the pipeline. 543 */ 544 Stats::Scalar fetchIdleCycles; 545 /** Total number of cycles spent blocked. */ 546 Stats::Scalar fetchBlockedCycles; 547 /** Total number of cycles spent in any other state. */ 548 Stats::Scalar fetchMiscStallCycles; 549 /** Total number of cycles spent in waiting for drains. */ 550 Stats::Scalar fetchPendingDrainCycles; 551 /** Total number of stall cycles caused by no active threads to run. */ 552 Stats::Scalar fetchNoActiveThreadStallCycles; 553 /** Total number of stall cycles caused by pending traps. */ 554 Stats::Scalar fetchPendingTrapStallCycles; 555 /** Total number of stall cycles caused by pending quiesce instructions. */ 556 Stats::Scalar fetchPendingQuiesceStallCycles; 557 /** Total number of stall cycles caused by I-cache wait retrys. */ 558 Stats::Scalar fetchIcacheWaitRetryStallCycles; 559 /** Stat for total number of fetched cache lines. */ 560 Stats::Scalar fetchedCacheLines; 561 /** Total number of outstanding icache accesses that were dropped 562 * due to a squash. 563 */ 564 Stats::Scalar fetchIcacheSquashes; 565 /** Total number of outstanding tlb accesses that were dropped 566 * due to a squash. 567 */ 568 Stats::Scalar fetchTlbSquashes; 569 /** Distribution of number of instructions fetched each cycle. */ 570 Stats::Distribution fetchNisnDist; 571 /** Rate of how often fetch was idle. */ 572 Stats::Formula idleRate; 573 /** Number of branch fetches per cycle. */ 574 Stats::Formula branchRate; 575 /** Number of instruction fetched per cycle. */ 576 Stats::Formula fetchRate; 577}; 578 579#endif //__CPU_O3_FETCH_HH__ 580