fetch.hh revision 10331:ed05298e8566 
1/*
2 * Copyright (c) 2010-2012, 2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 *          Korey Sewell
42 */
43
44#ifndef __CPU_O3_FETCH_HH__
45#define __CPU_O3_FETCH_HH__
46
47#include "arch/decoder.hh"
48#include "arch/utility.hh"
49#include "base/statistics.hh"
50#include "config/the_isa.hh"
51#include "cpu/pc_event.hh"
52#include "cpu/pred/bpred_unit.hh"
53#include "cpu/timebuf.hh"
54#include "cpu/translation.hh"
55#include "mem/packet.hh"
56#include "mem/port.hh"
57#include "sim/eventq.hh"
58#include "sim/probe/probe.hh"
59
60struct DerivO3CPUParams;
61
62/**
63 * DefaultFetch class handles both single threaded and SMT fetch. Its
64 * width is specified by the parameters; each cycle it tries to fetch
65 * that many instructions. It supports using a branch predictor to
66 * predict direction and targets.
67 * It supports the idling functionality of the CPU by indicating to
68 * the CPU when it is active and inactive.
69 */
70template <class Impl>
71class DefaultFetch
72{
73  public:
74    /** Typedefs from Impl. */
75    typedef typename Impl::CPUPol CPUPol;
76    typedef typename Impl::DynInst DynInst;
77    typedef typename Impl::DynInstPtr DynInstPtr;
78    typedef typename Impl::O3CPU O3CPU;
79
80    /** Typedefs from the CPU policy. */
81    typedef typename CPUPol::FetchStruct FetchStruct;
82    typedef typename CPUPol::TimeStruct TimeStruct;
83
84    /** Typedefs from ISA. */
85    typedef TheISA::MachInst MachInst;
86    typedef TheISA::ExtMachInst ExtMachInst;
87
88    class FetchTranslation : public BaseTLB::Translation
89    {
90      protected:
91        DefaultFetch<Impl> *fetch;
92
93      public:
94        FetchTranslation(DefaultFetch<Impl> *_fetch)
95            : fetch(_fetch)
96        {}
97
98        void
99        markDelayed()
100        {}
101
102        void
103        finish(Fault fault, RequestPtr req, ThreadContext *tc,
104               BaseTLB::Mode mode)
105        {
106            assert(mode == BaseTLB::Execute);
107            fetch->finishTranslation(fault, req);
108            delete this;
109        }
110    };
111
112  private:
113    /* Event to delay delivery of a fetch translation result in case of
114     * a fault and the nop to carry the fault cannot be generated
115     * immediately */
116    class FinishTranslationEvent : public Event
117    {
118      private:
119        DefaultFetch<Impl> *fetch;
120        Fault fault;
121        RequestPtr req;
122
123      public:
124        FinishTranslationEvent(DefaultFetch<Impl> *_fetch)
125            : fetch(_fetch)
126        {}
127
128        void setFault(Fault _fault)
129        {
130            fault = _fault;
131        }
132
133        void setReq(RequestPtr _req)
134        {
135            req = _req;
136        }
137
138        /** Process the delayed finish translation */
139        void process()
140        {
141            assert(fetch->numInst < fetch->fetchWidth);
142            fetch->finishTranslation(fault, req);
143        }
144
145        const char *description() const
146        {
147            return "FullO3CPU FetchFinishTranslation";
148        }
149      };
150
151  public:
152    /** Overall fetch status. Used to determine if the CPU can
153     * deschedule itsef due to a lack of activity.
154     */
155    enum FetchStatus {
156        Active,
157        Inactive
158    };
159
160    /** Individual thread status. */
161    enum ThreadStatus {
162        Running,
163        Idle,
164        Squashing,
165        Blocked,
166        Fetching,
167        TrapPending,
168        QuiescePending,
169        ItlbWait,
170        IcacheWaitResponse,
171        IcacheWaitRetry,
172        IcacheAccessComplete,
173        NoGoodAddr
174    };
175
176    /** Fetching Policy, Add new policies here.*/
177    enum FetchPriority {
178        SingleThread,
179        RoundRobin,
180        Branch,
181        IQ,
182        LSQ
183    };
184
185  private:
186    /** Fetch status. */
187    FetchStatus _status;
188
189    /** Per-thread status. */
190    ThreadStatus fetchStatus[Impl::MaxThreads];
191
192    /** Fetch policy. */
193    FetchPriority fetchPolicy;
194
195    /** List that has the threads organized by priority. */
196    std::list<ThreadID> priorityList;
197
198    /** Probe points. */
199    ProbePointArg<DynInstPtr> *ppFetch;
200
201  public:
202    /** DefaultFetch constructor. */
203    DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params);
204
205    /** Returns the name of fetch. */
206    std::string name() const;
207
208    /** Registers statistics. */
209    void regStats();
210
211    /** Registers probes. */
212    void regProbePoints();
213
214    /** Sets the main backwards communication time buffer pointer. */
215    void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
216
217    /** Sets pointer to list of active threads. */
218    void setActiveThreads(std::list<ThreadID> *at_ptr);
219
220    /** Sets pointer to time buffer used to communicate to the next stage. */
221    void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
222
223    /** Initialize stage. */
224    void startupStage();
225
226    /** Handles retrying the fetch access. */
227    void recvRetry();
228
229    /** Processes cache completion event. */
230    void processCacheCompletion(PacketPtr pkt);
231
232    /** Resume after a drain. */
233    void drainResume();
234
235    /** Perform sanity checks after a drain. */
236    void drainSanityCheck() const;
237
238    /** Has the stage drained? */
239    bool isDrained() const;
240
241    /** Takes over from another CPU's thread. */
242    void takeOverFrom();
243
244    /**
245     * Stall the fetch stage after reaching a safe drain point.
246     *
247     * The CPU uses this method to stop fetching instructions from a
248     * thread that has been drained. The drain stall is different from
249     * all other stalls in that it is signaled instantly from the
250     * commit stage (without the normal communication delay) when it
251     * has reached a safe point to drain from.
252     */
253    void drainStall(ThreadID tid);
254
255    /** Tells fetch to wake up from a quiesce instruction. */
256    void wakeFromQuiesce();
257
258    /** For priority-based fetch policies, need to keep update priorityList */
259    void deactivateThread(ThreadID tid);
260  private:
261    /** Reset this pipeline stage */
262    void resetStage();
263
264    /** Changes the status of this stage to active, and indicates this
265     * to the CPU.
266     */
267    inline void switchToActive();
268
269    /** Changes the status of this stage to inactive, and indicates
270     * this to the CPU.
271     */
272    inline void switchToInactive();
273
274    /**
275     * Looks up in the branch predictor to see if the next PC should be
276     * either next PC+=MachInst or a branch target.
277     * @param next_PC Next PC variable passed in by reference.  It is
278     * expected to be set to the current PC; it will be updated with what
279     * the next PC will be.
280     * @param next_NPC Used for ISAs which use delay slots.
281     * @return Whether or not a branch was predicted as taken.
282     */
283    bool lookupAndUpdateNextPC(DynInstPtr &inst, TheISA::PCState &pc);
284
285    /**
286     * Fetches the cache line that contains the fetch PC.  Returns any
287     * fault that happened.  Puts the data into the class variable
288     * fetchBuffer, which may not hold the entire fetched cache line.
289     * @param vaddr The memory address that is being fetched from.
290     * @param ret_fault The fault reference that will be set to the result of
291     * the icache access.
292     * @param tid Thread id.
293     * @param pc The actual PC of the current instruction.
294     * @return Any fault that occured.
295     */
296    bool fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc);
297    void finishTranslation(Fault fault, RequestPtr mem_req);
298
299
300    /** Check if an interrupt is pending and that we need to handle
301     */
302    bool
303    checkInterrupt(Addr pc)
304    {
305        return (interruptPending && (THE_ISA != ALPHA_ISA || !(pc & 0x3)));
306    }
307
308    /** Squashes a specific thread and resets the PC. */
309    inline void doSquash(const TheISA::PCState &newPC,
310                         const DynInstPtr squashInst, ThreadID tid);
311
312    /** Squashes a specific thread and resets the PC. Also tells the CPU to
313     * remove any instructions between fetch and decode that should be sqaushed.
314     */
315    void squashFromDecode(const TheISA::PCState &newPC,
316                          const DynInstPtr squashInst,
317                          const InstSeqNum seq_num, ThreadID tid);
318
319    /** Checks if a thread is stalled. */
320    bool checkStall(ThreadID tid) const;
321
322    /** Updates overall fetch stage status; to be called at the end of each
323     * cycle. */
324    FetchStatus updateFetchStatus();
325
326  public:
327    /** Squashes a specific thread and resets the PC. Also tells the CPU to
328     * remove any instructions that are not in the ROB. The source of this
329     * squash should be the commit stage.
330     */
331    void squash(const TheISA::PCState &newPC, const InstSeqNum seq_num,
332                DynInstPtr squashInst, ThreadID tid);
333
334    /** Ticks the fetch stage, processing all inputs signals and fetching
335     * as many instructions as possible.
336     */
337    void tick();
338
339    /** Checks all input signals and updates the status as necessary.
340     *  @return: Returns if the status has changed due to input signals.
341     */
342    bool checkSignalsAndUpdate(ThreadID tid);
343
344    /** Does the actual fetching of instructions and passing them on to the
345     * next stage.
346     * @param status_change fetch() sets this variable if there was a status
347     * change (ie switching to IcacheMissStall).
348     */
349    void fetch(bool &status_change);
350
351    /** Align a PC to the start of a fetch buffer block. */
352    Addr fetchBufferAlignPC(Addr addr)
353    {
354        return (addr & ~(fetchBufferMask));
355    }
356
357    /** The decoder. */
358    TheISA::Decoder *decoder[Impl::MaxThreads];
359
360  private:
361    DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst,
362                         StaticInstPtr curMacroop, TheISA::PCState thisPC,
363                         TheISA::PCState nextPC, bool trace);
364
365    /** Returns the appropriate thread to fetch, given the fetch policy. */
366    ThreadID getFetchingThread(FetchPriority &fetch_priority);
367
368    /** Returns the appropriate thread to fetch using a round robin policy. */
369    ThreadID roundRobin();
370
371    /** Returns the appropriate thread to fetch using the IQ count policy. */
372    ThreadID iqCount();
373
374    /** Returns the appropriate thread to fetch using the LSQ count policy. */
375    ThreadID lsqCount();
376
377    /** Returns the appropriate thread to fetch using the branch count
378     * policy. */
379    ThreadID branchCount();
380
381    /** Pipeline the next I-cache access to the current one. */
382    void pipelineIcacheAccesses(ThreadID tid);
383
384    /** Profile the reasons of fetch stall. */
385    void profileStall(ThreadID tid);
386
387  private:
388    /** Pointer to the O3CPU. */
389    O3CPU *cpu;
390
391    /** Time buffer interface. */
392    TimeBuffer<TimeStruct> *timeBuffer;
393
394    /** Wire to get decode's information from backwards time buffer. */
395    typename TimeBuffer<TimeStruct>::wire fromDecode;
396
397    /** Wire to get rename's information from backwards time buffer. */
398    typename TimeBuffer<TimeStruct>::wire fromRename;
399
400    /** Wire to get iew's information from backwards time buffer. */
401    typename TimeBuffer<TimeStruct>::wire fromIEW;
402
403    /** Wire to get commit's information from backwards time buffer. */
404    typename TimeBuffer<TimeStruct>::wire fromCommit;
405
406    //Might be annoying how this name is different than the queue.
407    /** Wire used to write any information heading to decode. */
408    typename TimeBuffer<FetchStruct>::wire toDecode;
409
410    /** BPredUnit. */
411    BPredUnit *branchPred;
412
413    TheISA::PCState pc[Impl::MaxThreads];
414
415    Addr fetchOffset[Impl::MaxThreads];
416
417    StaticInstPtr macroop[Impl::MaxThreads];
418
419    /** Can the fetch stage redirect from an interrupt on this instruction? */
420    bool delayedCommit[Impl::MaxThreads];
421
422    /** Memory request used to access cache. */
423    RequestPtr memReq[Impl::MaxThreads];
424
425    /** Variable that tracks if fetch has written to the time buffer this
426     * cycle. Used to tell CPU if there is activity this cycle.
427     */
428    bool wroteToTimeBuffer;
429
430    /** Tracks how many instructions has been fetched this cycle. */
431    int numInst;
432
433    /** Source of possible stalls. */
434    struct Stalls {
435        bool decode;
436        bool drain;
437    };
438
439    /** Tracks which stages are telling fetch to stall. */
440    Stalls stalls[Impl::MaxThreads];
441
442    /** Decode to fetch delay. */
443    Cycles decodeToFetchDelay;
444
445    /** Rename to fetch delay. */
446    Cycles renameToFetchDelay;
447
448    /** IEW to fetch delay. */
449    Cycles iewToFetchDelay;
450
451    /** Commit to fetch delay. */
452    Cycles commitToFetchDelay;
453
454    /** The width of fetch in instructions. */
455    unsigned fetchWidth;
456
457    /** The width of decode in instructions. */
458    unsigned decodeWidth;
459
460    /** Is the cache blocked?  If so no threads can access it. */
461    bool cacheBlocked;
462
463    /** The packet that is waiting to be retried. */
464    PacketPtr retryPkt;
465
466    /** The thread that is waiting on the cache to tell fetch to retry. */
467    ThreadID retryTid;
468
469    /** Cache block size. */
470    unsigned int cacheBlkSize;
471
472    /** The size of the fetch buffer in bytes. The fetch buffer
473     *  itself may be smaller than a cache line.
474     */
475    unsigned fetchBufferSize;
476
477    /** Mask to align a fetch address to a fetch buffer boundary. */
478    Addr fetchBufferMask;
479
480    /** The fetch data that is being fetched and buffered. */
481    uint8_t *fetchBuffer[Impl::MaxThreads];
482
483    /** The PC of the first instruction loaded into the fetch buffer. */
484    Addr fetchBufferPC[Impl::MaxThreads];
485
486    /** The size of the fetch queue in micro-ops */
487    unsigned fetchQueueSize;
488
489    /** Queue of fetched instructions. Per-thread to prevent HoL blocking. */
490    std::deque<DynInstPtr> fetchQueue[Impl::MaxThreads];
491
492    /** Whether or not the fetch buffer data is valid. */
493    bool fetchBufferValid[Impl::MaxThreads];
494
495    /** Size of instructions. */
496    int instSize;
497
498    /** Icache stall statistics. */
499    Counter lastIcacheStall[Impl::MaxThreads];
500
501    /** List of Active Threads */
502    std::list<ThreadID> *activeThreads;
503
504    /** Number of threads. */
505    ThreadID numThreads;
506
507    /** Number of threads that are actively fetching. */
508    ThreadID numFetchingThreads;
509
510    /** Thread ID being fetched. */
511    ThreadID threadFetched;
512
513    /** Checks if there is an interrupt pending.  If there is, fetch
514     * must stop once it is not fetching PAL instructions.
515     */
516    bool interruptPending;
517
518    /** Set to true if a pipelined I-cache request should be issued. */
519    bool issuePipelinedIfetch[Impl::MaxThreads];
520
521    /** Event used to delay fault generation of translation faults */
522    FinishTranslationEvent finishTranslationEvent;
523
524    // @todo: Consider making these vectors and tracking on a per thread basis.
525    /** Stat for total number of cycles stalled due to an icache miss. */
526    Stats::Scalar icacheStallCycles;
527    /** Stat for total number of fetched instructions. */
528    Stats::Scalar fetchedInsts;
529    /** Total number of fetched branches. */
530    Stats::Scalar fetchedBranches;
531    /** Stat for total number of predicted branches. */
532    Stats::Scalar predictedBranches;
533    /** Stat for total number of cycles spent fetching. */
534    Stats::Scalar fetchCycles;
535    /** Stat for total number of cycles spent squashing. */
536    Stats::Scalar fetchSquashCycles;
537    /** Stat for total number of cycles spent waiting for translation */
538    Stats::Scalar fetchTlbCycles;
539    /** Stat for total number of cycles spent blocked due to other stages in
540     * the pipeline.
541     */
542    Stats::Scalar fetchIdleCycles;
543    /** Total number of cycles spent blocked. */
544    Stats::Scalar fetchBlockedCycles;
545    /** Total number of cycles spent in any other state. */
546    Stats::Scalar fetchMiscStallCycles;
547    /** Total number of cycles spent in waiting for drains. */
548    Stats::Scalar fetchPendingDrainCycles;
549    /** Total number of stall cycles caused by no active threads to run. */
550    Stats::Scalar fetchNoActiveThreadStallCycles;
551    /** Total number of stall cycles caused by pending traps. */
552    Stats::Scalar fetchPendingTrapStallCycles;
553    /** Total number of stall cycles caused by pending quiesce instructions. */
554    Stats::Scalar fetchPendingQuiesceStallCycles;
555    /** Total number of stall cycles caused by I-cache wait retrys. */
556    Stats::Scalar fetchIcacheWaitRetryStallCycles;
557    /** Stat for total number of fetched cache lines. */
558    Stats::Scalar fetchedCacheLines;
559    /** Total number of outstanding icache accesses that were dropped
560     * due to a squash.
561     */
562    Stats::Scalar fetchIcacheSquashes;
563    /** Total number of outstanding tlb accesses that were dropped
564     * due to a squash.
565     */
566    Stats::Scalar fetchTlbSquashes;
567    /** Distribution of number of instructions fetched each cycle. */
568    Stats::Distribution fetchNisnDist;
569    /** Rate of how often fetch was idle. */
570    Stats::Formula idleRate;
571    /** Number of branch fetches per cycle. */
572    Stats::Formula branchRate;
573    /** Number of instruction fetched per cycle. */
574    Stats::Formula fetchRate;
575};
576
577#endif //__CPU_O3_FETCH_HH__
578