fetch.hh revision 10328:867b536a68be
1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 * Korey Sewell 42 */ 43 44#ifndef __CPU_O3_FETCH_HH__ 45#define __CPU_O3_FETCH_HH__ 46 47#include "arch/decoder.hh" 48#include "arch/utility.hh" 49#include "base/statistics.hh" 50#include "config/the_isa.hh" 51#include "cpu/pc_event.hh" 52#include "cpu/pred/bpred_unit.hh" 53#include "cpu/timebuf.hh" 54#include "cpu/translation.hh" 55#include "mem/packet.hh" 56#include "mem/port.hh" 57#include "sim/eventq.hh" 58#include "sim/probe/probe.hh" 59 60struct DerivO3CPUParams; 61 62/** 63 * DefaultFetch class handles both single threaded and SMT fetch. Its 64 * width is specified by the parameters; each cycle it tries to fetch 65 * that many instructions. It supports using a branch predictor to 66 * predict direction and targets. 67 * It supports the idling functionality of the CPU by indicating to 68 * the CPU when it is active and inactive. 69 */ 70template <class Impl> 71class DefaultFetch 72{ 73 public: 74 /** Typedefs from Impl. */ 75 typedef typename Impl::CPUPol CPUPol; 76 typedef typename Impl::DynInst DynInst; 77 typedef typename Impl::DynInstPtr DynInstPtr; 78 typedef typename Impl::O3CPU O3CPU; 79 80 /** Typedefs from the CPU policy. */ 81 typedef typename CPUPol::FetchStruct FetchStruct; 82 typedef typename CPUPol::TimeStruct TimeStruct; 83 84 /** Typedefs from ISA. */ 85 typedef TheISA::MachInst MachInst; 86 typedef TheISA::ExtMachInst ExtMachInst; 87 88 class FetchTranslation : public BaseTLB::Translation 89 { 90 protected: 91 DefaultFetch<Impl> *fetch; 92 93 public: 94 FetchTranslation(DefaultFetch<Impl> *_fetch) 95 : fetch(_fetch) 96 {} 97 98 void 99 markDelayed() 100 {} 101 102 void 103 finish(Fault fault, RequestPtr req, ThreadContext *tc, 104 BaseTLB::Mode mode) 105 { 106 assert(mode == BaseTLB::Execute); 107 fetch->finishTranslation(fault, req); 108 delete this; 109 } 110 }; 111 112 private: 113 /* Event to delay delivery of a fetch translation result in case of 114 * a fault and the nop to carry the fault cannot be generated 115 * immediately */ 116 class FinishTranslationEvent : public Event 117 { 118 private: 119 DefaultFetch<Impl> *fetch; 120 Fault fault; 121 RequestPtr req; 122 123 public: 124 FinishTranslationEvent(DefaultFetch<Impl> *_fetch) 125 : fetch(_fetch) 126 {} 127 128 void setFault(Fault _fault) 129 { 130 fault = _fault; 131 } 132 133 void setReq(RequestPtr _req) 134 { 135 req = _req; 136 } 137 138 /** Process the delayed finish translation */ 139 void process() 140 { 141 assert(fetch->numInst < fetch->fetchWidth); 142 fetch->finishTranslation(fault, req); 143 } 144 145 const char *description() const 146 { 147 return "FullO3CPU FetchFinishTranslation"; 148 } 149 }; 150 151 public: 152 /** Overall fetch status. Used to determine if the CPU can 153 * deschedule itsef due to a lack of activity. 154 */ 155 enum FetchStatus { 156 Active, 157 Inactive 158 }; 159 160 /** Individual thread status. */ 161 enum ThreadStatus { 162 Running, 163 Idle, 164 Squashing, 165 Blocked, 166 Fetching, 167 TrapPending, 168 QuiescePending, 169 ItlbWait, 170 IcacheWaitResponse, 171 IcacheWaitRetry, 172 IcacheAccessComplete, 173 NoGoodAddr 174 }; 175 176 /** Fetching Policy, Add new policies here.*/ 177 enum FetchPriority { 178 SingleThread, 179 RoundRobin, 180 Branch, 181 IQ, 182 LSQ 183 }; 184 185 private: 186 /** Fetch status. */ 187 FetchStatus _status; 188 189 /** Per-thread status. */ 190 ThreadStatus fetchStatus[Impl::MaxThreads]; 191 192 /** Fetch policy. */ 193 FetchPriority fetchPolicy; 194 195 /** List that has the threads organized by priority. */ 196 std::list<ThreadID> priorityList; 197 198 /** Probe points. */ 199 ProbePointArg<DynInstPtr> *ppFetch; 200 201 public: 202 /** DefaultFetch constructor. */ 203 DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params); 204 205 /** Returns the name of fetch. */ 206 std::string name() const; 207 208 /** Registers statistics. */ 209 void regStats(); 210 211 /** Registers probes. */ 212 void regProbePoints(); 213 214 /** Sets the main backwards communication time buffer pointer. */ 215 void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer); 216 217 /** Sets pointer to list of active threads. */ 218 void setActiveThreads(std::list<ThreadID> *at_ptr); 219 220 /** Sets pointer to time buffer used to communicate to the next stage. */ 221 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 222 223 /** Initialize stage. */ 224 void startupStage(); 225 226 /** Handles retrying the fetch access. */ 227 void recvRetry(); 228 229 /** Processes cache completion event. */ 230 void processCacheCompletion(PacketPtr pkt); 231 232 /** Resume after a drain. */ 233 void drainResume(); 234 235 /** Perform sanity checks after a drain. */ 236 void drainSanityCheck() const; 237 238 /** Has the stage drained? */ 239 bool isDrained() const; 240 241 /** Takes over from another CPU's thread. */ 242 void takeOverFrom(); 243 244 /** 245 * Stall the fetch stage after reaching a safe drain point. 246 * 247 * The CPU uses this method to stop fetching instructions from a 248 * thread that has been drained. The drain stall is different from 249 * all other stalls in that it is signaled instantly from the 250 * commit stage (without the normal communication delay) when it 251 * has reached a safe point to drain from. 252 */ 253 void drainStall(ThreadID tid); 254 255 /** Tells fetch to wake up from a quiesce instruction. */ 256 void wakeFromQuiesce(); 257 258 private: 259 /** Reset this pipeline stage */ 260 void resetStage(); 261 262 /** Changes the status of this stage to active, and indicates this 263 * to the CPU. 264 */ 265 inline void switchToActive(); 266 267 /** Changes the status of this stage to inactive, and indicates 268 * this to the CPU. 269 */ 270 inline void switchToInactive(); 271 272 /** 273 * Looks up in the branch predictor to see if the next PC should be 274 * either next PC+=MachInst or a branch target. 275 * @param next_PC Next PC variable passed in by reference. It is 276 * expected to be set to the current PC; it will be updated with what 277 * the next PC will be. 278 * @param next_NPC Used for ISAs which use delay slots. 279 * @return Whether or not a branch was predicted as taken. 280 */ 281 bool lookupAndUpdateNextPC(DynInstPtr &inst, TheISA::PCState &pc); 282 283 /** 284 * Fetches the cache line that contains the fetch PC. Returns any 285 * fault that happened. Puts the data into the class variable 286 * fetchBuffer, which may not hold the entire fetched cache line. 287 * @param vaddr The memory address that is being fetched from. 288 * @param ret_fault The fault reference that will be set to the result of 289 * the icache access. 290 * @param tid Thread id. 291 * @param pc The actual PC of the current instruction. 292 * @return Any fault that occured. 293 */ 294 bool fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc); 295 void finishTranslation(Fault fault, RequestPtr mem_req); 296 297 298 /** Check if an interrupt is pending and that we need to handle 299 */ 300 bool 301 checkInterrupt(Addr pc) 302 { 303 return (interruptPending && (THE_ISA != ALPHA_ISA || !(pc & 0x3))); 304 } 305 306 /** Squashes a specific thread and resets the PC. */ 307 inline void doSquash(const TheISA::PCState &newPC, 308 const DynInstPtr squashInst, ThreadID tid); 309 310 /** Squashes a specific thread and resets the PC. Also tells the CPU to 311 * remove any instructions between fetch and decode that should be sqaushed. 312 */ 313 void squashFromDecode(const TheISA::PCState &newPC, 314 const DynInstPtr squashInst, 315 const InstSeqNum seq_num, ThreadID tid); 316 317 /** Checks if a thread is stalled. */ 318 bool checkStall(ThreadID tid) const; 319 320 /** Updates overall fetch stage status; to be called at the end of each 321 * cycle. */ 322 FetchStatus updateFetchStatus(); 323 324 public: 325 /** Squashes a specific thread and resets the PC. Also tells the CPU to 326 * remove any instructions that are not in the ROB. The source of this 327 * squash should be the commit stage. 328 */ 329 void squash(const TheISA::PCState &newPC, const InstSeqNum seq_num, 330 DynInstPtr squashInst, ThreadID tid); 331 332 /** Ticks the fetch stage, processing all inputs signals and fetching 333 * as many instructions as possible. 334 */ 335 void tick(); 336 337 /** Checks all input signals and updates the status as necessary. 338 * @return: Returns if the status has changed due to input signals. 339 */ 340 bool checkSignalsAndUpdate(ThreadID tid); 341 342 /** Does the actual fetching of instructions and passing them on to the 343 * next stage. 344 * @param status_change fetch() sets this variable if there was a status 345 * change (ie switching to IcacheMissStall). 346 */ 347 void fetch(bool &status_change); 348 349 /** Align a PC to the start of a fetch buffer block. */ 350 Addr fetchBufferAlignPC(Addr addr) 351 { 352 return (addr & ~(fetchBufferMask)); 353 } 354 355 /** The decoder. */ 356 TheISA::Decoder *decoder[Impl::MaxThreads]; 357 358 private: 359 DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst, 360 StaticInstPtr curMacroop, TheISA::PCState thisPC, 361 TheISA::PCState nextPC, bool trace); 362 363 /** Returns the appropriate thread to fetch, given the fetch policy. */ 364 ThreadID getFetchingThread(FetchPriority &fetch_priority); 365 366 /** Returns the appropriate thread to fetch using a round robin policy. */ 367 ThreadID roundRobin(); 368 369 /** Returns the appropriate thread to fetch using the IQ count policy. */ 370 ThreadID iqCount(); 371 372 /** Returns the appropriate thread to fetch using the LSQ count policy. */ 373 ThreadID lsqCount(); 374 375 /** Returns the appropriate thread to fetch using the branch count 376 * policy. */ 377 ThreadID branchCount(); 378 379 /** Pipeline the next I-cache access to the current one. */ 380 void pipelineIcacheAccesses(ThreadID tid); 381 382 /** Profile the reasons of fetch stall. */ 383 void profileStall(ThreadID tid); 384 385 private: 386 /** Pointer to the O3CPU. */ 387 O3CPU *cpu; 388 389 /** Time buffer interface. */ 390 TimeBuffer<TimeStruct> *timeBuffer; 391 392 /** Wire to get decode's information from backwards time buffer. */ 393 typename TimeBuffer<TimeStruct>::wire fromDecode; 394 395 /** Wire to get rename's information from backwards time buffer. */ 396 typename TimeBuffer<TimeStruct>::wire fromRename; 397 398 /** Wire to get iew's information from backwards time buffer. */ 399 typename TimeBuffer<TimeStruct>::wire fromIEW; 400 401 /** Wire to get commit's information from backwards time buffer. */ 402 typename TimeBuffer<TimeStruct>::wire fromCommit; 403 404 /** Internal fetch instruction queue. */ 405 TimeBuffer<FetchStruct> *fetchQueue; 406 407 //Might be annoying how this name is different than the queue. 408 /** Wire used to write any information heading to decode. */ 409 typename TimeBuffer<FetchStruct>::wire toDecode; 410 411 /** BPredUnit. */ 412 BPredUnit *branchPred; 413 414 TheISA::PCState pc[Impl::MaxThreads]; 415 416 Addr fetchOffset[Impl::MaxThreads]; 417 418 StaticInstPtr macroop[Impl::MaxThreads]; 419 420 /** Can the fetch stage redirect from an interrupt on this instruction? */ 421 bool delayedCommit[Impl::MaxThreads]; 422 423 /** Memory request used to access cache. */ 424 RequestPtr memReq[Impl::MaxThreads]; 425 426 /** Variable that tracks if fetch has written to the time buffer this 427 * cycle. Used to tell CPU if there is activity this cycle. 428 */ 429 bool wroteToTimeBuffer; 430 431 /** Tracks how many instructions has been fetched this cycle. */ 432 int numInst; 433 434 /** Source of possible stalls. */ 435 struct Stalls { 436 bool decode; 437 bool drain; 438 }; 439 440 /** Tracks which stages are telling fetch to stall. */ 441 Stalls stalls[Impl::MaxThreads]; 442 443 /** Decode to fetch delay. */ 444 Cycles decodeToFetchDelay; 445 446 /** Rename to fetch delay. */ 447 Cycles renameToFetchDelay; 448 449 /** IEW to fetch delay. */ 450 Cycles iewToFetchDelay; 451 452 /** Commit to fetch delay. */ 453 Cycles commitToFetchDelay; 454 455 /** The width of fetch in instructions. */ 456 unsigned fetchWidth; 457 458 /** Is the cache blocked? If so no threads can access it. */ 459 bool cacheBlocked; 460 461 /** The packet that is waiting to be retried. */ 462 PacketPtr retryPkt; 463 464 /** The thread that is waiting on the cache to tell fetch to retry. */ 465 ThreadID retryTid; 466 467 /** Cache block size. */ 468 unsigned int cacheBlkSize; 469 470 /** The size of the fetch buffer in bytes. The fetch buffer 471 * itself may be smaller than a cache line. 472 */ 473 unsigned fetchBufferSize; 474 475 /** Mask to align a fetch address to a fetch buffer boundary. */ 476 Addr fetchBufferMask; 477 478 /** The fetch data that is being fetched and buffered. */ 479 uint8_t *fetchBuffer[Impl::MaxThreads]; 480 481 /** The PC of the first instruction loaded into the fetch buffer. */ 482 Addr fetchBufferPC[Impl::MaxThreads]; 483 484 /** Whether or not the fetch buffer data is valid. */ 485 bool fetchBufferValid[Impl::MaxThreads]; 486 487 /** Size of instructions. */ 488 int instSize; 489 490 /** Icache stall statistics. */ 491 Counter lastIcacheStall[Impl::MaxThreads]; 492 493 /** List of Active Threads */ 494 std::list<ThreadID> *activeThreads; 495 496 /** Number of threads. */ 497 ThreadID numThreads; 498 499 /** Number of threads that are actively fetching. */ 500 ThreadID numFetchingThreads; 501 502 /** Thread ID being fetched. */ 503 ThreadID threadFetched; 504 505 /** Checks if there is an interrupt pending. If there is, fetch 506 * must stop once it is not fetching PAL instructions. 507 */ 508 bool interruptPending; 509 510 /** Set to true if a pipelined I-cache request should be issued. */ 511 bool issuePipelinedIfetch[Impl::MaxThreads]; 512 513 /** Event used to delay fault generation of translation faults */ 514 FinishTranslationEvent finishTranslationEvent; 515 516 // @todo: Consider making these vectors and tracking on a per thread basis. 517 /** Stat for total number of cycles stalled due to an icache miss. */ 518 Stats::Scalar icacheStallCycles; 519 /** Stat for total number of fetched instructions. */ 520 Stats::Scalar fetchedInsts; 521 /** Total number of fetched branches. */ 522 Stats::Scalar fetchedBranches; 523 /** Stat for total number of predicted branches. */ 524 Stats::Scalar predictedBranches; 525 /** Stat for total number of cycles spent fetching. */ 526 Stats::Scalar fetchCycles; 527 /** Stat for total number of cycles spent squashing. */ 528 Stats::Scalar fetchSquashCycles; 529 /** Stat for total number of cycles spent waiting for translation */ 530 Stats::Scalar fetchTlbCycles; 531 /** Stat for total number of cycles spent blocked due to other stages in 532 * the pipeline. 533 */ 534 Stats::Scalar fetchIdleCycles; 535 /** Total number of cycles spent blocked. */ 536 Stats::Scalar fetchBlockedCycles; 537 /** Total number of cycles spent in any other state. */ 538 Stats::Scalar fetchMiscStallCycles; 539 /** Total number of cycles spent in waiting for drains. */ 540 Stats::Scalar fetchPendingDrainCycles; 541 /** Total number of stall cycles caused by no active threads to run. */ 542 Stats::Scalar fetchNoActiveThreadStallCycles; 543 /** Total number of stall cycles caused by pending traps. */ 544 Stats::Scalar fetchPendingTrapStallCycles; 545 /** Total number of stall cycles caused by pending quiesce instructions. */ 546 Stats::Scalar fetchPendingQuiesceStallCycles; 547 /** Total number of stall cycles caused by I-cache wait retrys. */ 548 Stats::Scalar fetchIcacheWaitRetryStallCycles; 549 /** Stat for total number of fetched cache lines. */ 550 Stats::Scalar fetchedCacheLines; 551 /** Total number of outstanding icache accesses that were dropped 552 * due to a squash. 553 */ 554 Stats::Scalar fetchIcacheSquashes; 555 /** Total number of outstanding tlb accesses that were dropped 556 * due to a squash. 557 */ 558 Stats::Scalar fetchTlbSquashes; 559 /** Distribution of number of instructions fetched each cycle. */ 560 Stats::Distribution fetchNisnDist; 561 /** Rate of how often fetch was idle. */ 562 Stats::Formula idleRate; 563 /** Number of branch fetches per cycle. */ 564 Stats::Formula branchRate; 565 /** Number of instruction fetched per cycle. */ 566 Stats::Formula fetchRate; 567}; 568 569#endif //__CPU_O3_FETCH_HH__ 570