dyn_inst_impl.hh revision 9527
11689SN/A/* 28733Sgeoffrey.blake@arm.com * Copyright (c) 2010-2011 ARM Limited 37783SGiacomo.Gabrielli@arm.com * All rights reserved 47783SGiacomo.Gabrielli@arm.com * 57783SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 67783SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 77783SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 87783SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 97783SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 107783SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 117783SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 127783SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 137783SGiacomo.Gabrielli@arm.com * 142316SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665SN/A * 402665SN/A * Authors: Kevin Lim 411689SN/A */ 421061SN/A 435953Ssaidi@eecs.umich.edu#include "base/cp_annotate.hh" 445596Sgblack@eecs.umich.edu#include "cpu/o3/dyn_inst.hh" 458779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 469252Sdjordje.kovacevic@arm.com#include "debug/O3PipeView.hh" 471061SN/A 481061SN/Atemplate <class Impl> 495596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr staticInst, 508502Sgblack@eecs.umich.edu StaticInstPtr macroop, 517720Sgblack@eecs.umich.edu TheISA::PCState pc, TheISA::PCState predPC, 525596Sgblack@eecs.umich.edu InstSeqNum seq_num, O3CPU *cpu) 538502Sgblack@eecs.umich.edu : BaseDynInst<Impl>(staticInst, macroop, pc, predPC, seq_num, cpu) 544637SN/A{ 554637SN/A initVars(); 564637SN/A} 574637SN/A 584637SN/Atemplate <class Impl> 598502Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr _staticInst, 608502Sgblack@eecs.umich.edu StaticInstPtr _macroop) 618502Sgblack@eecs.umich.edu : BaseDynInst<Impl>(_staticInst, _macroop) 621061SN/A{ 632292SN/A initVars(); 642292SN/A} 652292SN/A 669252Sdjordje.kovacevic@arm.comtemplate <class Impl>BaseO3DynInst<Impl>::~BaseO3DynInst() 679252Sdjordje.kovacevic@arm.com{ 689252Sdjordje.kovacevic@arm.com#if TRACING_ON 699527SMatt.Horsnell@arm.com if (DTRACE(O3PipeView)) { 709527SMatt.Horsnell@arm.com Tick fetch = this->fetchTick; 719527SMatt.Horsnell@arm.com // fetchTick can be -1 if the instruction fetched outside the trace window. 729527SMatt.Horsnell@arm.com if (fetch != -1) { 739527SMatt.Horsnell@arm.com Tick val; 749527SMatt.Horsnell@arm.com // Print info needed by the pipeline activity viewer. 759527SMatt.Horsnell@arm.com DPRINTFR(O3PipeView, "O3PipeView:fetch:%llu:0x%08llx:%d:%llu:%s\n", 769527SMatt.Horsnell@arm.com fetch, 779527SMatt.Horsnell@arm.com this->instAddr(), 789527SMatt.Horsnell@arm.com this->microPC(), 799527SMatt.Horsnell@arm.com this->seqNum, 809527SMatt.Horsnell@arm.com this->staticInst->disassemble(this->instAddr())); 819527SMatt.Horsnell@arm.com 829527SMatt.Horsnell@arm.com val = (this->decodeTick == -1) ? 0 : fetch + this->decodeTick; 839527SMatt.Horsnell@arm.com DPRINTFR(O3PipeView, "O3PipeView:decode:%llu\n", val); 849527SMatt.Horsnell@arm.com val = (this->renameTick == -1) ? 0 : fetch + this->renameTick; 859527SMatt.Horsnell@arm.com DPRINTFR(O3PipeView, "O3PipeView:rename:%llu\n", val); 869527SMatt.Horsnell@arm.com val = (this->dispatchTick == -1) ? 0 : fetch + this->dispatchTick; 879527SMatt.Horsnell@arm.com DPRINTFR(O3PipeView, "O3PipeView:dispatch:%llu\n", val); 889527SMatt.Horsnell@arm.com val = (this->issueTick == -1) ? 0 : fetch + this->issueTick; 899527SMatt.Horsnell@arm.com DPRINTFR(O3PipeView, "O3PipeView:issue:%llu\n", val); 909527SMatt.Horsnell@arm.com val = (this->completeTick == -1) ? 0 : fetch + this->completeTick; 919527SMatt.Horsnell@arm.com DPRINTFR(O3PipeView, "O3PipeView:complete:%llu\n", val); 929527SMatt.Horsnell@arm.com val = (this->commitTick == -1) ? 0 : fetch + this->commitTick; 939527SMatt.Horsnell@arm.com 949527SMatt.Horsnell@arm.com Tick valS = (this->storeTick == -1) ? 0 : fetch + this->storeTick; 959527SMatt.Horsnell@arm.com DPRINTFR(O3PipeView, "O3PipeView:retire:%llu:store:%llu\n", val, valS); 969527SMatt.Horsnell@arm.com } 979527SMatt.Horsnell@arm.com } 989252Sdjordje.kovacevic@arm.com#endif 999252Sdjordje.kovacevic@arm.com}; 1009252Sdjordje.kovacevic@arm.com 1019252Sdjordje.kovacevic@arm.com 1022292SN/Atemplate <class Impl> 1032292SN/Avoid 1045596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::initVars() 1052292SN/A{ 1061464SN/A // Make sure to have the renamed register entries set to the same 1071464SN/A // as the normal register entries. It will allow the IQ to work 1081464SN/A // without any modifications. 1092292SN/A for (int i = 0; i < this->staticInst->numDestRegs(); i++) { 1103782SN/A this->_destRegIdx[i] = this->staticInst->destRegIdx(i); 1111464SN/A } 1121464SN/A 1132292SN/A for (int i = 0; i < this->staticInst->numSrcRegs(); i++) { 1143782SN/A this->_srcRegIdx[i] = this->staticInst->srcRegIdx(i); 1151464SN/A } 1167783SGiacomo.Gabrielli@arm.com 1179046SAli.Saidi@ARM.com this->_readySrcRegIdx.reset(); 1189046SAli.Saidi@ARM.com 1197783SGiacomo.Gabrielli@arm.com _numDestMiscRegs = 0; 1208471SGiacomo.Gabrielli@arm.com 1218471SGiacomo.Gabrielli@arm.com#if TRACING_ON 1229252Sdjordje.kovacevic@arm.com // Value -1 indicates that particular phase 1239252Sdjordje.kovacevic@arm.com // hasn't happened (yet). 1249252Sdjordje.kovacevic@arm.com fetchTick = -1; 1259252Sdjordje.kovacevic@arm.com decodeTick = -1; 1269252Sdjordje.kovacevic@arm.com renameTick = -1; 1279252Sdjordje.kovacevic@arm.com dispatchTick = -1; 1289252Sdjordje.kovacevic@arm.com issueTick = -1; 1299252Sdjordje.kovacevic@arm.com completeTick = -1; 1309252Sdjordje.kovacevic@arm.com commitTick = -1; 1319527SMatt.Horsnell@arm.com storeTick = -1; 1328471SGiacomo.Gabrielli@arm.com#endif 1331061SN/A} 1341061SN/A 1352292SN/Atemplate <class Impl> 1362292SN/AFault 1375596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::execute() 1382292SN/A{ 1392348SN/A // @todo: Pretty convoluted way to avoid squashing from happening 1402680SN/A // when using the TC during an instruction's execution 1412348SN/A // (specifically for instructions that have side-effects that use 1422680SN/A // the TC). Fix this. 1439382SAli.Saidi@ARM.com bool no_squash_from_TC = this->thread->noSquashFromTC; 1449382SAli.Saidi@ARM.com this->thread->noSquashFromTC = true; 1452292SN/A 1462292SN/A this->fault = this->staticInst->execute(this, this->traceData); 1472292SN/A 1489382SAli.Saidi@ARM.com this->thread->noSquashFromTC = no_squash_from_TC; 1492292SN/A 1502292SN/A return this->fault; 1512292SN/A} 1522292SN/A 1532292SN/Atemplate <class Impl> 1542292SN/AFault 1555596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::initiateAcc() 1562292SN/A{ 1572348SN/A // @todo: Pretty convoluted way to avoid squashing from happening 1582680SN/A // when using the TC during an instruction's execution 1592348SN/A // (specifically for instructions that have side-effects that use 1602680SN/A // the TC). Fix this. 1619382SAli.Saidi@ARM.com bool no_squash_from_TC = this->thread->noSquashFromTC; 1629382SAli.Saidi@ARM.com this->thread->noSquashFromTC = true; 1632292SN/A 1642292SN/A this->fault = this->staticInst->initiateAcc(this, this->traceData); 1652292SN/A 1669382SAli.Saidi@ARM.com this->thread->noSquashFromTC = no_squash_from_TC; 1672292SN/A 1682292SN/A return this->fault; 1692292SN/A} 1702292SN/A 1712292SN/Atemplate <class Impl> 1722292SN/AFault 1735596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::completeAcc(PacketPtr pkt) 1742292SN/A{ 1757758Sminkyu.jeong@arm.com // @todo: Pretty convoluted way to avoid squashing from happening 1767758Sminkyu.jeong@arm.com // when using the TC during an instruction's execution 1777758Sminkyu.jeong@arm.com // (specifically for instructions that have side-effects that use 1787758Sminkyu.jeong@arm.com // the TC). Fix this. 1799382SAli.Saidi@ARM.com bool no_squash_from_TC = this->thread->noSquashFromTC; 1809382SAli.Saidi@ARM.com this->thread->noSquashFromTC = true; 1817758Sminkyu.jeong@arm.com 1828887Sgeoffrey.blake@arm.com if (this->cpu->checker) { 1838887Sgeoffrey.blake@arm.com if (this->isStoreConditional()) { 1848887Sgeoffrey.blake@arm.com this->reqToVerify->setExtraData(pkt->req->getExtraData()); 1858887Sgeoffrey.blake@arm.com } 1868733Sgeoffrey.blake@arm.com } 1878887Sgeoffrey.blake@arm.com 1882790SN/A this->fault = this->staticInst->completeAcc(pkt, this, this->traceData); 1892292SN/A 1909382SAli.Saidi@ARM.com this->thread->noSquashFromTC = no_squash_from_TC; 1917758Sminkyu.jeong@arm.com 1922292SN/A return this->fault; 1932292SN/A} 1942292SN/A 1951061SN/Atemplate <class Impl> 1965702Ssaidi@eecs.umich.eduFault 1975702Ssaidi@eecs.umich.eduBaseO3DynInst<Impl>::hwrei() 1985702Ssaidi@eecs.umich.edu{ 1995702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 2005702Ssaidi@eecs.umich.edu // Can only do a hwrei when in pal mode. 2017720Sgblack@eecs.umich.edu if (!(this->instAddr() & 0x3)) 2025702Ssaidi@eecs.umich.edu return new AlphaISA::UnimplementedOpcodeFault; 2035702Ssaidi@eecs.umich.edu 2045702Ssaidi@eecs.umich.edu // Set the next PC based on the value of the EXC_ADDR IPR. 2057720Sgblack@eecs.umich.edu AlphaISA::PCState pc = this->pcState(); 2067720Sgblack@eecs.umich.edu pc.npc(this->cpu->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR, 2077720Sgblack@eecs.umich.edu this->threadNumber)); 2087720Sgblack@eecs.umich.edu this->pcState(pc); 2095953Ssaidi@eecs.umich.edu if (CPA::available()) { 2105953Ssaidi@eecs.umich.edu ThreadContext *tc = this->cpu->tcBase(this->threadNumber); 2117720Sgblack@eecs.umich.edu CPA::cpa()->swAutoBegin(tc, this->nextInstAddr()); 2125953Ssaidi@eecs.umich.edu } 2135702Ssaidi@eecs.umich.edu 2145702Ssaidi@eecs.umich.edu // Tell CPU to clear any state it needs to if a hwrei is taken. 2155702Ssaidi@eecs.umich.edu this->cpu->hwrei(this->threadNumber); 2165702Ssaidi@eecs.umich.edu#else 2175702Ssaidi@eecs.umich.edu 2185702Ssaidi@eecs.umich.edu#endif 2195702Ssaidi@eecs.umich.edu // FIXME: XXX check for interrupts? XXX 2205702Ssaidi@eecs.umich.edu return NoFault; 2215702Ssaidi@eecs.umich.edu} 2225702Ssaidi@eecs.umich.edu 2235702Ssaidi@eecs.umich.edutemplate <class Impl> 2241061SN/Avoid 2255596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::trap(Fault fault) 2261061SN/A{ 2277684Sgblack@eecs.umich.edu this->cpu->trap(fault, this->threadNumber, this->staticInst); 2281061SN/A} 2295702Ssaidi@eecs.umich.edu 2305702Ssaidi@eecs.umich.edutemplate <class Impl> 2315702Ssaidi@eecs.umich.edubool 2325702Ssaidi@eecs.umich.eduBaseO3DynInst<Impl>::simPalCheck(int palFunc) 2335702Ssaidi@eecs.umich.edu{ 2345702Ssaidi@eecs.umich.edu#if THE_ISA != ALPHA_ISA 2355702Ssaidi@eecs.umich.edu panic("simPalCheck called, but PAL only exists in Alpha!\n"); 2365702Ssaidi@eecs.umich.edu#endif 2375702Ssaidi@eecs.umich.edu return this->cpu->simPalCheck(palFunc, this->threadNumber); 2385702Ssaidi@eecs.umich.edu} 2398557Sgblack@eecs.umich.edu 2401061SN/Atemplate <class Impl> 2411061SN/Avoid 2425596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::syscall(int64_t callnum) 2431061SN/A{ 2448806Sgblack@eecs.umich.edu if (FullSystem) 2458779Sgblack@eecs.umich.edu panic("Syscall emulation isn't available in FS mode.\n"); 2468806Sgblack@eecs.umich.edu 2475556SN/A // HACK: check CPU's nextPC before and after syscall. If it 2485556SN/A // changes, update this instruction's nextPC because the syscall 2495556SN/A // must have changed the nextPC. 2507720Sgblack@eecs.umich.edu TheISA::PCState curPC = this->cpu->pcState(this->threadNumber); 2512669SN/A this->cpu->syscall(callnum, this->threadNumber); 2527720Sgblack@eecs.umich.edu TheISA::PCState newPC = this->cpu->pcState(this->threadNumber); 2537720Sgblack@eecs.umich.edu if (!(curPC == newPC)) { 2547720Sgblack@eecs.umich.edu this->pcState(newPC); 2555556SN/A } 2561061SN/A} 2571061SN/A 258