dyn_inst_impl.hh revision 8887
11689SN/A/* 28733Sgeoffrey.blake@arm.com * Copyright (c) 2010-2011 ARM Limited 37783SGiacomo.Gabrielli@arm.com * All rights reserved 47783SGiacomo.Gabrielli@arm.com * 57783SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 67783SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 77783SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 87783SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 97783SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 107783SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 117783SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 127783SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 137783SGiacomo.Gabrielli@arm.com * 142316SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665SN/A * 402665SN/A * Authors: Kevin Lim 411689SN/A */ 421061SN/A 435953Ssaidi@eecs.umich.edu#include "base/cp_annotate.hh" 445596Sgblack@eecs.umich.edu#include "cpu/o3/dyn_inst.hh" 458779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 461061SN/A 471061SN/Atemplate <class Impl> 485596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr staticInst, 498502Sgblack@eecs.umich.edu StaticInstPtr macroop, 507720Sgblack@eecs.umich.edu TheISA::PCState pc, TheISA::PCState predPC, 515596Sgblack@eecs.umich.edu InstSeqNum seq_num, O3CPU *cpu) 528502Sgblack@eecs.umich.edu : BaseDynInst<Impl>(staticInst, macroop, pc, predPC, seq_num, cpu) 534637SN/A{ 544637SN/A initVars(); 554637SN/A} 564637SN/A 574637SN/Atemplate <class Impl> 588502Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr _staticInst, 598502Sgblack@eecs.umich.edu StaticInstPtr _macroop) 608502Sgblack@eecs.umich.edu : BaseDynInst<Impl>(_staticInst, _macroop) 611061SN/A{ 622292SN/A initVars(); 632292SN/A} 642292SN/A 652292SN/Atemplate <class Impl> 662292SN/Avoid 675596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::initVars() 682292SN/A{ 691464SN/A // Make sure to have the renamed register entries set to the same 701464SN/A // as the normal register entries. It will allow the IQ to work 711464SN/A // without any modifications. 722292SN/A for (int i = 0; i < this->staticInst->numDestRegs(); i++) { 733782SN/A this->_destRegIdx[i] = this->staticInst->destRegIdx(i); 741464SN/A } 751464SN/A 762292SN/A for (int i = 0; i < this->staticInst->numSrcRegs(); i++) { 773782SN/A this->_srcRegIdx[i] = this->staticInst->srcRegIdx(i); 782292SN/A this->_readySrcRegIdx[i] = 0; 791464SN/A } 807783SGiacomo.Gabrielli@arm.com 817783SGiacomo.Gabrielli@arm.com _numDestMiscRegs = 0; 828471SGiacomo.Gabrielli@arm.com 838471SGiacomo.Gabrielli@arm.com#if TRACING_ON 848471SGiacomo.Gabrielli@arm.com fetchTick = 0; 858471SGiacomo.Gabrielli@arm.com decodeTick = 0; 868471SGiacomo.Gabrielli@arm.com renameTick = 0; 878471SGiacomo.Gabrielli@arm.com dispatchTick = 0; 888471SGiacomo.Gabrielli@arm.com issueTick = 0; 898471SGiacomo.Gabrielli@arm.com completeTick = 0; 908471SGiacomo.Gabrielli@arm.com#endif 911061SN/A} 921061SN/A 932292SN/Atemplate <class Impl> 942292SN/AFault 955596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::execute() 962292SN/A{ 972348SN/A // @todo: Pretty convoluted way to avoid squashing from happening 982680SN/A // when using the TC during an instruction's execution 992348SN/A // (specifically for instructions that have side-effects that use 1002680SN/A // the TC). Fix this. 1012292SN/A bool in_syscall = this->thread->inSyscall; 1022292SN/A this->thread->inSyscall = true; 1032292SN/A 1042292SN/A this->fault = this->staticInst->execute(this, this->traceData); 1052292SN/A 1062292SN/A this->thread->inSyscall = in_syscall; 1072292SN/A 1082292SN/A return this->fault; 1092292SN/A} 1102292SN/A 1112292SN/Atemplate <class Impl> 1122292SN/AFault 1135596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::initiateAcc() 1142292SN/A{ 1152348SN/A // @todo: Pretty convoluted way to avoid squashing from happening 1162680SN/A // when using the TC during an instruction's execution 1172348SN/A // (specifically for instructions that have side-effects that use 1182680SN/A // the TC). Fix this. 1192292SN/A bool in_syscall = this->thread->inSyscall; 1202292SN/A this->thread->inSyscall = true; 1212292SN/A 1222292SN/A this->fault = this->staticInst->initiateAcc(this, this->traceData); 1232292SN/A 1242292SN/A this->thread->inSyscall = in_syscall; 1252292SN/A 1262292SN/A return this->fault; 1272292SN/A} 1282292SN/A 1292292SN/Atemplate <class Impl> 1302292SN/AFault 1315596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::completeAcc(PacketPtr pkt) 1322292SN/A{ 1337758Sminkyu.jeong@arm.com // @todo: Pretty convoluted way to avoid squashing from happening 1347758Sminkyu.jeong@arm.com // when using the TC during an instruction's execution 1357758Sminkyu.jeong@arm.com // (specifically for instructions that have side-effects that use 1367758Sminkyu.jeong@arm.com // the TC). Fix this. 1377758Sminkyu.jeong@arm.com bool in_syscall = this->thread->inSyscall; 1387758Sminkyu.jeong@arm.com this->thread->inSyscall = true; 1397758Sminkyu.jeong@arm.com 1408887Sgeoffrey.blake@arm.com if (this->cpu->checker) { 1418887Sgeoffrey.blake@arm.com if (this->isStoreConditional()) { 1428887Sgeoffrey.blake@arm.com this->reqToVerify->setExtraData(pkt->req->getExtraData()); 1438887Sgeoffrey.blake@arm.com } 1448733Sgeoffrey.blake@arm.com } 1458887Sgeoffrey.blake@arm.com 1462790SN/A this->fault = this->staticInst->completeAcc(pkt, this, this->traceData); 1472292SN/A 1487758Sminkyu.jeong@arm.com this->thread->inSyscall = in_syscall; 1497758Sminkyu.jeong@arm.com 1502292SN/A return this->fault; 1512292SN/A} 1522292SN/A 1531061SN/Atemplate <class Impl> 1545702Ssaidi@eecs.umich.eduFault 1555702Ssaidi@eecs.umich.eduBaseO3DynInst<Impl>::hwrei() 1565702Ssaidi@eecs.umich.edu{ 1575702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 1585702Ssaidi@eecs.umich.edu // Can only do a hwrei when in pal mode. 1597720Sgblack@eecs.umich.edu if (!(this->instAddr() & 0x3)) 1605702Ssaidi@eecs.umich.edu return new AlphaISA::UnimplementedOpcodeFault; 1615702Ssaidi@eecs.umich.edu 1625702Ssaidi@eecs.umich.edu // Set the next PC based on the value of the EXC_ADDR IPR. 1637720Sgblack@eecs.umich.edu AlphaISA::PCState pc = this->pcState(); 1647720Sgblack@eecs.umich.edu pc.npc(this->cpu->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR, 1657720Sgblack@eecs.umich.edu this->threadNumber)); 1667720Sgblack@eecs.umich.edu this->pcState(pc); 1675953Ssaidi@eecs.umich.edu if (CPA::available()) { 1685953Ssaidi@eecs.umich.edu ThreadContext *tc = this->cpu->tcBase(this->threadNumber); 1697720Sgblack@eecs.umich.edu CPA::cpa()->swAutoBegin(tc, this->nextInstAddr()); 1705953Ssaidi@eecs.umich.edu } 1715702Ssaidi@eecs.umich.edu 1725702Ssaidi@eecs.umich.edu // Tell CPU to clear any state it needs to if a hwrei is taken. 1735702Ssaidi@eecs.umich.edu this->cpu->hwrei(this->threadNumber); 1745702Ssaidi@eecs.umich.edu#else 1755702Ssaidi@eecs.umich.edu 1765702Ssaidi@eecs.umich.edu#endif 1775702Ssaidi@eecs.umich.edu // FIXME: XXX check for interrupts? XXX 1785702Ssaidi@eecs.umich.edu return NoFault; 1795702Ssaidi@eecs.umich.edu} 1805702Ssaidi@eecs.umich.edu 1815702Ssaidi@eecs.umich.edutemplate <class Impl> 1821061SN/Avoid 1835596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::trap(Fault fault) 1841061SN/A{ 1857684Sgblack@eecs.umich.edu this->cpu->trap(fault, this->threadNumber, this->staticInst); 1861061SN/A} 1875702Ssaidi@eecs.umich.edu 1885702Ssaidi@eecs.umich.edutemplate <class Impl> 1895702Ssaidi@eecs.umich.edubool 1905702Ssaidi@eecs.umich.eduBaseO3DynInst<Impl>::simPalCheck(int palFunc) 1915702Ssaidi@eecs.umich.edu{ 1925702Ssaidi@eecs.umich.edu#if THE_ISA != ALPHA_ISA 1935702Ssaidi@eecs.umich.edu panic("simPalCheck called, but PAL only exists in Alpha!\n"); 1945702Ssaidi@eecs.umich.edu#endif 1955702Ssaidi@eecs.umich.edu return this->cpu->simPalCheck(palFunc, this->threadNumber); 1965702Ssaidi@eecs.umich.edu} 1978557Sgblack@eecs.umich.edu 1981061SN/Atemplate <class Impl> 1991061SN/Avoid 2005596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::syscall(int64_t callnum) 2011061SN/A{ 2028806Sgblack@eecs.umich.edu if (FullSystem) 2038779Sgblack@eecs.umich.edu panic("Syscall emulation isn't available in FS mode.\n"); 2048806Sgblack@eecs.umich.edu 2055556SN/A // HACK: check CPU's nextPC before and after syscall. If it 2065556SN/A // changes, update this instruction's nextPC because the syscall 2075556SN/A // must have changed the nextPC. 2087720Sgblack@eecs.umich.edu TheISA::PCState curPC = this->cpu->pcState(this->threadNumber); 2092669SN/A this->cpu->syscall(callnum, this->threadNumber); 2107720Sgblack@eecs.umich.edu TheISA::PCState newPC = this->cpu->pcState(this->threadNumber); 2117720Sgblack@eecs.umich.edu if (!(curPC == newPC)) { 2127720Sgblack@eecs.umich.edu this->pcState(newPC); 2135556SN/A } 2141061SN/A} 2151061SN/A 216