dyn_inst_impl.hh revision 7783
110263Satgutier@umich.edu/* 212566Snikos.nikoleris@arm.com * Copyright (c) 2010 ARM Limited 310263Satgutier@umich.edu * All rights reserved 410263Satgutier@umich.edu * 510263Satgutier@umich.edu * The license below extends only to copyright in the software and shall 610263Satgutier@umich.edu * not be construed as granting a license to any other intellectual 710263Satgutier@umich.edu * property including but not limited to intellectual property relating 810263Satgutier@umich.edu * to a hardware implementation of the functionality of the software 910263Satgutier@umich.edu * licensed hereunder. You may use the software subject to the license 1010263Satgutier@umich.edu * terms below provided that you ensure that this notice is replicated 1110263Satgutier@umich.edu * unmodified and in its entirety in all distributions of the software, 1210263Satgutier@umich.edu * modified or unmodified, in source code or in binary form. 1310263Satgutier@umich.edu * 1410263Satgutier@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 1510263Satgutier@umich.edu * All rights reserved. 1610263Satgutier@umich.edu * 1710263Satgutier@umich.edu * Redistribution and use in source and binary forms, with or without 1810263Satgutier@umich.edu * modification, are permitted provided that the following conditions are 1910263Satgutier@umich.edu * met: redistributions of source code must retain the above copyright 2010263Satgutier@umich.edu * notice, this list of conditions and the following disclaimer; 2110263Satgutier@umich.edu * redistributions in binary form must reproduce the above copyright 2210263Satgutier@umich.edu * notice, this list of conditions and the following disclaimer in the 2310263Satgutier@umich.edu * documentation and/or other materials provided with the distribution; 2410263Satgutier@umich.edu * neither the name of the copyright holders nor the names of its 2510263Satgutier@umich.edu * contributors may be used to endorse or promote products derived from 2610263Satgutier@umich.edu * this software without specific prior written permission. 2710263Satgutier@umich.edu * 2810263Satgutier@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2910263Satgutier@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3010263Satgutier@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3110263Satgutier@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3210263Satgutier@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3310263Satgutier@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3410263Satgutier@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3510263Satgutier@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3610263Satgutier@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3710263Satgutier@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3810263Satgutier@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3910263Satgutier@umich.edu * 4010263Satgutier@umich.edu * Authors: Kevin Lim 4110263Satgutier@umich.edu */ 4210263Satgutier@umich.edu 4310263Satgutier@umich.edu#include "base/cp_annotate.hh" 4410263Satgutier@umich.edu#include "cpu/o3/dyn_inst.hh" 4510263Satgutier@umich.edu 4610263Satgutier@umich.edutemplate <class Impl> 4710263Satgutier@umich.eduBaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr staticInst, 4812492Sodanrc@yahoo.com.br TheISA::PCState pc, TheISA::PCState predPC, 4912492Sodanrc@yahoo.com.br InstSeqNum seq_num, O3CPU *cpu) 5010263Satgutier@umich.edu : BaseDynInst<Impl>(staticInst, pc, predPC, seq_num, cpu) 5113941Sodanrc@yahoo.com.br{ 5212728Snikos.nikoleris@arm.com initVars(); 5312727Snikos.nikoleris@arm.com} 5412548Sodanrc@yahoo.com.br 5510263Satgutier@umich.edutemplate <class Impl> 5612727Snikos.nikoleris@arm.comBaseO3DynInst<Impl>::BaseO3DynInst(ExtMachInst inst, 5712727Snikos.nikoleris@arm.com TheISA::PCState pc, TheISA::PCState predPC, 5811486Snikos.nikoleris@arm.com InstSeqNum seq_num, O3CPU *cpu) 5913223Sodanrc@yahoo.com.br : BaseDynInst<Impl>(inst, pc, predPC, seq_num, cpu) 6012684Sodanrc@yahoo.com.br{ 6113225Sodanrc@yahoo.com.br initVars(); 6210263Satgutier@umich.edu} 6313219Sodanrc@yahoo.com.br 6413752Sodanrc@yahoo.com.brtemplate <class Impl> 6510263Satgutier@umich.eduBaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr &_staticInst) 6610263Satgutier@umich.edu : BaseDynInst<Impl>(_staticInst) 6710263Satgutier@umich.edu{ 6813219Sodanrc@yahoo.com.br initVars(); 6910263Satgutier@umich.edu} 7010263Satgutier@umich.edu 7112600Sodanrc@yahoo.com.brtemplate <class Impl> 7213219Sodanrc@yahoo.com.brvoid 7310263Satgutier@umich.eduBaseO3DynInst<Impl>::initVars() 7410263Satgutier@umich.edu{ 7510263Satgutier@umich.edu // Make sure to have the renamed register entries set to the same 7610263Satgutier@umich.edu // as the normal register entries. It will allow the IQ to work 7710941Sdavid.guillen@arm.com // without any modifications. 7810941Sdavid.guillen@arm.com for (int i = 0; i < this->staticInst->numDestRegs(); i++) { 7912548Sodanrc@yahoo.com.br this->_destRegIdx[i] = this->staticInst->destRegIdx(i); 8012548Sodanrc@yahoo.com.br } 8113220Sodanrc@yahoo.com.br 8212548Sodanrc@yahoo.com.br for (int i = 0; i < this->staticInst->numSrcRegs(); i++) { 8310263Satgutier@umich.edu this->_srcRegIdx[i] = this->staticInst->srcRegIdx(i); 8410263Satgutier@umich.edu this->_readySrcRegIdx[i] = 0; 8510263Satgutier@umich.edu } 8612600Sodanrc@yahoo.com.br 8712600Sodanrc@yahoo.com.br _numDestMiscRegs = 0; 8812600Sodanrc@yahoo.com.br} 8912600Sodanrc@yahoo.com.br 9010263Satgutier@umich.edutemplate <class Impl> 9110263Satgutier@umich.eduFault 9210263Satgutier@umich.eduBaseO3DynInst<Impl>::execute() 9310263Satgutier@umich.edu{ 9410263Satgutier@umich.edu // @todo: Pretty convoluted way to avoid squashing from happening 9510263Satgutier@umich.edu // when using the TC during an instruction's execution 9610263Satgutier@umich.edu // (specifically for instructions that have side-effects that use 9710263Satgutier@umich.edu // the TC). Fix this. 9810263Satgutier@umich.edu bool in_syscall = this->thread->inSyscall; 9910263Satgutier@umich.edu this->thread->inSyscall = true; 10010263Satgutier@umich.edu 10112548Sodanrc@yahoo.com.br this->fault = this->staticInst->execute(this, this->traceData); 10210263Satgutier@umich.edu 10310263Satgutier@umich.edu this->thread->inSyscall = in_syscall; 10413419Sodanrc@yahoo.com.br 10513216Sodanrc@yahoo.com.br return this->fault; 10613419Sodanrc@yahoo.com.br} 10713216Sodanrc@yahoo.com.br 10813216Sodanrc@yahoo.com.brtemplate <class Impl> 10912745Sodanrc@yahoo.com.brFault 11012745Sodanrc@yahoo.com.brBaseO3DynInst<Impl>::initiateAcc() 11112684Sodanrc@yahoo.com.br{ 11212684Sodanrc@yahoo.com.br // @todo: Pretty convoluted way to avoid squashing from happening 11312684Sodanrc@yahoo.com.br // when using the TC during an instruction's execution 11412684Sodanrc@yahoo.com.br // (specifically for instructions that have side-effects that use 11512684Sodanrc@yahoo.com.br // the TC). Fix this. 11612684Sodanrc@yahoo.com.br bool in_syscall = this->thread->inSyscall; 11710263Satgutier@umich.edu this->thread->inSyscall = true; 11813418Sodanrc@yahoo.com.br 11913418Sodanrc@yahoo.com.br this->fault = this->staticInst->initiateAcc(this, this->traceData); 12013418Sodanrc@yahoo.com.br 12113418Sodanrc@yahoo.com.br this->thread->inSyscall = in_syscall; 12210263Satgutier@umich.edu 12310263Satgutier@umich.edu return this->fault; 12413418Sodanrc@yahoo.com.br} 12510263Satgutier@umich.edu 12610263Satgutier@umich.edutemplate <class Impl> 12711870Snikos.nikoleris@arm.comFault 12810263Satgutier@umich.eduBaseO3DynInst<Impl>::completeAcc(PacketPtr pkt) 12913220Sodanrc@yahoo.com.br{ 13010263Satgutier@umich.edu // @todo: Pretty convoluted way to avoid squashing from happening 13110263Satgutier@umich.edu // when using the TC during an instruction's execution 13210263Satgutier@umich.edu // (specifically for instructions that have side-effects that use 13310263Satgutier@umich.edu // the TC). Fix this. 13410941Sdavid.guillen@arm.com bool in_syscall = this->thread->inSyscall; 13510263Satgutier@umich.edu this->thread->inSyscall = true; 13611484Snikos.nikoleris@arm.com 13710263Satgutier@umich.edu this->fault = this->staticInst->completeAcc(pkt, this, this->traceData); 13810263Satgutier@umich.edu 13910263Satgutier@umich.edu this->thread->inSyscall = in_syscall; 14010941Sdavid.guillen@arm.com 14110263Satgutier@umich.edu return this->fault; 14210263Satgutier@umich.edu} 14313418Sodanrc@yahoo.com.br 14411484Snikos.nikoleris@arm.com#if FULL_SYSTEM 14512684Sodanrc@yahoo.com.brtemplate <class Impl> 14612684Sodanrc@yahoo.com.brFault 14712684Sodanrc@yahoo.com.brBaseO3DynInst<Impl>::hwrei() 14812600Sodanrc@yahoo.com.br{ 14912684Sodanrc@yahoo.com.br#if THE_ISA == ALPHA_ISA 15010263Satgutier@umich.edu // Can only do a hwrei when in pal mode. 15110263Satgutier@umich.edu if (!(this->instAddr() & 0x3)) 15213418Sodanrc@yahoo.com.br return new AlphaISA::UnimplementedOpcodeFault; 15313418Sodanrc@yahoo.com.br 15413418Sodanrc@yahoo.com.br // Set the next PC based on the value of the EXC_ADDR IPR. 15510263Satgutier@umich.edu AlphaISA::PCState pc = this->pcState(); 15610263Satgutier@umich.edu pc.npc(this->cpu->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR, 15710263Satgutier@umich.edu this->threadNumber)); 15810263Satgutier@umich.edu this->pcState(pc); 15912744Sodanrc@yahoo.com.br if (CPA::available()) { 16012744Sodanrc@yahoo.com.br ThreadContext *tc = this->cpu->tcBase(this->threadNumber); 16112600Sodanrc@yahoo.com.br CPA::cpa()->swAutoBegin(tc, this->nextInstAddr()); 16212600Sodanrc@yahoo.com.br } 16312746Sodanrc@yahoo.com.br 16413941Sodanrc@yahoo.com.br // Tell CPU to clear any state it needs to if a hwrei is taken. 16512744Sodanrc@yahoo.com.br this->cpu->hwrei(this->threadNumber); 16612600Sodanrc@yahoo.com.br#else 16710263Satgutier@umich.edu 16812746Sodanrc@yahoo.com.br#endif 16913941Sodanrc@yahoo.com.br // FIXME: XXX check for interrupts? XXX 17012746Sodanrc@yahoo.com.br return NoFault; 17110263Satgutier@umich.edu} 17213219Sodanrc@yahoo.com.br 17313219Sodanrc@yahoo.com.brtemplate <class Impl> 17413219Sodanrc@yahoo.com.brvoid 17512684Sodanrc@yahoo.com.brBaseO3DynInst<Impl>::trap(Fault fault) 17612600Sodanrc@yahoo.com.br{ 17712684Sodanrc@yahoo.com.br this->cpu->trap(fault, this->threadNumber, this->staticInst); 17813219Sodanrc@yahoo.com.br} 17912684Sodanrc@yahoo.com.br 18012744Sodanrc@yahoo.com.brtemplate <class Impl> 18112744Sodanrc@yahoo.com.brbool 18212744Sodanrc@yahoo.com.brBaseO3DynInst<Impl>::simPalCheck(int palFunc) 18312684Sodanrc@yahoo.com.br{ 18412600Sodanrc@yahoo.com.br#if THE_ISA != ALPHA_ISA 18510263Satgutier@umich.edu panic("simPalCheck called, but PAL only exists in Alpha!\n"); 18612600Sodanrc@yahoo.com.br#endif 18712636Sodanrc@yahoo.com.br return this->cpu->simPalCheck(palFunc, this->threadNumber); 18812636Sodanrc@yahoo.com.br} 18913752Sodanrc@yahoo.com.br#else 19010263Satgutier@umich.edutemplate <class Impl> 19110263Satgutier@umich.eduvoid 19213752Sodanrc@yahoo.com.brBaseO3DynInst<Impl>::syscall(int64_t callnum) 19312636Sodanrc@yahoo.com.br{ 19412636Sodanrc@yahoo.com.br // HACK: check CPU's nextPC before and after syscall. If it 19513752Sodanrc@yahoo.com.br // changes, update this instruction's nextPC because the syscall 19610274Smitch.hayenga@arm.com // must have changed the nextPC. 19712745Sodanrc@yahoo.com.br TheISA::PCState curPC = this->cpu->pcState(this->threadNumber); 19812745Sodanrc@yahoo.com.br this->cpu->syscall(callnum, this->threadNumber); 19912745Sodanrc@yahoo.com.br TheISA::PCState newPC = this->cpu->pcState(this->threadNumber); 20012636Sodanrc@yahoo.com.br if (!(curPC == newPC)) { 20112684Sodanrc@yahoo.com.br this->pcState(newPC); 20212636Sodanrc@yahoo.com.br } 20310263Satgutier@umich.edu} 20410263Satgutier@umich.edu#endif 20510941Sdavid.guillen@arm.com 20610941Sdavid.guillen@arm.com