dyn_inst_impl.hh revision 7684
11689SN/A/* 22316SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Kevin Lim 291689SN/A */ 301061SN/A 315953Ssaidi@eecs.umich.edu#include "base/cp_annotate.hh" 325596Sgblack@eecs.umich.edu#include "cpu/o3/dyn_inst.hh" 331061SN/A 341061SN/Atemplate <class Impl> 355596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr staticInst, 365596Sgblack@eecs.umich.edu Addr PC, Addr NPC, Addr microPC, 375596Sgblack@eecs.umich.edu Addr Pred_PC, Addr Pred_NPC, 385596Sgblack@eecs.umich.edu Addr Pred_MicroPC, 395596Sgblack@eecs.umich.edu InstSeqNum seq_num, O3CPU *cpu) 404637SN/A : BaseDynInst<Impl>(staticInst, PC, NPC, microPC, 415596Sgblack@eecs.umich.edu Pred_PC, Pred_NPC, Pred_MicroPC, seq_num, cpu) 424637SN/A{ 434637SN/A initVars(); 444637SN/A} 454637SN/A 464637SN/Atemplate <class Impl> 475596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::BaseO3DynInst(ExtMachInst inst, 485596Sgblack@eecs.umich.edu Addr PC, Addr NPC, Addr microPC, 495596Sgblack@eecs.umich.edu Addr Pred_PC, Addr Pred_NPC, 505596Sgblack@eecs.umich.edu Addr Pred_MicroPC, 515596Sgblack@eecs.umich.edu InstSeqNum seq_num, O3CPU *cpu) 524637SN/A : BaseDynInst<Impl>(inst, PC, NPC, microPC, 535596Sgblack@eecs.umich.edu Pred_PC, Pred_NPC, Pred_MicroPC, seq_num, cpu) 541061SN/A{ 552292SN/A initVars(); 561061SN/A} 571061SN/A 581061SN/Atemplate <class Impl> 595596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr &_staticInst) 601464SN/A : BaseDynInst<Impl>(_staticInst) 611061SN/A{ 622292SN/A initVars(); 632292SN/A} 642292SN/A 652292SN/Atemplate <class Impl> 662292SN/Avoid 675596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::initVars() 682292SN/A{ 691464SN/A // Make sure to have the renamed register entries set to the same 701464SN/A // as the normal register entries. It will allow the IQ to work 711464SN/A // without any modifications. 722292SN/A for (int i = 0; i < this->staticInst->numDestRegs(); i++) { 733782SN/A this->_destRegIdx[i] = this->staticInst->destRegIdx(i); 741464SN/A } 751464SN/A 762292SN/A for (int i = 0; i < this->staticInst->numSrcRegs(); i++) { 773782SN/A this->_srcRegIdx[i] = this->staticInst->srcRegIdx(i); 782292SN/A this->_readySrcRegIdx[i] = 0; 791464SN/A } 801061SN/A} 811061SN/A 822292SN/Atemplate <class Impl> 832292SN/AFault 845596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::execute() 852292SN/A{ 862348SN/A // @todo: Pretty convoluted way to avoid squashing from happening 872680SN/A // when using the TC during an instruction's execution 882348SN/A // (specifically for instructions that have side-effects that use 892680SN/A // the TC). Fix this. 902292SN/A bool in_syscall = this->thread->inSyscall; 912292SN/A this->thread->inSyscall = true; 922292SN/A 932292SN/A this->fault = this->staticInst->execute(this, this->traceData); 942292SN/A 952292SN/A this->thread->inSyscall = in_syscall; 962292SN/A 972292SN/A return this->fault; 982292SN/A} 992292SN/A 1002292SN/Atemplate <class Impl> 1012292SN/AFault 1025596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::initiateAcc() 1032292SN/A{ 1042348SN/A // @todo: Pretty convoluted way to avoid squashing from happening 1052680SN/A // when using the TC during an instruction's execution 1062348SN/A // (specifically for instructions that have side-effects that use 1072680SN/A // the TC). Fix this. 1082292SN/A bool in_syscall = this->thread->inSyscall; 1092292SN/A this->thread->inSyscall = true; 1102292SN/A 1112292SN/A this->fault = this->staticInst->initiateAcc(this, this->traceData); 1122292SN/A 1132292SN/A this->thread->inSyscall = in_syscall; 1142292SN/A 1152292SN/A return this->fault; 1162292SN/A} 1172292SN/A 1182292SN/Atemplate <class Impl> 1192292SN/AFault 1205596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::completeAcc(PacketPtr pkt) 1212292SN/A{ 1222790SN/A this->fault = this->staticInst->completeAcc(pkt, this, this->traceData); 1232292SN/A 1242292SN/A return this->fault; 1252292SN/A} 1262292SN/A 1271858SN/A#if FULL_SYSTEM 1281061SN/Atemplate <class Impl> 1295702Ssaidi@eecs.umich.eduFault 1305702Ssaidi@eecs.umich.eduBaseO3DynInst<Impl>::hwrei() 1315702Ssaidi@eecs.umich.edu{ 1325702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 1335702Ssaidi@eecs.umich.edu // Can only do a hwrei when in pal mode. 1345702Ssaidi@eecs.umich.edu if (!(this->readPC() & 0x3)) 1355702Ssaidi@eecs.umich.edu return new AlphaISA::UnimplementedOpcodeFault; 1365702Ssaidi@eecs.umich.edu 1375702Ssaidi@eecs.umich.edu // Set the next PC based on the value of the EXC_ADDR IPR. 1385702Ssaidi@eecs.umich.edu this->setNextPC(this->cpu->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR, 1395702Ssaidi@eecs.umich.edu this->threadNumber)); 1405953Ssaidi@eecs.umich.edu if (CPA::available()) { 1415953Ssaidi@eecs.umich.edu ThreadContext *tc = this->cpu->tcBase(this->threadNumber); 1425953Ssaidi@eecs.umich.edu CPA::cpa()->swAutoBegin(tc, this->readNextPC()); 1435953Ssaidi@eecs.umich.edu } 1445702Ssaidi@eecs.umich.edu 1455702Ssaidi@eecs.umich.edu // Tell CPU to clear any state it needs to if a hwrei is taken. 1465702Ssaidi@eecs.umich.edu this->cpu->hwrei(this->threadNumber); 1475702Ssaidi@eecs.umich.edu#else 1485702Ssaidi@eecs.umich.edu 1495702Ssaidi@eecs.umich.edu#endif 1505702Ssaidi@eecs.umich.edu // FIXME: XXX check for interrupts? XXX 1515702Ssaidi@eecs.umich.edu return NoFault; 1525702Ssaidi@eecs.umich.edu} 1535702Ssaidi@eecs.umich.edu 1545702Ssaidi@eecs.umich.edutemplate <class Impl> 1551061SN/Avoid 1565596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::trap(Fault fault) 1571061SN/A{ 1587684Sgblack@eecs.umich.edu this->cpu->trap(fault, this->threadNumber, this->staticInst); 1591061SN/A} 1605702Ssaidi@eecs.umich.edu 1615702Ssaidi@eecs.umich.edutemplate <class Impl> 1625702Ssaidi@eecs.umich.edubool 1635702Ssaidi@eecs.umich.eduBaseO3DynInst<Impl>::simPalCheck(int palFunc) 1645702Ssaidi@eecs.umich.edu{ 1655702Ssaidi@eecs.umich.edu#if THE_ISA != ALPHA_ISA 1665702Ssaidi@eecs.umich.edu panic("simPalCheck called, but PAL only exists in Alpha!\n"); 1675702Ssaidi@eecs.umich.edu#endif 1685702Ssaidi@eecs.umich.edu return this->cpu->simPalCheck(palFunc, this->threadNumber); 1695702Ssaidi@eecs.umich.edu} 1701061SN/A#else 1711061SN/Atemplate <class Impl> 1721061SN/Avoid 1735596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::syscall(int64_t callnum) 1741061SN/A{ 1755556SN/A // HACK: check CPU's nextPC before and after syscall. If it 1765556SN/A // changes, update this instruction's nextPC because the syscall 1775556SN/A // must have changed the nextPC. 1785556SN/A Addr cpu_next_pc = this->cpu->readNextPC(this->threadNumber); 1792669SN/A this->cpu->syscall(callnum, this->threadNumber); 1805556SN/A Addr new_next_pc = this->cpu->readNextPC(this->threadNumber); 1815556SN/A if (cpu_next_pc != new_next_pc) { 1825556SN/A this->setNextPC(new_next_pc); 1835556SN/A } 1841061SN/A} 1851061SN/A#endif 1861061SN/A 187