dyn_inst_impl.hh revision 5596
112855Sgabeblack@google.com/* 212855Sgabeblack@google.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 312855Sgabeblack@google.com * All rights reserved. 412855Sgabeblack@google.com * 512855Sgabeblack@google.com * Redistribution and use in source and binary forms, with or without 612855Sgabeblack@google.com * modification, are permitted provided that the following conditions are 712855Sgabeblack@google.com * met: redistributions of source code must retain the above copyright 812855Sgabeblack@google.com * notice, this list of conditions and the following disclaimer; 912855Sgabeblack@google.com * redistributions in binary form must reproduce the above copyright 1012855Sgabeblack@google.com * notice, this list of conditions and the following disclaimer in the 1112855Sgabeblack@google.com * documentation and/or other materials provided with the distribution; 1212855Sgabeblack@google.com * neither the name of the copyright holders nor the names of its 1312855Sgabeblack@google.com * contributors may be used to endorse or promote products derived from 1412855Sgabeblack@google.com * this software without specific prior written permission. 1512855Sgabeblack@google.com * 1612855Sgabeblack@google.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1712855Sgabeblack@google.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1812855Sgabeblack@google.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1912855Sgabeblack@google.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2012855Sgabeblack@google.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2112855Sgabeblack@google.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2212855Sgabeblack@google.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2312855Sgabeblack@google.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2412855Sgabeblack@google.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2512855Sgabeblack@google.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2612855Sgabeblack@google.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2712855Sgabeblack@google.com * 2812855Sgabeblack@google.com * Authors: Kevin Lim 2912855Sgabeblack@google.com */ 3012855Sgabeblack@google.com 3112855Sgabeblack@google.com#include "cpu/o3/dyn_inst.hh" 3212855Sgabeblack@google.com 3312855Sgabeblack@google.comtemplate <class Impl> 3412855Sgabeblack@google.comBaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr staticInst, 3512855Sgabeblack@google.com Addr PC, Addr NPC, Addr microPC, 3612855Sgabeblack@google.com Addr Pred_PC, Addr Pred_NPC, 3712855Sgabeblack@google.com Addr Pred_MicroPC, 3812855Sgabeblack@google.com InstSeqNum seq_num, O3CPU *cpu) 3912855Sgabeblack@google.com : BaseDynInst<Impl>(staticInst, PC, NPC, microPC, 4012855Sgabeblack@google.com Pred_PC, Pred_NPC, Pred_MicroPC, seq_num, cpu) 4112855Sgabeblack@google.com{ 4212855Sgabeblack@google.com initVars(); 4312855Sgabeblack@google.com} 4412855Sgabeblack@google.com 4512855Sgabeblack@google.comtemplate <class Impl> 4612855Sgabeblack@google.comBaseO3DynInst<Impl>::BaseO3DynInst(ExtMachInst inst, 4712855Sgabeblack@google.com Addr PC, Addr NPC, Addr microPC, 4812855Sgabeblack@google.com Addr Pred_PC, Addr Pred_NPC, 4912855Sgabeblack@google.com Addr Pred_MicroPC, 5012855Sgabeblack@google.com InstSeqNum seq_num, O3CPU *cpu) 5112855Sgabeblack@google.com : BaseDynInst<Impl>(inst, PC, NPC, microPC, 5212855Sgabeblack@google.com Pred_PC, Pred_NPC, Pred_MicroPC, seq_num, cpu) 5312855Sgabeblack@google.com{ 5412855Sgabeblack@google.com initVars(); 5512855Sgabeblack@google.com} 5612855Sgabeblack@google.com 5712855Sgabeblack@google.comtemplate <class Impl> 5812855Sgabeblack@google.comBaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr &_staticInst) 5912855Sgabeblack@google.com : BaseDynInst<Impl>(_staticInst) 6012855Sgabeblack@google.com{ 6112855Sgabeblack@google.com initVars(); 6212855Sgabeblack@google.com} 6312855Sgabeblack@google.com 6412855Sgabeblack@google.comtemplate <class Impl> 6512855Sgabeblack@google.comvoid 6612855Sgabeblack@google.comBaseO3DynInst<Impl>::initVars() 6712855Sgabeblack@google.com{ 6812855Sgabeblack@google.com // Make sure to have the renamed register entries set to the same 6912855Sgabeblack@google.com // as the normal register entries. It will allow the IQ to work 7012855Sgabeblack@google.com // without any modifications. 7112855Sgabeblack@google.com for (int i = 0; i < this->staticInst->numDestRegs(); i++) { 7212855Sgabeblack@google.com this->_destRegIdx[i] = this->staticInst->destRegIdx(i); 7312855Sgabeblack@google.com } 7412855Sgabeblack@google.com 7512855Sgabeblack@google.com for (int i = 0; i < this->staticInst->numSrcRegs(); i++) { 7612855Sgabeblack@google.com this->_srcRegIdx[i] = this->staticInst->srcRegIdx(i); 7712855Sgabeblack@google.com this->_readySrcRegIdx[i] = 0; 78 } 79} 80 81template <class Impl> 82Fault 83BaseO3DynInst<Impl>::execute() 84{ 85 // @todo: Pretty convoluted way to avoid squashing from happening 86 // when using the TC during an instruction's execution 87 // (specifically for instructions that have side-effects that use 88 // the TC). Fix this. 89 bool in_syscall = this->thread->inSyscall; 90 this->thread->inSyscall = true; 91 92 this->fault = this->staticInst->execute(this, this->traceData); 93 94 this->thread->inSyscall = in_syscall; 95 96 return this->fault; 97} 98 99template <class Impl> 100Fault 101BaseO3DynInst<Impl>::initiateAcc() 102{ 103 // @todo: Pretty convoluted way to avoid squashing from happening 104 // when using the TC during an instruction's execution 105 // (specifically for instructions that have side-effects that use 106 // the TC). Fix this. 107 bool in_syscall = this->thread->inSyscall; 108 this->thread->inSyscall = true; 109 110 this->fault = this->staticInst->initiateAcc(this, this->traceData); 111 112 this->thread->inSyscall = in_syscall; 113 114 return this->fault; 115} 116 117template <class Impl> 118Fault 119BaseO3DynInst<Impl>::completeAcc(PacketPtr pkt) 120{ 121 this->fault = this->staticInst->completeAcc(pkt, this, this->traceData); 122 123 return this->fault; 124} 125 126#if FULL_SYSTEM 127template <class Impl> 128Fault 129BaseO3DynInst<Impl>::hwrei() 130{ 131#if THE_ISA == ALPHA_ISA 132 // Can only do a hwrei when in pal mode. 133 if (!(this->readPC() & 0x3)) 134 return new AlphaISA::UnimplementedOpcodeFault; 135 136 // Set the next PC based on the value of the EXC_ADDR IPR. 137 this->setNextPC(this->cpu->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR, 138 this->threadNumber)); 139 140 // Tell CPU to clear any state it needs to if a hwrei is taken. 141 this->cpu->hwrei(this->threadNumber); 142#else 143 144#endif 145 // FIXME: XXX check for interrupts? XXX 146 return NoFault; 147} 148 149template <class Impl> 150void 151BaseO3DynInst<Impl>::trap(Fault fault) 152{ 153 this->cpu->trap(fault, this->threadNumber); 154} 155 156template <class Impl> 157bool 158BaseO3DynInst<Impl>::simPalCheck(int palFunc) 159{ 160#if THE_ISA != ALPHA_ISA 161 panic("simPalCheck called, but PAL only exists in Alpha!\n"); 162#endif 163 return this->cpu->simPalCheck(palFunc, this->threadNumber); 164} 165#else 166template <class Impl> 167void 168BaseO3DynInst<Impl>::syscall(int64_t callnum) 169{ 170 // HACK: check CPU's nextPC before and after syscall. If it 171 // changes, update this instruction's nextPC because the syscall 172 // must have changed the nextPC. 173 Addr cpu_next_pc = this->cpu->readNextPC(this->threadNumber); 174 this->cpu->syscall(callnum, this->threadNumber); 175 Addr new_next_pc = this->cpu->readNextPC(this->threadNumber); 176 if (cpu_next_pc != new_next_pc) { 177 this->setNextPC(new_next_pc); 178 } 179} 180#endif 181 182