dyn_inst_impl.hh revision 1464
19243SN/A 210889Sandreas.hansson@arm.com#include "cpu/beta_cpu/alpha_dyn_inst.hh" 39243SN/A 49243SN/Atemplate <class Impl> 59243SN/AAlphaDynInst<Impl>::AlphaDynInst(MachInst inst, Addr PC, Addr Pred_PC, 69243SN/A InstSeqNum seq_num, FullCPU *cpu) 79243SN/A : BaseDynInst<Impl>(inst, PC, Pred_PC, seq_num, cpu) 89243SN/A{ 99243SN/A // Make sure to have the renamed register entries set to the same 109243SN/A // as the normal register entries. It will allow the IQ to work 119243SN/A // without any modifications. 129243SN/A for (int i = 0; i < this->staticInst->numDestRegs(); i++) 139243SN/A { 149831SN/A _destRegIdx[i] = this->staticInst->destRegIdx(i); 159831SN/A } 169831SN/A 179243SN/A for (int i = 0; i < this->staticInst->numSrcRegs(); i++) 189243SN/A { 199243SN/A _srcRegIdx[i] = this->staticInst->srcRegIdx(i); 209243SN/A this->_readySrcRegIdx[i] = 0; 219243SN/A } 229243SN/A 239243SN/A} 249243SN/A 259243SN/Atemplate <class Impl> 269243SN/AAlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr<AlphaISA> &_staticInst) 279243SN/A : BaseDynInst<Impl>(_staticInst) 289243SN/A{ 299243SN/A // Make sure to have the renamed register entries set to the same 309243SN/A // as the normal register entries. It will allow the IQ to work 319243SN/A // without any modifications. 329243SN/A for (int i = 0; i < _staticInst->numDestRegs(); i++) 339243SN/A { 349243SN/A _destRegIdx[i] = _staticInst->destRegIdx(i); 359243SN/A } 369243SN/A 379243SN/A for (int i = 0; i < _staticInst->numSrcRegs(); i++) 389243SN/A { 399243SN/A _srcRegIdx[i] = _staticInst->srcRegIdx(i); 409243SN/A } 419243SN/A} 429967SN/A 4310618SOmar.Naji@arm.comtemplate <class Impl> 449243SN/Auint64_t 459243SN/AAlphaDynInst<Impl>::readUniq() 4610146Sandreas.hansson@arm.com{ 479356SN/A return this->cpu->readUniq(); 4810146Sandreas.hansson@arm.com} 4910247Sandreas.hansson@arm.com 5010208Sandreas.hansson@arm.comtemplate <class Impl> 519352SN/Avoid 5210146Sandreas.hansson@arm.comAlphaDynInst<Impl>::setUniq(uint64_t val) 539814SN/A{ 549243SN/A this->cpu->setUniq(val); 559243SN/A} 5610432SOmar.Naji@arm.com 579243SN/Atemplate <class Impl> 5810146Sandreas.hansson@arm.comuint64_t 599243SN/AAlphaDynInst<Impl>::readFpcr() 6010619Sandreas.hansson@arm.com{ 619243SN/A return this->cpu->readFpcr(); 6210211Sandreas.hansson@arm.com} 6310618SOmar.Naji@arm.com 6410489SOmar.Naji@arm.comtemplate <class Impl> 659831SN/Avoid 669831SN/AAlphaDynInst<Impl>::setFpcr(uint64_t val) 679831SN/A{ 689831SN/A this->cpu->setFpcr(val); 699831SN/A} 7010140SN/A 7110646Sandreas.hansson@arm.com#ifdef FULL_SYSTEM 729243SN/Atemplate <class Impl> 7310394Swendy.elsasser@arm.comuint64_t 7410394Swendy.elsasser@arm.comAlphaDynInst<Impl>::readIpr(int idx, Fault &fault) 759566SN/A{ 769243SN/A return this->cpu->readIpr(idx, fault); 779243SN/A} 7810140SN/A 7910140SN/Atemplate <class Impl> 8010147Sandreas.hansson@arm.comFault 8110147Sandreas.hansson@arm.comAlphaDynInst<Impl>::setIpr(int idx, uint64_t val) 8210393Swendy.elsasser@arm.com{ 8310394Swendy.elsasser@arm.com return this->cpu->setIpr(idx, val); 8410394Swendy.elsasser@arm.com} 8510394Swendy.elsasser@arm.com 869243SN/Atemplate <class Impl> 879243SN/AFault 8810141SN/AAlphaDynInst<Impl>::hwrei() 899726SN/A{ 909726SN/A return this->cpu->hwrei(); 9110618SOmar.Naji@arm.com} 9210618SOmar.Naji@arm.com 939243SN/Atemplate <class Impl> 9410620Sandreas.hansson@arm.comint 9510620Sandreas.hansson@arm.comAlphaDynInst<Impl>::readIntrFlag() 9610620Sandreas.hansson@arm.com{ 9710620Sandreas.hansson@arm.comreturn this->cpu->readIntrFlag(); 9810620Sandreas.hansson@arm.com} 9910889Sandreas.hansson@arm.com 10010889Sandreas.hansson@arm.comtemplate <class Impl> 10110889Sandreas.hansson@arm.comvoid 10210618SOmar.Naji@arm.comAlphaDynInst<Impl>::setIntrFlag(int val) 10310618SOmar.Naji@arm.com{ 10410618SOmar.Naji@arm.com this->cpu->setIntrFlag(val); 10510432SOmar.Naji@arm.com} 10610618SOmar.Naji@arm.com 10710618SOmar.Naji@arm.comtemplate <class Impl> 10810618SOmar.Naji@arm.combool 10910432SOmar.Naji@arm.comAlphaDynInst<Impl>::inPalMode() 11010246Sandreas.hansson@arm.com{ 11110618SOmar.Naji@arm.com return this->cpu->inPalMode(); 11210561SOmar.Naji@arm.com} 11310561SOmar.Naji@arm.com 11410561SOmar.Naji@arm.comtemplate <class Impl> 11510394Swendy.elsasser@arm.comvoid 11610394Swendy.elsasser@arm.comAlphaDynInst<Impl>::trap(Fault fault) 11710394Swendy.elsasser@arm.com{ 11810394Swendy.elsasser@arm.com this->cpu->trap(fault); 11910394Swendy.elsasser@arm.com} 12010394Swendy.elsasser@arm.com 12110394Swendy.elsasser@arm.comtemplate <class Impl> 12210394Swendy.elsasser@arm.combool 12310618SOmar.Naji@arm.comAlphaDynInst<Impl>::simPalCheck(int palFunc) 12410394Swendy.elsasser@arm.com{ 12510394Swendy.elsasser@arm.com return this->cpu->simPalCheck(palFunc); 12610618SOmar.Naji@arm.com} 12710394Swendy.elsasser@arm.com#else 12810246Sandreas.hansson@arm.comtemplate <class Impl> 12910246Sandreas.hansson@arm.comvoid 13010246Sandreas.hansson@arm.comAlphaDynInst<Impl>::syscall() 13110140SN/A{ 13210140SN/A this->cpu->syscall(); 13310140SN/A} 13410140SN/A#endif 13510140SN/A 1369243SN/A