dyn_inst_impl.hh revision 10474
11689SN/A/*
28733Sgeoffrey.blake@arm.com * Copyright (c) 2010-2011 ARM Limited
37783SGiacomo.Gabrielli@arm.com * All rights reserved
47783SGiacomo.Gabrielli@arm.com *
57783SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall
67783SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual
77783SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating
87783SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software
97783SGiacomo.Gabrielli@arm.com * licensed hereunder.  You may use the software subject to the license
107783SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated
117783SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software,
127783SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form.
137783SGiacomo.Gabrielli@arm.com *
142316SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan
151689SN/A * All rights reserved.
161689SN/A *
171689SN/A * Redistribution and use in source and binary forms, with or without
181689SN/A * modification, are permitted provided that the following conditions are
191689SN/A * met: redistributions of source code must retain the above copyright
201689SN/A * notice, this list of conditions and the following disclaimer;
211689SN/A * redistributions in binary form must reproduce the above copyright
221689SN/A * notice, this list of conditions and the following disclaimer in the
231689SN/A * documentation and/or other materials provided with the distribution;
241689SN/A * neither the name of the copyright holders nor the names of its
251689SN/A * contributors may be used to endorse or promote products derived from
261689SN/A * this software without specific prior written permission.
271689SN/A *
281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
392665SN/A *
402665SN/A * Authors: Kevin Lim
411689SN/A */
421061SN/A
439944Smatt.horsnell@ARM.com#ifndef __CPU_O3_DYN_INST_IMPL_HH__
449944Smatt.horsnell@ARM.com#define __CPU_O3_DYN_INST_IMPL_HH__
459944Smatt.horsnell@ARM.com
465953Ssaidi@eecs.umich.edu#include "base/cp_annotate.hh"
475596Sgblack@eecs.umich.edu#include "cpu/o3/dyn_inst.hh"
488779Sgblack@eecs.umich.edu#include "sim/full_system.hh"
499252Sdjordje.kovacevic@arm.com#include "debug/O3PipeView.hh"
501061SN/A
511061SN/Atemplate <class Impl>
5210417Sandreas.hansson@arm.comBaseO3DynInst<Impl>::BaseO3DynInst(const StaticInstPtr &staticInst,
5310417Sandreas.hansson@arm.com                                   const StaticInstPtr &macroop,
547720Sgblack@eecs.umich.edu                                   TheISA::PCState pc, TheISA::PCState predPC,
555596Sgblack@eecs.umich.edu                                   InstSeqNum seq_num, O3CPU *cpu)
568502Sgblack@eecs.umich.edu    : BaseDynInst<Impl>(staticInst, macroop, pc, predPC, seq_num, cpu)
574637SN/A{
584637SN/A    initVars();
594637SN/A}
604637SN/A
614637SN/Atemplate <class Impl>
6210417Sandreas.hansson@arm.comBaseO3DynInst<Impl>::BaseO3DynInst(const StaticInstPtr &_staticInst,
6310417Sandreas.hansson@arm.com                                   const StaticInstPtr &_macroop)
648502Sgblack@eecs.umich.edu    : BaseDynInst<Impl>(_staticInst, _macroop)
651061SN/A{
662292SN/A    initVars();
672292SN/A}
682292SN/A
699252Sdjordje.kovacevic@arm.comtemplate <class Impl>BaseO3DynInst<Impl>::~BaseO3DynInst()
709252Sdjordje.kovacevic@arm.com{
719252Sdjordje.kovacevic@arm.com#if TRACING_ON
729527SMatt.Horsnell@arm.com    if (DTRACE(O3PipeView)) {
739527SMatt.Horsnell@arm.com        Tick fetch = this->fetchTick;
749527SMatt.Horsnell@arm.com        // fetchTick can be -1 if the instruction fetched outside the trace window.
759527SMatt.Horsnell@arm.com        if (fetch != -1) {
769527SMatt.Horsnell@arm.com            Tick val;
779527SMatt.Horsnell@arm.com            // Print info needed by the pipeline activity viewer.
789527SMatt.Horsnell@arm.com            DPRINTFR(O3PipeView, "O3PipeView:fetch:%llu:0x%08llx:%d:%llu:%s\n",
799527SMatt.Horsnell@arm.com                     fetch,
809527SMatt.Horsnell@arm.com                     this->instAddr(),
819527SMatt.Horsnell@arm.com                     this->microPC(),
829527SMatt.Horsnell@arm.com                     this->seqNum,
839527SMatt.Horsnell@arm.com                     this->staticInst->disassemble(this->instAddr()));
849527SMatt.Horsnell@arm.com
859527SMatt.Horsnell@arm.com            val = (this->decodeTick == -1) ? 0 : fetch + this->decodeTick;
869527SMatt.Horsnell@arm.com            DPRINTFR(O3PipeView, "O3PipeView:decode:%llu\n", val);
879527SMatt.Horsnell@arm.com            val = (this->renameTick == -1) ? 0 : fetch + this->renameTick;
889527SMatt.Horsnell@arm.com            DPRINTFR(O3PipeView, "O3PipeView:rename:%llu\n", val);
899527SMatt.Horsnell@arm.com            val = (this->dispatchTick == -1) ? 0 : fetch + this->dispatchTick;
909527SMatt.Horsnell@arm.com            DPRINTFR(O3PipeView, "O3PipeView:dispatch:%llu\n", val);
919527SMatt.Horsnell@arm.com            val = (this->issueTick == -1) ? 0 : fetch + this->issueTick;
929527SMatt.Horsnell@arm.com            DPRINTFR(O3PipeView, "O3PipeView:issue:%llu\n", val);
939527SMatt.Horsnell@arm.com            val = (this->completeTick == -1) ? 0 : fetch + this->completeTick;
949527SMatt.Horsnell@arm.com            DPRINTFR(O3PipeView, "O3PipeView:complete:%llu\n", val);
959527SMatt.Horsnell@arm.com            val = (this->commitTick == -1) ? 0 : fetch + this->commitTick;
969527SMatt.Horsnell@arm.com
979527SMatt.Horsnell@arm.com            Tick valS = (this->storeTick == -1) ? 0 : fetch + this->storeTick;
989527SMatt.Horsnell@arm.com            DPRINTFR(O3PipeView, "O3PipeView:retire:%llu:store:%llu\n", val, valS);
999527SMatt.Horsnell@arm.com        }
1009527SMatt.Horsnell@arm.com    }
1019252Sdjordje.kovacevic@arm.com#endif
1029252Sdjordje.kovacevic@arm.com};
1039252Sdjordje.kovacevic@arm.com
1049252Sdjordje.kovacevic@arm.com
1052292SN/Atemplate <class Impl>
1062292SN/Avoid
1075596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::initVars()
1082292SN/A{
1091464SN/A    // Make sure to have the renamed register entries set to the same
1101464SN/A    // as the normal register entries.  It will allow the IQ to work
1111464SN/A    // without any modifications.
1122292SN/A    for (int i = 0; i < this->staticInst->numDestRegs(); i++) {
1133782SN/A        this->_destRegIdx[i] = this->staticInst->destRegIdx(i);
1141464SN/A    }
1151464SN/A
1162292SN/A    for (int i = 0; i < this->staticInst->numSrcRegs(); i++) {
1173782SN/A        this->_srcRegIdx[i] = this->staticInst->srcRegIdx(i);
1181464SN/A    }
1197783SGiacomo.Gabrielli@arm.com
1209046SAli.Saidi@ARM.com    this->_readySrcRegIdx.reset();
1219046SAli.Saidi@ARM.com
1227783SGiacomo.Gabrielli@arm.com    _numDestMiscRegs = 0;
1238471SGiacomo.Gabrielli@arm.com
1248471SGiacomo.Gabrielli@arm.com#if TRACING_ON
1259252Sdjordje.kovacevic@arm.com    // Value -1 indicates that particular phase
1269252Sdjordje.kovacevic@arm.com    // hasn't happened (yet).
1279252Sdjordje.kovacevic@arm.com    fetchTick = -1;
1289252Sdjordje.kovacevic@arm.com    decodeTick = -1;
1299252Sdjordje.kovacevic@arm.com    renameTick = -1;
1309252Sdjordje.kovacevic@arm.com    dispatchTick = -1;
1319252Sdjordje.kovacevic@arm.com    issueTick = -1;
1329252Sdjordje.kovacevic@arm.com    completeTick = -1;
1339252Sdjordje.kovacevic@arm.com    commitTick = -1;
1349527SMatt.Horsnell@arm.com    storeTick = -1;
1358471SGiacomo.Gabrielli@arm.com#endif
1361061SN/A}
1371061SN/A
1382292SN/Atemplate <class Impl>
1392292SN/AFault
1405596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::execute()
1412292SN/A{
1422348SN/A    // @todo: Pretty convoluted way to avoid squashing from happening
1432680SN/A    // when using the TC during an instruction's execution
1442348SN/A    // (specifically for instructions that have side-effects that use
1452680SN/A    // the TC).  Fix this.
1469382SAli.Saidi@ARM.com    bool no_squash_from_TC = this->thread->noSquashFromTC;
1479382SAli.Saidi@ARM.com    this->thread->noSquashFromTC = true;
1482292SN/A
1492292SN/A    this->fault = this->staticInst->execute(this, this->traceData);
1502292SN/A
1519382SAli.Saidi@ARM.com    this->thread->noSquashFromTC = no_squash_from_TC;
1522292SN/A
1532292SN/A    return this->fault;
1542292SN/A}
1552292SN/A
1562292SN/Atemplate <class Impl>
1572292SN/AFault
1585596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::initiateAcc()
1592292SN/A{
1602348SN/A    // @todo: Pretty convoluted way to avoid squashing from happening
1612680SN/A    // when using the TC during an instruction's execution
1622348SN/A    // (specifically for instructions that have side-effects that use
1632680SN/A    // the TC).  Fix this.
1649382SAli.Saidi@ARM.com    bool no_squash_from_TC = this->thread->noSquashFromTC;
1659382SAli.Saidi@ARM.com    this->thread->noSquashFromTC = true;
1662292SN/A
1672292SN/A    this->fault = this->staticInst->initiateAcc(this, this->traceData);
1682292SN/A
1699382SAli.Saidi@ARM.com    this->thread->noSquashFromTC = no_squash_from_TC;
1702292SN/A
1712292SN/A    return this->fault;
1722292SN/A}
1732292SN/A
1742292SN/Atemplate <class Impl>
1752292SN/AFault
1765596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::completeAcc(PacketPtr pkt)
1772292SN/A{
1787758Sminkyu.jeong@arm.com    // @todo: Pretty convoluted way to avoid squashing from happening
1797758Sminkyu.jeong@arm.com    // when using the TC during an instruction's execution
1807758Sminkyu.jeong@arm.com    // (specifically for instructions that have side-effects that use
1817758Sminkyu.jeong@arm.com    // the TC).  Fix this.
1829382SAli.Saidi@ARM.com    bool no_squash_from_TC = this->thread->noSquashFromTC;
1839382SAli.Saidi@ARM.com    this->thread->noSquashFromTC = true;
1847758Sminkyu.jeong@arm.com
1858887Sgeoffrey.blake@arm.com    if (this->cpu->checker) {
1868887Sgeoffrey.blake@arm.com        if (this->isStoreConditional()) {
1878887Sgeoffrey.blake@arm.com            this->reqToVerify->setExtraData(pkt->req->getExtraData());
1888887Sgeoffrey.blake@arm.com        }
1898733Sgeoffrey.blake@arm.com    }
1908887Sgeoffrey.blake@arm.com
1912790SN/A    this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
1922292SN/A
1939382SAli.Saidi@ARM.com    this->thread->noSquashFromTC = no_squash_from_TC;
1947758Sminkyu.jeong@arm.com
1952292SN/A    return this->fault;
1962292SN/A}
1972292SN/A
1981061SN/Atemplate <class Impl>
1995702Ssaidi@eecs.umich.eduFault
2005702Ssaidi@eecs.umich.eduBaseO3DynInst<Impl>::hwrei()
2015702Ssaidi@eecs.umich.edu{
2025702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA
2035702Ssaidi@eecs.umich.edu    // Can only do a hwrei when in pal mode.
2047720Sgblack@eecs.umich.edu    if (!(this->instAddr() & 0x3))
20510474Sandreas.hansson@arm.com        return std::make_shared<AlphaISA::UnimplementedOpcodeFault>();
2065702Ssaidi@eecs.umich.edu
2075702Ssaidi@eecs.umich.edu    // Set the next PC based on the value of the EXC_ADDR IPR.
2087720Sgblack@eecs.umich.edu    AlphaISA::PCState pc = this->pcState();
2097720Sgblack@eecs.umich.edu    pc.npc(this->cpu->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR,
2107720Sgblack@eecs.umich.edu                                          this->threadNumber));
2117720Sgblack@eecs.umich.edu    this->pcState(pc);
2125953Ssaidi@eecs.umich.edu    if (CPA::available()) {
2135953Ssaidi@eecs.umich.edu        ThreadContext *tc = this->cpu->tcBase(this->threadNumber);
2147720Sgblack@eecs.umich.edu        CPA::cpa()->swAutoBegin(tc, this->nextInstAddr());
2155953Ssaidi@eecs.umich.edu    }
2165702Ssaidi@eecs.umich.edu
2175702Ssaidi@eecs.umich.edu    // Tell CPU to clear any state it needs to if a hwrei is taken.
2185702Ssaidi@eecs.umich.edu    this->cpu->hwrei(this->threadNumber);
2195702Ssaidi@eecs.umich.edu#else
2205702Ssaidi@eecs.umich.edu
2215702Ssaidi@eecs.umich.edu#endif
2225702Ssaidi@eecs.umich.edu    // FIXME: XXX check for interrupts? XXX
2235702Ssaidi@eecs.umich.edu    return NoFault;
2245702Ssaidi@eecs.umich.edu}
2255702Ssaidi@eecs.umich.edu
2265702Ssaidi@eecs.umich.edutemplate <class Impl>
2271061SN/Avoid
22810379Sandreas.hansson@arm.comBaseO3DynInst<Impl>::trap(const Fault &fault)
2291061SN/A{
2307684Sgblack@eecs.umich.edu    this->cpu->trap(fault, this->threadNumber, this->staticInst);
2311061SN/A}
2325702Ssaidi@eecs.umich.edu
2335702Ssaidi@eecs.umich.edutemplate <class Impl>
2345702Ssaidi@eecs.umich.edubool
2355702Ssaidi@eecs.umich.eduBaseO3DynInst<Impl>::simPalCheck(int palFunc)
2365702Ssaidi@eecs.umich.edu{
2375702Ssaidi@eecs.umich.edu#if THE_ISA != ALPHA_ISA
2385702Ssaidi@eecs.umich.edu    panic("simPalCheck called, but PAL only exists in Alpha!\n");
2395702Ssaidi@eecs.umich.edu#endif
2405702Ssaidi@eecs.umich.edu    return this->cpu->simPalCheck(palFunc, this->threadNumber);
2415702Ssaidi@eecs.umich.edu}
2428557Sgblack@eecs.umich.edu
2431061SN/Atemplate <class Impl>
2441061SN/Avoid
2455596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::syscall(int64_t callnum)
2461061SN/A{
2478806Sgblack@eecs.umich.edu    if (FullSystem)
2488779Sgblack@eecs.umich.edu        panic("Syscall emulation isn't available in FS mode.\n");
2498806Sgblack@eecs.umich.edu
2505556SN/A    // HACK: check CPU's nextPC before and after syscall. If it
2515556SN/A    // changes, update this instruction's nextPC because the syscall
2525556SN/A    // must have changed the nextPC.
2537720Sgblack@eecs.umich.edu    TheISA::PCState curPC = this->cpu->pcState(this->threadNumber);
2542669SN/A    this->cpu->syscall(callnum, this->threadNumber);
2557720Sgblack@eecs.umich.edu    TheISA::PCState newPC = this->cpu->pcState(this->threadNumber);
2567720Sgblack@eecs.umich.edu    if (!(curPC == newPC)) {
2577720Sgblack@eecs.umich.edu        this->pcState(newPC);
2585556SN/A    }
2591061SN/A}
2601061SN/A
2619944Smatt.horsnell@ARM.com#endif//__CPU_O3_DYN_INST_IMPL_HH__
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