dyn_inst.hh revision 9532:01f0fac41c84
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 */ 42 43#ifndef __CPU_O3_DYN_INST_HH__ 44#define __CPU_O3_DYN_INST_HH__ 45 46#include "arch/isa_traits.hh" 47#include "config/the_isa.hh" 48#include "cpu/o3/cpu.hh" 49#include "cpu/o3/isa_specific.hh" 50#include "cpu/base_dyn_inst.hh" 51#include "cpu/inst_seq.hh" 52 53class Packet; 54 55/** 56 * Mostly implementation & ISA specific AlphaDynInst. As with most 57 * other classes in the new CPU model, it is templated on the Impl to 58 * allow for passing in of all types, such as the CPU type and the ISA 59 * type. The AlphaDynInst serves as the primary interface to the CPU 60 * for instructions that are executing. 61 */ 62template <class Impl> 63class BaseO3DynInst : public BaseDynInst<Impl> 64{ 65 public: 66 /** Typedef for the CPU. */ 67 typedef typename Impl::O3CPU O3CPU; 68 69 /** Binary machine instruction type. */ 70 typedef TheISA::MachInst MachInst; 71 /** Extended machine instruction type. */ 72 typedef TheISA::ExtMachInst ExtMachInst; 73 /** Logical register index type. */ 74 typedef TheISA::RegIndex RegIndex; 75 /** Integer register index type. */ 76 typedef TheISA::IntReg IntReg; 77 typedef TheISA::FloatReg FloatReg; 78 typedef TheISA::FloatRegBits FloatRegBits; 79 /** Misc register index type. */ 80 typedef TheISA::MiscReg MiscReg; 81 82 enum { 83 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs 84 MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs 85 }; 86 87 public: 88 /** BaseDynInst constructor given a binary instruction. */ 89 BaseO3DynInst(StaticInstPtr staticInst, StaticInstPtr macroop, 90 TheISA::PCState pc, TheISA::PCState predPC, 91 InstSeqNum seq_num, O3CPU *cpu); 92 93 /** BaseDynInst constructor given a static inst pointer. */ 94 BaseO3DynInst(StaticInstPtr _staticInst, StaticInstPtr _macroop); 95 96 ~BaseO3DynInst(); 97 98 /** Executes the instruction.*/ 99 Fault execute(); 100 101 /** Initiates the access. Only valid for memory operations. */ 102 Fault initiateAcc(); 103 104 /** Completes the access. Only valid for memory operations. */ 105 Fault completeAcc(PacketPtr pkt); 106 107 private: 108 /** Initializes variables. */ 109 void initVars(); 110 111 protected: 112 /** Values to be written to the destination misc. registers. */ 113 MiscReg _destMiscRegVal[TheISA::MaxMiscDestRegs]; 114 115 /** Indexes of the destination misc. registers. They are needed to defer 116 * the write accesses to the misc. registers until the commit stage, when 117 * the instruction is out of its speculative state. 118 */ 119 short _destMiscRegIdx[TheISA::MaxMiscDestRegs]; 120 121 /** Number of destination misc. registers. */ 122 uint8_t _numDestMiscRegs; 123 124 125 public: 126#if TRACING_ON 127 /** Tick records used for the pipeline activity viewer. */ 128 Tick fetchTick; // instruction fetch is completed. 129 int32_t decodeTick; // instruction enters decode phase 130 int32_t renameTick; // instruction enters rename phase 131 int32_t dispatchTick; 132 int32_t issueTick; 133 int32_t completeTick; 134 int32_t commitTick; 135 int32_t storeTick; 136#endif 137 138 /** Reads a misc. register, including any side-effects the read 139 * might have as defined by the architecture. 140 */ 141 MiscReg readMiscReg(int misc_reg) 142 { 143 return this->cpu->readMiscReg(misc_reg, this->threadNumber); 144 } 145 146 /** Sets a misc. register, including any side-effects the write 147 * might have as defined by the architecture. 148 */ 149 void setMiscReg(int misc_reg, const MiscReg &val) 150 { 151 /** Writes to misc. registers are recorded and deferred until the 152 * commit stage, when updateMiscRegs() is called. First, check if 153 * the misc reg has been written before and update its value to be 154 * committed instead of making a new entry. If not, make a new 155 * entry and record the write. 156 */ 157 for (int idx = 0; idx < _numDestMiscRegs; idx++) { 158 if (_destMiscRegIdx[idx] == misc_reg) { 159 _destMiscRegVal[idx] = val; 160 return; 161 } 162 } 163 164 assert(_numDestMiscRegs < TheISA::MaxMiscDestRegs); 165 _destMiscRegIdx[_numDestMiscRegs] = misc_reg; 166 _destMiscRegVal[_numDestMiscRegs] = val; 167 _numDestMiscRegs++; 168 } 169 170 /** Reads a misc. register, including any side-effects the read 171 * might have as defined by the architecture. 172 */ 173 TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx) 174 { 175 return this->cpu->readMiscReg( 176 si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag, 177 this->threadNumber); 178 } 179 180 /** Sets a misc. register, including any side-effects the write 181 * might have as defined by the architecture. 182 */ 183 void setMiscRegOperand(const StaticInst *si, int idx, 184 const MiscReg &val) 185 { 186 int misc_reg = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 187 setMiscReg(misc_reg, val); 188 } 189 190 /** Called at the commit stage to update the misc. registers. */ 191 void updateMiscRegs() 192 { 193 // @todo: Pretty convoluted way to avoid squashing from happening when 194 // using the TC during an instruction's execution (specifically for 195 // instructions that have side-effects that use the TC). Fix this. 196 // See cpu/o3/dyn_inst_impl.hh. 197 bool no_squash_from_TC = this->thread->noSquashFromTC; 198 this->thread->noSquashFromTC = true; 199 200 for (int i = 0; i < _numDestMiscRegs; i++) 201 this->cpu->setMiscReg( 202 _destMiscRegIdx[i], _destMiscRegVal[i], this->threadNumber); 203 204 this->thread->noSquashFromTC = no_squash_from_TC; 205 } 206 207 void forwardOldRegs() 208 { 209 210 for (int idx = 0; idx < this->numDestRegs(); idx++) { 211 PhysRegIndex prev_phys_reg = this->prevDestRegIdx(idx); 212 TheISA::RegIndex original_dest_reg = this->staticInst->destRegIdx(idx); 213 if (original_dest_reg < TheISA::FP_Base_DepTag) 214 this->setIntRegOperand(this->staticInst.get(), idx, this->cpu->readIntReg(prev_phys_reg)); 215 else if (original_dest_reg < TheISA::Ctrl_Base_DepTag) 216 this->setFloatRegOperandBits(this->staticInst.get(), idx, this->cpu->readFloatRegBits(prev_phys_reg)); 217 } 218 } 219 /** Calls hardware return from error interrupt. */ 220 Fault hwrei(); 221 /** Traps to handle specified fault. */ 222 void trap(Fault fault); 223 bool simPalCheck(int palFunc); 224 225 /** Emulates a syscall. */ 226 void syscall(int64_t callnum); 227 228 public: 229 230 // The register accessor methods provide the index of the 231 // instruction's operand (e.g., 0 or 1), not the architectural 232 // register index, to simplify the implementation of register 233 // renaming. We find the architectural register index by indexing 234 // into the instruction's own operand index table. Note that a 235 // raw pointer to the StaticInst is provided instead of a 236 // ref-counted StaticInstPtr to redice overhead. This is fine as 237 // long as these methods don't copy the pointer into any long-term 238 // storage (which is pretty hard to imagine they would have reason 239 // to do). 240 241 uint64_t readIntRegOperand(const StaticInst *si, int idx) 242 { 243 return this->cpu->readIntReg(this->_srcRegIdx[idx]); 244 } 245 246 FloatReg readFloatRegOperand(const StaticInst *si, int idx) 247 { 248 return this->cpu->readFloatReg(this->_srcRegIdx[idx]); 249 } 250 251 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 252 { 253 return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]); 254 } 255 256 /** @todo: Make results into arrays so they can handle multiple dest 257 * registers. 258 */ 259 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 260 { 261 this->cpu->setIntReg(this->_destRegIdx[idx], val); 262 BaseDynInst<Impl>::setIntRegOperand(si, idx, val); 263 } 264 265 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 266 { 267 this->cpu->setFloatReg(this->_destRegIdx[idx], val); 268 BaseDynInst<Impl>::setFloatRegOperand(si, idx, val); 269 } 270 271 void setFloatRegOperandBits(const StaticInst *si, int idx, 272 FloatRegBits val) 273 { 274 this->cpu->setFloatRegBits(this->_destRegIdx[idx], val); 275 BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val); 276 } 277 278#if THE_ISA == MIPS_ISA 279 uint64_t readRegOtherThread(int misc_reg) 280 { 281 panic("MIPS MT not defined for O3 CPU.\n"); 282 return 0; 283 } 284 285 void setRegOtherThread(int misc_reg, const TheISA::MiscReg &val) 286 { 287 panic("MIPS MT not defined for O3 CPU.\n"); 288 } 289#endif 290 291 public: 292 /** Calculates EA part of a memory instruction. Currently unused, 293 * though it may be useful in the future if we want to split 294 * memory operations into EA calculation and memory access parts. 295 */ 296 Fault calcEA() 297 { 298 return this->staticInst->eaCompInst()->execute(this, this->traceData); 299 } 300 301 /** Does the memory access part of a memory instruction. Currently unused, 302 * though it may be useful in the future if we want to split 303 * memory operations into EA calculation and memory access parts. 304 */ 305 Fault memAccess() 306 { 307 return this->staticInst->memAccInst()->execute(this, this->traceData); 308 } 309}; 310 311#endif // __CPU_O3_ALPHA_DYN_INST_HH__ 312 313