dyn_inst.hh revision 9382:1c97b57d5169
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 */ 42 43#ifndef __CPU_O3_DYN_INST_HH__ 44#define __CPU_O3_DYN_INST_HH__ 45 46#include "arch/isa_traits.hh" 47#include "config/the_isa.hh" 48#include "cpu/o3/cpu.hh" 49#include "cpu/o3/isa_specific.hh" 50#include "cpu/base_dyn_inst.hh" 51#include "cpu/inst_seq.hh" 52 53class Packet; 54 55/** 56 * Mostly implementation & ISA specific AlphaDynInst. As with most 57 * other classes in the new CPU model, it is templated on the Impl to 58 * allow for passing in of all types, such as the CPU type and the ISA 59 * type. The AlphaDynInst serves as the primary interface to the CPU 60 * for instructions that are executing. 61 */ 62template <class Impl> 63class BaseO3DynInst : public BaseDynInst<Impl> 64{ 65 public: 66 /** Typedef for the CPU. */ 67 typedef typename Impl::O3CPU O3CPU; 68 69 /** Binary machine instruction type. */ 70 typedef TheISA::MachInst MachInst; 71 /** Extended machine instruction type. */ 72 typedef TheISA::ExtMachInst ExtMachInst; 73 /** Logical register index type. */ 74 typedef TheISA::RegIndex RegIndex; 75 /** Integer register index type. */ 76 typedef TheISA::IntReg IntReg; 77 typedef TheISA::FloatReg FloatReg; 78 typedef TheISA::FloatRegBits FloatRegBits; 79 /** Misc register index type. */ 80 typedef TheISA::MiscReg MiscReg; 81 82 enum { 83 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs 84 MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs 85 }; 86 87 public: 88 /** BaseDynInst constructor given a binary instruction. */ 89 BaseO3DynInst(StaticInstPtr staticInst, StaticInstPtr macroop, 90 TheISA::PCState pc, TheISA::PCState predPC, 91 InstSeqNum seq_num, O3CPU *cpu); 92 93 /** BaseDynInst constructor given a static inst pointer. */ 94 BaseO3DynInst(StaticInstPtr _staticInst, StaticInstPtr _macroop); 95 96 ~BaseO3DynInst(); 97 98 /** Executes the instruction.*/ 99 Fault execute(); 100 101 /** Initiates the access. Only valid for memory operations. */ 102 Fault initiateAcc(); 103 104 /** Completes the access. Only valid for memory operations. */ 105 Fault completeAcc(PacketPtr pkt); 106 107 private: 108 /** Initializes variables. */ 109 void initVars(); 110 111 protected: 112 /** Values to be written to the destination misc. registers. */ 113 MiscReg _destMiscRegVal[TheISA::MaxMiscDestRegs]; 114 115 /** Indexes of the destination misc. registers. They are needed to defer 116 * the write accesses to the misc. registers until the commit stage, when 117 * the instruction is out of its speculative state. 118 */ 119 short _destMiscRegIdx[TheISA::MaxMiscDestRegs]; 120 121 /** Number of destination misc. registers. */ 122 uint8_t _numDestMiscRegs; 123 124 125 public: 126#if TRACING_ON 127 /** Tick records used for the pipeline activity viewer. */ 128 Tick fetchTick; // instruction fetch is completed. 129 int32_t decodeTick; // instruction enters decode phase 130 int32_t renameTick; // instruction enters rename phase 131 int32_t dispatchTick; 132 int32_t issueTick; 133 int32_t completeTick; 134 int32_t commitTick; 135#endif 136 137 /** Reads a misc. register, including any side-effects the read 138 * might have as defined by the architecture. 139 */ 140 MiscReg readMiscReg(int misc_reg) 141 { 142 return this->cpu->readMiscReg(misc_reg, this->threadNumber); 143 } 144 145 /** Sets a misc. register, including any side-effects the write 146 * might have as defined by the architecture. 147 */ 148 void setMiscReg(int misc_reg, const MiscReg &val) 149 { 150 /** Writes to misc. registers are recorded and deferred until the 151 * commit stage, when updateMiscRegs() is called. 152 */ 153 assert(_numDestMiscRegs < TheISA::MaxMiscDestRegs); 154 _destMiscRegIdx[_numDestMiscRegs] = misc_reg; 155 _destMiscRegVal[_numDestMiscRegs] = val; 156 _numDestMiscRegs++; 157 } 158 159 /** Reads a misc. register, including any side-effects the read 160 * might have as defined by the architecture. 161 */ 162 TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx) 163 { 164 return this->cpu->readMiscReg( 165 si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag, 166 this->threadNumber); 167 } 168 169 /** Sets a misc. register, including any side-effects the write 170 * might have as defined by the architecture. 171 */ 172 void setMiscRegOperand(const StaticInst *si, int idx, 173 const MiscReg &val) 174 { 175 int misc_reg = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 176 setMiscReg(misc_reg, val); 177 } 178 179 /** Called at the commit stage to update the misc. registers. */ 180 void updateMiscRegs() 181 { 182 // @todo: Pretty convoluted way to avoid squashing from happening when 183 // using the TC during an instruction's execution (specifically for 184 // instructions that have side-effects that use the TC). Fix this. 185 // See cpu/o3/dyn_inst_impl.hh. 186 bool no_squash_from_TC = this->thread->noSquashFromTC; 187 this->thread->noSquashFromTC = true; 188 189 for (int i = 0; i < _numDestMiscRegs; i++) 190 this->cpu->setMiscReg( 191 _destMiscRegIdx[i], _destMiscRegVal[i], this->threadNumber); 192 193 this->thread->noSquashFromTC = no_squash_from_TC; 194 } 195 196 void forwardOldRegs() 197 { 198 199 for (int idx = 0; idx < this->numDestRegs(); idx++) { 200 PhysRegIndex prev_phys_reg = this->prevDestRegIdx(idx); 201 TheISA::RegIndex original_dest_reg = this->staticInst->destRegIdx(idx); 202 if (original_dest_reg < TheISA::FP_Base_DepTag) 203 this->setIntRegOperand(this->staticInst.get(), idx, this->cpu->readIntReg(prev_phys_reg)); 204 else if (original_dest_reg < TheISA::Ctrl_Base_DepTag) 205 this->setFloatRegOperandBits(this->staticInst.get(), idx, this->cpu->readFloatRegBits(prev_phys_reg)); 206 } 207 } 208 /** Calls hardware return from error interrupt. */ 209 Fault hwrei(); 210 /** Traps to handle specified fault. */ 211 void trap(Fault fault); 212 bool simPalCheck(int palFunc); 213 214 /** Emulates a syscall. */ 215 void syscall(int64_t callnum); 216 217 public: 218 219 // The register accessor methods provide the index of the 220 // instruction's operand (e.g., 0 or 1), not the architectural 221 // register index, to simplify the implementation of register 222 // renaming. We find the architectural register index by indexing 223 // into the instruction's own operand index table. Note that a 224 // raw pointer to the StaticInst is provided instead of a 225 // ref-counted StaticInstPtr to redice overhead. This is fine as 226 // long as these methods don't copy the pointer into any long-term 227 // storage (which is pretty hard to imagine they would have reason 228 // to do). 229 230 uint64_t readIntRegOperand(const StaticInst *si, int idx) 231 { 232 return this->cpu->readIntReg(this->_srcRegIdx[idx]); 233 } 234 235 FloatReg readFloatRegOperand(const StaticInst *si, int idx) 236 { 237 return this->cpu->readFloatReg(this->_srcRegIdx[idx]); 238 } 239 240 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 241 { 242 return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]); 243 } 244 245 /** @todo: Make results into arrays so they can handle multiple dest 246 * registers. 247 */ 248 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 249 { 250 this->cpu->setIntReg(this->_destRegIdx[idx], val); 251 BaseDynInst<Impl>::setIntRegOperand(si, idx, val); 252 } 253 254 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 255 { 256 this->cpu->setFloatReg(this->_destRegIdx[idx], val); 257 BaseDynInst<Impl>::setFloatRegOperand(si, idx, val); 258 } 259 260 void setFloatRegOperandBits(const StaticInst *si, int idx, 261 FloatRegBits val) 262 { 263 this->cpu->setFloatRegBits(this->_destRegIdx[idx], val); 264 BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val); 265 } 266 267#if THE_ISA == MIPS_ISA 268 uint64_t readRegOtherThread(int misc_reg) 269 { 270 panic("MIPS MT not defined for O3 CPU.\n"); 271 return 0; 272 } 273 274 void setRegOtherThread(int misc_reg, const TheISA::MiscReg &val) 275 { 276 panic("MIPS MT not defined for O3 CPU.\n"); 277 } 278#endif 279 280 public: 281 /** Calculates EA part of a memory instruction. Currently unused, 282 * though it may be useful in the future if we want to split 283 * memory operations into EA calculation and memory access parts. 284 */ 285 Fault calcEA() 286 { 287 return this->staticInst->eaCompInst()->execute(this, this->traceData); 288 } 289 290 /** Does the memory access part of a memory instruction. Currently unused, 291 * though it may be useful in the future if we want to split 292 * memory operations into EA calculation and memory access parts. 293 */ 294 Fault memAccess() 295 { 296 return this->staticInst->memAccInst()->execute(this, this->traceData); 297 } 298}; 299 300#endif // __CPU_O3_ALPHA_DYN_INST_HH__ 301 302