dyn_inst.hh revision 9046:a1104cc13db2
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 */ 42 43#ifndef __CPU_O3_DYN_INST_HH__ 44#define __CPU_O3_DYN_INST_HH__ 45 46#include "arch/isa_traits.hh" 47#include "config/the_isa.hh" 48#include "cpu/o3/cpu.hh" 49#include "cpu/o3/isa_specific.hh" 50#include "cpu/base_dyn_inst.hh" 51#include "cpu/inst_seq.hh" 52 53class Packet; 54 55/** 56 * Mostly implementation & ISA specific AlphaDynInst. As with most 57 * other classes in the new CPU model, it is templated on the Impl to 58 * allow for passing in of all types, such as the CPU type and the ISA 59 * type. The AlphaDynInst serves as the primary interface to the CPU 60 * for instructions that are executing. 61 */ 62template <class Impl> 63class BaseO3DynInst : public BaseDynInst<Impl> 64{ 65 public: 66 /** Typedef for the CPU. */ 67 typedef typename Impl::O3CPU O3CPU; 68 69 /** Binary machine instruction type. */ 70 typedef TheISA::MachInst MachInst; 71 /** Extended machine instruction type. */ 72 typedef TheISA::ExtMachInst ExtMachInst; 73 /** Logical register index type. */ 74 typedef TheISA::RegIndex RegIndex; 75 /** Integer register index type. */ 76 typedef TheISA::IntReg IntReg; 77 typedef TheISA::FloatReg FloatReg; 78 typedef TheISA::FloatRegBits FloatRegBits; 79 /** Misc register index type. */ 80 typedef TheISA::MiscReg MiscReg; 81 82 enum { 83 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs 84 MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs 85 }; 86 87 public: 88 /** BaseDynInst constructor given a binary instruction. */ 89 BaseO3DynInst(StaticInstPtr staticInst, StaticInstPtr macroop, 90 TheISA::PCState pc, TheISA::PCState predPC, 91 InstSeqNum seq_num, O3CPU *cpu); 92 93 /** BaseDynInst constructor given a static inst pointer. */ 94 BaseO3DynInst(StaticInstPtr _staticInst, StaticInstPtr _macroop); 95 96 /** Executes the instruction.*/ 97 Fault execute(); 98 99 /** Initiates the access. Only valid for memory operations. */ 100 Fault initiateAcc(); 101 102 /** Completes the access. Only valid for memory operations. */ 103 Fault completeAcc(PacketPtr pkt); 104 105 private: 106 /** Initializes variables. */ 107 void initVars(); 108 109 protected: 110 /** Values to be written to the destination misc. registers. */ 111 MiscReg _destMiscRegVal[TheISA::MaxMiscDestRegs]; 112 113 /** Indexes of the destination misc. registers. They are needed to defer 114 * the write accesses to the misc. registers until the commit stage, when 115 * the instruction is out of its speculative state. 116 */ 117 short _destMiscRegIdx[TheISA::MaxMiscDestRegs]; 118 119 /** Number of destination misc. registers. */ 120 uint8_t _numDestMiscRegs; 121 122 123 public: 124#if TRACING_ON 125 /** Tick records used for the pipeline activity viewer. */ 126 Tick fetchTick; 127 uint32_t decodeTick; 128 uint32_t renameTick; 129 uint32_t dispatchTick; 130 uint32_t issueTick; 131 uint32_t completeTick; 132#endif 133 134 /** Reads a misc. register, including any side-effects the read 135 * might have as defined by the architecture. 136 */ 137 MiscReg readMiscReg(int misc_reg) 138 { 139 return this->cpu->readMiscReg(misc_reg, this->threadNumber); 140 } 141 142 /** Sets a misc. register, including any side-effects the write 143 * might have as defined by the architecture. 144 */ 145 void setMiscReg(int misc_reg, const MiscReg &val) 146 { 147 /** Writes to misc. registers are recorded and deferred until the 148 * commit stage, when updateMiscRegs() is called. 149 */ 150 assert(_numDestMiscRegs < TheISA::MaxMiscDestRegs); 151 _destMiscRegIdx[_numDestMiscRegs] = misc_reg; 152 _destMiscRegVal[_numDestMiscRegs] = val; 153 _numDestMiscRegs++; 154 } 155 156 /** Reads a misc. register, including any side-effects the read 157 * might have as defined by the architecture. 158 */ 159 TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx) 160 { 161 return this->cpu->readMiscReg( 162 si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag, 163 this->threadNumber); 164 } 165 166 /** Sets a misc. register, including any side-effects the write 167 * might have as defined by the architecture. 168 */ 169 void setMiscRegOperand(const StaticInst *si, int idx, 170 const MiscReg &val) 171 { 172 int misc_reg = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 173 setMiscReg(misc_reg, val); 174 } 175 176 /** Called at the commit stage to update the misc. registers. */ 177 void updateMiscRegs() 178 { 179 // @todo: Pretty convoluted way to avoid squashing from happening when 180 // using the TC during an instruction's execution (specifically for 181 // instructions that have side-effects that use the TC). Fix this. 182 // See cpu/o3/dyn_inst_impl.hh. 183 bool in_syscall = this->thread->inSyscall; 184 this->thread->inSyscall = true; 185 186 for (int i = 0; i < _numDestMiscRegs; i++) 187 this->cpu->setMiscReg( 188 _destMiscRegIdx[i], _destMiscRegVal[i], this->threadNumber); 189 190 this->thread->inSyscall = in_syscall; 191 } 192 193 void forwardOldRegs() 194 { 195 196 for (int idx = 0; idx < this->numDestRegs(); idx++) { 197 PhysRegIndex prev_phys_reg = this->prevDestRegIdx(idx); 198 TheISA::RegIndex original_dest_reg = this->staticInst->destRegIdx(idx); 199 if (original_dest_reg < TheISA::FP_Base_DepTag) 200 this->setIntRegOperand(this->staticInst.get(), idx, this->cpu->readIntReg(prev_phys_reg)); 201 else if (original_dest_reg < TheISA::Ctrl_Base_DepTag) 202 this->setFloatRegOperandBits(this->staticInst.get(), idx, this->cpu->readFloatRegBits(prev_phys_reg)); 203 } 204 } 205 /** Calls hardware return from error interrupt. */ 206 Fault hwrei(); 207 /** Traps to handle specified fault. */ 208 void trap(Fault fault); 209 bool simPalCheck(int palFunc); 210 211 /** Emulates a syscall. */ 212 void syscall(int64_t callnum); 213 214 public: 215 216 // The register accessor methods provide the index of the 217 // instruction's operand (e.g., 0 or 1), not the architectural 218 // register index, to simplify the implementation of register 219 // renaming. We find the architectural register index by indexing 220 // into the instruction's own operand index table. Note that a 221 // raw pointer to the StaticInst is provided instead of a 222 // ref-counted StaticInstPtr to redice overhead. This is fine as 223 // long as these methods don't copy the pointer into any long-term 224 // storage (which is pretty hard to imagine they would have reason 225 // to do). 226 227 uint64_t readIntRegOperand(const StaticInst *si, int idx) 228 { 229 return this->cpu->readIntReg(this->_srcRegIdx[idx]); 230 } 231 232 FloatReg readFloatRegOperand(const StaticInst *si, int idx) 233 { 234 return this->cpu->readFloatReg(this->_srcRegIdx[idx]); 235 } 236 237 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 238 { 239 return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]); 240 } 241 242 /** @todo: Make results into arrays so they can handle multiple dest 243 * registers. 244 */ 245 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 246 { 247 this->cpu->setIntReg(this->_destRegIdx[idx], val); 248 BaseDynInst<Impl>::setIntRegOperand(si, idx, val); 249 } 250 251 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 252 { 253 this->cpu->setFloatReg(this->_destRegIdx[idx], val); 254 BaseDynInst<Impl>::setFloatRegOperand(si, idx, val); 255 } 256 257 void setFloatRegOperandBits(const StaticInst *si, int idx, 258 FloatRegBits val) 259 { 260 this->cpu->setFloatRegBits(this->_destRegIdx[idx], val); 261 BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val); 262 } 263 264#if THE_ISA == MIPS_ISA 265 uint64_t readRegOtherThread(int misc_reg) 266 { 267 panic("MIPS MT not defined for O3 CPU.\n"); 268 return 0; 269 } 270 271 void setRegOtherThread(int misc_reg, const TheISA::MiscReg &val) 272 { 273 panic("MIPS MT not defined for O3 CPU.\n"); 274 } 275#endif 276 277 public: 278 /** Calculates EA part of a memory instruction. Currently unused, 279 * though it may be useful in the future if we want to split 280 * memory operations into EA calculation and memory access parts. 281 */ 282 Fault calcEA() 283 { 284 return this->staticInst->eaCompInst()->execute(this, this->traceData); 285 } 286 287 /** Does the memory access part of a memory instruction. Currently unused, 288 * though it may be useful in the future if we want to split 289 * memory operations into EA calculation and memory access parts. 290 */ 291 Fault memAccess() 292 { 293 return this->staticInst->memAccInst()->execute(this, this->traceData); 294 } 295}; 296 297#endif // __CPU_O3_ALPHA_DYN_INST_HH__ 298 299