dyn_inst.hh revision 13830:b5d6aa6c0e99
17170Sgblack@eecs.umich.edu/* 210339Smitch.hayenga@arm.com * Copyright (c) 2010, 2016 ARM Limited 37170Sgblack@eecs.umich.edu * Copyright (c) 2013 Advanced Micro Devices, Inc. 47170Sgblack@eecs.umich.edu * All rights reserved 57170Sgblack@eecs.umich.edu * 67170Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 77170Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 87170Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 97170Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 107170Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 117170Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 127170Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 137170Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 147170Sgblack@eecs.umich.edu * 157170Sgblack@eecs.umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 167170Sgblack@eecs.umich.edu * All rights reserved. 177170Sgblack@eecs.umich.edu * 187170Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 197170Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 207170Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 217170Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 227170Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 237170Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 247170Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 257170Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 267170Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 277170Sgblack@eecs.umich.edu * this software without specific prior written permission. 287170Sgblack@eecs.umich.edu * 297170Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 307170Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 317170Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 327170Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 337170Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 347170Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 357170Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 367170Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 377170Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 387170Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 397170Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 407170Sgblack@eecs.umich.edu * 417170Sgblack@eecs.umich.edu * Authors: Kevin Lim 427170Sgblack@eecs.umich.edu */ 4311793Sbrandon.potter@amd.com 4411793Sbrandon.potter@amd.com#ifndef __CPU_O3_DYN_INST_HH__ 458229Snate@binkert.org#define __CPU_O3_DYN_INST_HH__ 468229Snate@binkert.org 478961Sgblack@eecs.umich.edu#include <array> 4810037SARM gem5 Developers 497170Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 507853SMatt.Horsnell@ARM.com#include "config/the_isa.hh" 517170Sgblack@eecs.umich.edu#include "cpu/o3/cpu.hh" 527170Sgblack@eecs.umich.edu#include "cpu/o3/isa_specific.hh" 537170Sgblack@eecs.umich.edu#include "cpu/base_dyn_inst.hh" 547170Sgblack@eecs.umich.edu#include "cpu/inst_seq.hh" 557170Sgblack@eecs.umich.edu#include "cpu/reg_class.hh" 567170Sgblack@eecs.umich.edu 577170Sgblack@eecs.umich.educlass Packet; 587170Sgblack@eecs.umich.edu 597170Sgblack@eecs.umich.edutemplate <class Impl> 607170Sgblack@eecs.umich.educlass BaseO3DynInst : public BaseDynInst<Impl> 617170Sgblack@eecs.umich.edu{ 627170Sgblack@eecs.umich.edu public: 637170Sgblack@eecs.umich.edu /** Typedef for the CPU. */ 6410346Smitch.hayenga@arm.com typedef typename Impl::O3CPU O3CPU; 658148SAli.Saidi@ARM.com 6610346Smitch.hayenga@arm.com /** Binary machine instruction type. */ 6710346Smitch.hayenga@arm.com typedef TheISA::MachInst MachInst; 6810346Smitch.hayenga@arm.com /** Register types. */ 6910346Smitch.hayenga@arm.com using VecRegContainer = TheISA::VecRegContainer; 7010346Smitch.hayenga@arm.com using VecElem = TheISA::VecElem; 7110346Smitch.hayenga@arm.com static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg; 7210346Smitch.hayenga@arm.com using VecPredRegContainer = TheISA::VecPredRegContainer; 7310346Smitch.hayenga@arm.com 748148SAli.Saidi@ARM.com enum { 7510346Smitch.hayenga@arm.com MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs 7610346Smitch.hayenga@arm.com MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs 7710346Smitch.hayenga@arm.com }; 7810346Smitch.hayenga@arm.com 7910346Smitch.hayenga@arm.com public: 8010346Smitch.hayenga@arm.com /** BaseDynInst constructor given a binary instruction. */ 8110346Smitch.hayenga@arm.com BaseO3DynInst(const StaticInstPtr &staticInst, const StaticInstPtr 8210346Smitch.hayenga@arm.com ¯oop, TheISA::PCState pc, TheISA::PCState predPC, 8310346Smitch.hayenga@arm.com InstSeqNum seq_num, O3CPU *cpu); 848148SAli.Saidi@ARM.com 857170Sgblack@eecs.umich.edu /** BaseDynInst constructor given a static inst pointer. */ 8610346Smitch.hayenga@arm.com BaseO3DynInst(const StaticInstPtr &_staticInst, 877170Sgblack@eecs.umich.edu const StaticInstPtr &_macroop); 887170Sgblack@eecs.umich.edu 897170Sgblack@eecs.umich.edu ~BaseO3DynInst(); 907170Sgblack@eecs.umich.edu 917170Sgblack@eecs.umich.edu /** Executes the instruction.*/ 927170Sgblack@eecs.umich.edu Fault execute(); 937170Sgblack@eecs.umich.edu 947170Sgblack@eecs.umich.edu /** Initiates the access. Only valid for memory operations. */ 957190Sgblack@eecs.umich.edu Fault initiateAcc(); 967190Sgblack@eecs.umich.edu 977170Sgblack@eecs.umich.edu /** Completes the access. Only valid for memory operations. */ 987170Sgblack@eecs.umich.edu Fault completeAcc(PacketPtr pkt); 9910346Smitch.hayenga@arm.com 10010346Smitch.hayenga@arm.com private: 1017190Sgblack@eecs.umich.edu /** Initializes variables. */ 1027170Sgblack@eecs.umich.edu void initVars(); 10310346Smitch.hayenga@arm.com 10410346Smitch.hayenga@arm.com protected: 10510346Smitch.hayenga@arm.com /** Explicitation of dependent names. */ 10610346Smitch.hayenga@arm.com using BaseDynInst<Impl>::cpu; 10710346Smitch.hayenga@arm.com using BaseDynInst<Impl>::_srcRegIdx; 10810346Smitch.hayenga@arm.com using BaseDynInst<Impl>::_destRegIdx; 10910346Smitch.hayenga@arm.com 11010346Smitch.hayenga@arm.com /** Values to be written to the destination misc. registers. */ 1117170Sgblack@eecs.umich.edu std::array<RegVal, TheISA::MaxMiscDestRegs> _destMiscRegVal; 11210346Smitch.hayenga@arm.com 11310346Smitch.hayenga@arm.com /** Indexes of the destination misc. registers. They are needed to defer 11410346Smitch.hayenga@arm.com * the write accesses to the misc. registers until the commit stage, when 11510346Smitch.hayenga@arm.com * the instruction is out of its speculative state. 1167170Sgblack@eecs.umich.edu */ 11710346Smitch.hayenga@arm.com std::array<short, TheISA::MaxMiscDestRegs> _destMiscRegIdx; 11810346Smitch.hayenga@arm.com 11910346Smitch.hayenga@arm.com /** Number of destination misc. registers. */ 12010346Smitch.hayenga@arm.com uint8_t _numDestMiscRegs; 1217170Sgblack@eecs.umich.edu 12210346Smitch.hayenga@arm.com 12310346Smitch.hayenga@arm.com public: 12410346Smitch.hayenga@arm.com#if TRACING_ON 12510346Smitch.hayenga@arm.com /** Tick records used for the pipeline activity viewer. */ 12610346Smitch.hayenga@arm.com Tick fetchTick; // instruction fetch is completed. 12710346Smitch.hayenga@arm.com int32_t decodeTick; // instruction enters decode phase 12810346Smitch.hayenga@arm.com int32_t renameTick; // instruction enters rename phase 12910346Smitch.hayenga@arm.com int32_t dispatchTick; 13010346Smitch.hayenga@arm.com int32_t issueTick; 13110346Smitch.hayenga@arm.com int32_t completeTick; 13210346Smitch.hayenga@arm.com int32_t commitTick; 13310346Smitch.hayenga@arm.com int32_t storeTick; 13410346Smitch.hayenga@arm.com#endif 13510346Smitch.hayenga@arm.com 13610346Smitch.hayenga@arm.com /** Reads a misc. register, including any side-effects the read 13710346Smitch.hayenga@arm.com * might have as defined by the architecture. 13810346Smitch.hayenga@arm.com */ 13910346Smitch.hayenga@arm.com RegVal 14010346Smitch.hayenga@arm.com readMiscReg(int misc_reg) override 14110346Smitch.hayenga@arm.com { 14210346Smitch.hayenga@arm.com return this->cpu->readMiscReg(misc_reg, this->threadNumber); 14310346Smitch.hayenga@arm.com } 14410346Smitch.hayenga@arm.com 14510346Smitch.hayenga@arm.com /** Sets a misc. register, including any side-effects the write 14610346Smitch.hayenga@arm.com * might have as defined by the architecture. 14710346Smitch.hayenga@arm.com */ 14811321Ssteve.reinhardt@amd.com void 14910346Smitch.hayenga@arm.com setMiscReg(int misc_reg, RegVal val) override 15010346Smitch.hayenga@arm.com { 15110346Smitch.hayenga@arm.com /** Writes to misc. registers are recorded and deferred until the 15210346Smitch.hayenga@arm.com * commit stage, when updateMiscRegs() is called. First, check if 15310346Smitch.hayenga@arm.com * the misc reg has been written before and update its value to be 15410346Smitch.hayenga@arm.com * committed instead of making a new entry. If not, make a new 15510346Smitch.hayenga@arm.com * entry and record the write. 15610346Smitch.hayenga@arm.com */ 15710346Smitch.hayenga@arm.com for (int idx = 0; idx < _numDestMiscRegs; idx++) { 15810346Smitch.hayenga@arm.com if (_destMiscRegIdx[idx] == misc_reg) { 15910346Smitch.hayenga@arm.com _destMiscRegVal[idx] = val; 16010346Smitch.hayenga@arm.com return; 16110346Smitch.hayenga@arm.com } 16210346Smitch.hayenga@arm.com } 16310346Smitch.hayenga@arm.com 16410346Smitch.hayenga@arm.com assert(_numDestMiscRegs < TheISA::MaxMiscDestRegs); 16510346Smitch.hayenga@arm.com _destMiscRegIdx[_numDestMiscRegs] = misc_reg; 16610346Smitch.hayenga@arm.com _destMiscRegVal[_numDestMiscRegs] = val; 16710346Smitch.hayenga@arm.com _numDestMiscRegs++; 16810346Smitch.hayenga@arm.com } 16910346Smitch.hayenga@arm.com 17010346Smitch.hayenga@arm.com /** Reads a misc. register, including any side-effects the read 17110346Smitch.hayenga@arm.com * might have as defined by the architecture. 17210346Smitch.hayenga@arm.com */ 17310346Smitch.hayenga@arm.com RegVal 1749640Snathanael.premillieu@irisa.fr readMiscRegOperand(const StaticInst *si, int idx) override 1759640Snathanael.premillieu@irisa.fr { 1769640Snathanael.premillieu@irisa.fr const RegId& reg = si->srcRegIdx(idx); 1779640Snathanael.premillieu@irisa.fr assert(reg.isMiscReg()); 1788148SAli.Saidi@ARM.com return this->cpu->readMiscReg(reg.index(), this->threadNumber); 17910346Smitch.hayenga@arm.com } 18010346Smitch.hayenga@arm.com 1817170Sgblack@eecs.umich.edu /** Sets a misc. register, including any side-effects the write 18210346Smitch.hayenga@arm.com * might have as defined by the architecture. 18310346Smitch.hayenga@arm.com */ 18410346Smitch.hayenga@arm.com void 18510346Smitch.hayenga@arm.com setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override 1867170Sgblack@eecs.umich.edu { 1877170Sgblack@eecs.umich.edu const RegId& reg = si->destRegIdx(idx); 18810346Smitch.hayenga@arm.com assert(reg.isMiscReg()); 18910346Smitch.hayenga@arm.com setMiscReg(reg.index(), val); 1907170Sgblack@eecs.umich.edu } 1917170Sgblack@eecs.umich.edu 1928148SAli.Saidi@ARM.com /** Called at the commit stage to update the misc. registers. */ 19310346Smitch.hayenga@arm.com void 1948148SAli.Saidi@ARM.com updateMiscRegs() 19510346Smitch.hayenga@arm.com { 1968148SAli.Saidi@ARM.com // @todo: Pretty convoluted way to avoid squashing from happening when 19710346Smitch.hayenga@arm.com // using the TC during an instruction's execution (specifically for 1988148SAli.Saidi@ARM.com // instructions that have side-effects that use the TC). Fix this. 19910346Smitch.hayenga@arm.com // See cpu/o3/dyn_inst_impl.hh. 20010346Smitch.hayenga@arm.com bool no_squash_from_TC = this->thread->noSquashFromTC; 20110346Smitch.hayenga@arm.com this->thread->noSquashFromTC = true; 20210346Smitch.hayenga@arm.com 20310346Smitch.hayenga@arm.com for (int i = 0; i < _numDestMiscRegs; i++) 20410346Smitch.hayenga@arm.com this->cpu->setMiscReg( 20510346Smitch.hayenga@arm.com _destMiscRegIdx[i], _destMiscRegVal[i], this->threadNumber); 20610346Smitch.hayenga@arm.com 20710346Smitch.hayenga@arm.com this->thread->noSquashFromTC = no_squash_from_TC; 20810346Smitch.hayenga@arm.com } 2099368Snathanael.premillieu@irisa.fr 2109368Snathanael.premillieu@irisa.fr void forwardOldRegs() 2119368Snathanael.premillieu@irisa.fr { 2129368Snathanael.premillieu@irisa.fr 2138148SAli.Saidi@ARM.com for (int idx = 0; idx < this->numDestRegs(); idx++) { 21410346Smitch.hayenga@arm.com PhysRegIdPtr prev_phys_reg = this->prevDestRegIdx(idx); 21510346Smitch.hayenga@arm.com const RegId& original_dest_reg = 21610346Smitch.hayenga@arm.com this->staticInst->destRegIdx(idx); 21710346Smitch.hayenga@arm.com switch (original_dest_reg.classValue()) { 2188148SAli.Saidi@ARM.com case IntRegClass: 2197170Sgblack@eecs.umich.edu this->setIntRegOperand(this->staticInst.get(), idx, 2207190Sgblack@eecs.umich.edu this->cpu->readIntReg(prev_phys_reg)); 22110346Smitch.hayenga@arm.com break; 2227190Sgblack@eecs.umich.edu case FloatRegClass: 22310666SAli.Saidi@ARM.com this->setFloatRegOperandBits(this->staticInst.get(), idx, 2247343Sgblack@eecs.umich.edu this->cpu->readFloatReg(prev_phys_reg)); 22510199SAndrew.Bardsley@arm.com break; 22610199SAndrew.Bardsley@arm.com case VecRegClass: 22710199SAndrew.Bardsley@arm.com this->setVecRegOperand(this->staticInst.get(), idx, 22810199SAndrew.Bardsley@arm.com this->cpu->readVecReg(prev_phys_reg)); 22910199SAndrew.Bardsley@arm.com break; 23010346Smitch.hayenga@arm.com case VecElemClass: 23110346Smitch.hayenga@arm.com this->setVecElemOperand(this->staticInst.get(), idx, 23210199SAndrew.Bardsley@arm.com this->cpu->readVecElem(prev_phys_reg)); 23310199SAndrew.Bardsley@arm.com break; 23410199SAndrew.Bardsley@arm.com case VecPredRegClass: 23510199SAndrew.Bardsley@arm.com this->setVecPredRegOperand(this->staticInst.get(), idx, 23610199SAndrew.Bardsley@arm.com this->cpu->readVecPredReg(prev_phys_reg)); 23710346Smitch.hayenga@arm.com break; 23810346Smitch.hayenga@arm.com case CCRegClass: 2397343Sgblack@eecs.umich.edu this->setCCRegOperand(this->staticInst.get(), idx, 2407170Sgblack@eecs.umich.edu this->cpu->readCCReg(prev_phys_reg)); 2417170Sgblack@eecs.umich.edu break; 24210037SARM gem5 Developers case MiscRegClass: 24310037SARM gem5 Developers // no need to forward misc reg values 24410037SARM gem5 Developers break; 24510037SARM gem5 Developers default: 24610037SARM gem5 Developers panic("Unknown register class: %d", 24710037SARM gem5 Developers (int)original_dest_reg.classValue()); 24810037SARM gem5 Developers } 24910346Smitch.hayenga@arm.com } 25010037SARM gem5 Developers } 25110346Smitch.hayenga@arm.com /** Calls hardware return from error interrupt. */ 25210346Smitch.hayenga@arm.com Fault hwrei() override; 25310346Smitch.hayenga@arm.com /** Traps to handle specified fault. */ 25410346Smitch.hayenga@arm.com void trap(const Fault &fault); 25510346Smitch.hayenga@arm.com bool simPalCheck(int palFunc) override; 25610346Smitch.hayenga@arm.com 25710346Smitch.hayenga@arm.com /** Emulates a syscall. */ 25810037SARM gem5 Developers void syscall(int64_t callnum, Fault *fault) override; 25910037SARM gem5 Developers 26010037SARM gem5 Developers public: 26110037SARM gem5 Developers 26210037SARM gem5 Developers // The register accessor methods provide the index of the 26310037SARM gem5 Developers // instruction's operand (e.g., 0 or 1), not the architectural 26410346Smitch.hayenga@arm.com // register index, to simplify the implementation of register 26510346Smitch.hayenga@arm.com // renaming. We find the architectural register index by indexing 26610346Smitch.hayenga@arm.com // into the instruction's own operand index table. Note that a 26710346Smitch.hayenga@arm.com // raw pointer to the StaticInst is provided instead of a 26810037SARM gem5 Developers // ref-counted StaticInstPtr to redice overhead. This is fine as 26910037SARM gem5 Developers // long as these methods don't copy the pointer into any long-term 27010037SARM gem5 Developers // storage (which is pretty hard to imagine they would have reason 27110037SARM gem5 Developers // to do). 27210346Smitch.hayenga@arm.com 27310346Smitch.hayenga@arm.com RegVal 27410346Smitch.hayenga@arm.com readIntRegOperand(const StaticInst *si, int idx) override 27510346Smitch.hayenga@arm.com { 27610037SARM gem5 Developers return this->cpu->readIntReg(this->_srcRegIdx[idx]); 27710346Smitch.hayenga@arm.com } 27810346Smitch.hayenga@arm.com 27910346Smitch.hayenga@arm.com RegVal 28010346Smitch.hayenga@arm.com readFloatRegOperandBits(const StaticInst *si, int idx) override 28110346Smitch.hayenga@arm.com { 28210346Smitch.hayenga@arm.com return this->cpu->readFloatReg(this->_srcRegIdx[idx]); 28310346Smitch.hayenga@arm.com } 28410346Smitch.hayenga@arm.com 28510037SARM gem5 Developers const VecRegContainer& 28610037SARM gem5 Developers readVecRegOperand(const StaticInst *si, int idx) const override 28710037SARM gem5 Developers { 28810346Smitch.hayenga@arm.com return this->cpu->readVecReg(this->_srcRegIdx[idx]); 28910346Smitch.hayenga@arm.com } 29010037SARM gem5 Developers 29110346Smitch.hayenga@arm.com /** 29210346Smitch.hayenga@arm.com * Read destination vector register operand for modification. 29310346Smitch.hayenga@arm.com */ 29410346Smitch.hayenga@arm.com VecRegContainer& 29510037SARM gem5 Developers getWritableVecRegOperand(const StaticInst *si, int idx) override 29610037SARM gem5 Developers { 29710037SARM gem5 Developers return this->cpu->getWritableVecReg(this->_destRegIdx[idx]); 29810346Smitch.hayenga@arm.com } 29910346Smitch.hayenga@arm.com 30010037SARM gem5 Developers /** Vector Register Lane Interfaces. */ 30110346Smitch.hayenga@arm.com /** @{ */ 30210346Smitch.hayenga@arm.com /** Reads source vector 8bit operand. */ 30310037SARM gem5 Developers ConstVecLane8 30410037SARM gem5 Developers readVec8BitLaneOperand(const StaticInst *si, int idx) const override 30510037SARM gem5 Developers { 30610037SARM gem5 Developers return cpu->template readVecLane<uint8_t>(_srcRegIdx[idx]); 30710037SARM gem5 Developers } 30810346Smitch.hayenga@arm.com 30910346Smitch.hayenga@arm.com /** Reads source vector 16bit operand. */ 31010346Smitch.hayenga@arm.com ConstVecLane16 31110346Smitch.hayenga@arm.com readVec16BitLaneOperand(const StaticInst *si, int idx) const override 31210037SARM gem5 Developers { 31310346Smitch.hayenga@arm.com return cpu->template readVecLane<uint16_t>(_srcRegIdx[idx]); 31410037SARM gem5 Developers } 31510037SARM gem5 Developers 31610037SARM gem5 Developers /** Reads source vector 32bit operand. */ 31710037SARM gem5 Developers ConstVecLane32 31810037SARM gem5 Developers readVec32BitLaneOperand(const StaticInst *si, int idx) const override 31910346Smitch.hayenga@arm.com { 32010346Smitch.hayenga@arm.com return cpu->template readVecLane<uint32_t>(_srcRegIdx[idx]); 32110037SARM gem5 Developers } 32210346Smitch.hayenga@arm.com 32310346Smitch.hayenga@arm.com /** Reads source vector 64bit operand. */ 32410037SARM gem5 Developers ConstVecLane64 32510037SARM gem5 Developers readVec64BitLaneOperand(const StaticInst *si, int idx) const override 32610346Smitch.hayenga@arm.com { 32710346Smitch.hayenga@arm.com return cpu->template readVecLane<uint64_t>(_srcRegIdx[idx]); 32810037SARM gem5 Developers } 32910037SARM gem5 Developers 33010037SARM gem5 Developers /** Write a lane of the destination vector operand. */ 33110037SARM gem5 Developers template <typename LD> 33210037SARM gem5 Developers void 33310346Smitch.hayenga@arm.com setVecLaneOperandT(const StaticInst *si, int idx, const LD& val) 33410037SARM gem5 Developers { 33510037SARM gem5 Developers return cpu->template setVecLane(_destRegIdx[idx], val); 33610037SARM gem5 Developers } 33710346Smitch.hayenga@arm.com virtual void 33810346Smitch.hayenga@arm.com setVecLaneOperand(const StaticInst *si, int idx, 33910666SAli.Saidi@ARM.com const LaneData<LaneSize::Byte>& val) override 34010037SARM gem5 Developers { 34110037SARM gem5 Developers return setVecLaneOperandT(si, idx, val); 34210037SARM gem5 Developers } 34310037SARM gem5 Developers virtual void 34410037SARM gem5 Developers setVecLaneOperand(const StaticInst *si, int idx, 34510037SARM gem5 Developers const LaneData<LaneSize::TwoByte>& val) override 34610037SARM gem5 Developers { 34710037SARM gem5 Developers return setVecLaneOperandT(si, idx, val); 34810037SARM gem5 Developers } 34910037SARM gem5 Developers virtual void 35010037SARM gem5 Developers setVecLaneOperand(const StaticInst *si, int idx, 35110037SARM gem5 Developers const LaneData<LaneSize::FourByte>& val) override 35210346Smitch.hayenga@arm.com { 35310037SARM gem5 Developers return setVecLaneOperandT(si, idx, val); 35410037SARM gem5 Developers } 35510346Smitch.hayenga@arm.com virtual void 35610346Smitch.hayenga@arm.com setVecLaneOperand(const StaticInst *si, int idx, 35710037SARM gem5 Developers const LaneData<LaneSize::EightByte>& val) override 35810346Smitch.hayenga@arm.com { 35910037SARM gem5 Developers return setVecLaneOperandT(si, idx, val); 36010346Smitch.hayenga@arm.com } 36110346Smitch.hayenga@arm.com /** @} */ 36210346Smitch.hayenga@arm.com 36310037SARM gem5 Developers VecElem readVecElemOperand(const StaticInst *si, int idx) const override 36410346Smitch.hayenga@arm.com { 36510666SAli.Saidi@ARM.com return this->cpu->readVecElem(this->_srcRegIdx[idx]); 36610037SARM gem5 Developers } 36710037SARM gem5 Developers 36810037SARM gem5 Developers const VecPredRegContainer& 36910037SARM gem5 Developers readVecPredRegOperand(const StaticInst *si, int idx) const override 37010037SARM gem5 Developers { 37110037SARM gem5 Developers return this->cpu->readVecPredReg(this->_srcRegIdx[idx]); 37210037SARM gem5 Developers } 37310346Smitch.hayenga@arm.com 37410037SARM gem5 Developers VecPredRegContainer& 37510037SARM gem5 Developers getWritableVecPredRegOperand(const StaticInst *si, int idx) override 37610346Smitch.hayenga@arm.com { 37710346Smitch.hayenga@arm.com return this->cpu->getWritableVecPredReg(this->_destRegIdx[idx]); 37810037SARM gem5 Developers } 37910346Smitch.hayenga@arm.com 38010037SARM gem5 Developers RegVal 38110346Smitch.hayenga@arm.com readCCRegOperand(const StaticInst *si, int idx) override 38210346Smitch.hayenga@arm.com { 38310037SARM gem5 Developers return this->cpu->readCCReg(this->_srcRegIdx[idx]); 38410346Smitch.hayenga@arm.com } 38510346Smitch.hayenga@arm.com 38610666SAli.Saidi@ARM.com /** @todo: Make results into arrays so they can handle multiple dest 38710037SARM gem5 Developers * registers. 38810346Smitch.hayenga@arm.com */ 38910346Smitch.hayenga@arm.com void 39010346Smitch.hayenga@arm.com setIntRegOperand(const StaticInst *si, int idx, RegVal val) override 39110346Smitch.hayenga@arm.com { 39210037SARM gem5 Developers this->cpu->setIntReg(this->_destRegIdx[idx], val); 39310037SARM gem5 Developers BaseDynInst<Impl>::setIntRegOperand(si, idx, val); 39410037SARM gem5 Developers } 39510037SARM gem5 Developers 39610037SARM gem5 Developers void 39710037SARM gem5 Developers setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override 39810037SARM gem5 Developers { 39910346Smitch.hayenga@arm.com this->cpu->setFloatReg(this->_destRegIdx[idx], val); 40010037SARM gem5 Developers BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val); 40110037SARM gem5 Developers } 40210346Smitch.hayenga@arm.com 40310346Smitch.hayenga@arm.com void 40410037SARM gem5 Developers setVecRegOperand(const StaticInst *si, int idx, 40510346Smitch.hayenga@arm.com const VecRegContainer& val) override 40610037SARM gem5 Developers { 40710346Smitch.hayenga@arm.com this->cpu->setVecReg(this->_destRegIdx[idx], val); 40810346Smitch.hayenga@arm.com BaseDynInst<Impl>::setVecRegOperand(si, idx, val); 40910037SARM gem5 Developers } 41010346Smitch.hayenga@arm.com 41110346Smitch.hayenga@arm.com void setVecElemOperand(const StaticInst *si, int idx, 41210666SAli.Saidi@ARM.com const VecElem val) override 41310037SARM gem5 Developers { 41410346Smitch.hayenga@arm.com int reg_idx = idx; 41510346Smitch.hayenga@arm.com this->cpu->setVecElem(this->_destRegIdx[reg_idx], val); 41610346Smitch.hayenga@arm.com BaseDynInst<Impl>::setVecElemOperand(si, idx, val); 41710346Smitch.hayenga@arm.com } 41810037SARM gem5 Developers 41910037SARM gem5 Developers void 42010037SARM gem5 Developers setVecPredRegOperand(const StaticInst *si, int idx, 42110037SARM gem5 Developers const VecPredRegContainer& val) override 42210037SARM gem5 Developers { 42310037SARM gem5 Developers this->cpu->setVecPredReg(this->_destRegIdx[idx], val); 42410037SARM gem5 Developers BaseDynInst<Impl>::setVecPredRegOperand(si, idx, val); 42510037SARM gem5 Developers } 42610346Smitch.hayenga@arm.com 42710037SARM gem5 Developers void setCCRegOperand(const StaticInst *si, int idx, RegVal val) override 42810037SARM gem5 Developers { 42910346Smitch.hayenga@arm.com this->cpu->setCCReg(this->_destRegIdx[idx], val); 43010346Smitch.hayenga@arm.com BaseDynInst<Impl>::setCCRegOperand(si, idx, val); 43110037SARM gem5 Developers } 43210346Smitch.hayenga@arm.com 43310346Smitch.hayenga@arm.com#if THE_ISA == MIPS_ISA 43410037SARM gem5 Developers RegVal 43510346Smitch.hayenga@arm.com readRegOtherThread(const RegId& misc_reg, ThreadID tid) override 43610346Smitch.hayenga@arm.com { 43710346Smitch.hayenga@arm.com panic("MIPS MT not defined for O3 CPU.\n"); 43810346Smitch.hayenga@arm.com return 0; 43910346Smitch.hayenga@arm.com } 44010037SARM gem5 Developers 44110037SARM gem5 Developers void 44210346Smitch.hayenga@arm.com setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid) override 44310666SAli.Saidi@ARM.com { 44410037SARM gem5 Developers panic("MIPS MT not defined for O3 CPU.\n"); 44510037SARM gem5 Developers } 44610037SARM gem5 Developers#endif 44710037SARM gem5 Developers}; 44810037SARM gem5 Developers 44910037SARM gem5 Developers#endif // __CPU_O3_ALPHA_DYN_INST_HH__ 45010037SARM gem5 Developers 45110346Smitch.hayenga@arm.com