dyn_inst.hh revision 13500:6e0a2a7c6d8c
1/* 2 * Copyright (c) 2010, 2016 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2004-2006 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 */ 43 44#ifndef __CPU_O3_DYN_INST_HH__ 45#define __CPU_O3_DYN_INST_HH__ 46 47#include <array> 48 49#include "arch/isa_traits.hh" 50#include "config/the_isa.hh" 51#include "cpu/o3/cpu.hh" 52#include "cpu/o3/isa_specific.hh" 53#include "cpu/base_dyn_inst.hh" 54#include "cpu/inst_seq.hh" 55#include "cpu/reg_class.hh" 56 57class Packet; 58 59template <class Impl> 60class BaseO3DynInst : public BaseDynInst<Impl> 61{ 62 public: 63 /** Typedef for the CPU. */ 64 typedef typename Impl::O3CPU O3CPU; 65 66 /** Binary machine instruction type. */ 67 typedef TheISA::MachInst MachInst; 68 /** Register types. */ 69 typedef TheISA::IntReg IntReg; 70 typedef TheISA::FloatReg FloatReg; 71 typedef TheISA::FloatRegBits FloatRegBits; 72 typedef TheISA::CCReg CCReg; 73 using VecRegContainer = TheISA::VecRegContainer; 74 using VecElem = TheISA::VecElem; 75 static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg; 76 77 /** Misc register type. */ 78 typedef TheISA::MiscReg MiscReg; 79 80 enum { 81 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs 82 MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs 83 }; 84 85 public: 86 /** BaseDynInst constructor given a binary instruction. */ 87 BaseO3DynInst(const StaticInstPtr &staticInst, const StaticInstPtr 88 ¯oop, TheISA::PCState pc, TheISA::PCState predPC, 89 InstSeqNum seq_num, O3CPU *cpu); 90 91 /** BaseDynInst constructor given a static inst pointer. */ 92 BaseO3DynInst(const StaticInstPtr &_staticInst, 93 const StaticInstPtr &_macroop); 94 95 ~BaseO3DynInst(); 96 97 /** Executes the instruction.*/ 98 Fault execute(); 99 100 /** Initiates the access. Only valid for memory operations. */ 101 Fault initiateAcc(); 102 103 /** Completes the access. Only valid for memory operations. */ 104 Fault completeAcc(PacketPtr pkt); 105 106 private: 107 /** Initializes variables. */ 108 void initVars(); 109 110 protected: 111 /** Explicitation of dependent names. */ 112 using BaseDynInst<Impl>::cpu; 113 using BaseDynInst<Impl>::_srcRegIdx; 114 using BaseDynInst<Impl>::_destRegIdx; 115 116 /** Values to be written to the destination misc. registers. */ 117 std::array<MiscReg, TheISA::MaxMiscDestRegs> _destMiscRegVal; 118 119 /** Indexes of the destination misc. registers. They are needed to defer 120 * the write accesses to the misc. registers until the commit stage, when 121 * the instruction is out of its speculative state. 122 */ 123 std::array<short, TheISA::MaxMiscDestRegs> _destMiscRegIdx; 124 125 /** Number of destination misc. registers. */ 126 uint8_t _numDestMiscRegs; 127 128 129 public: 130#if TRACING_ON 131 /** Tick records used for the pipeline activity viewer. */ 132 Tick fetchTick; // instruction fetch is completed. 133 int32_t decodeTick; // instruction enters decode phase 134 int32_t renameTick; // instruction enters rename phase 135 int32_t dispatchTick; 136 int32_t issueTick; 137 int32_t completeTick; 138 int32_t commitTick; 139 int32_t storeTick; 140#endif 141 142 /** Reads a misc. register, including any side-effects the read 143 * might have as defined by the architecture. 144 */ 145 MiscReg readMiscReg(int misc_reg) 146 { 147 return this->cpu->readMiscReg(misc_reg, this->threadNumber); 148 } 149 150 /** Sets a misc. register, including any side-effects the write 151 * might have as defined by the architecture. 152 */ 153 void setMiscReg(int misc_reg, const MiscReg &val) 154 { 155 /** Writes to misc. registers are recorded and deferred until the 156 * commit stage, when updateMiscRegs() is called. First, check if 157 * the misc reg has been written before and update its value to be 158 * committed instead of making a new entry. If not, make a new 159 * entry and record the write. 160 */ 161 for (int idx = 0; idx < _numDestMiscRegs; idx++) { 162 if (_destMiscRegIdx[idx] == misc_reg) { 163 _destMiscRegVal[idx] = val; 164 return; 165 } 166 } 167 168 assert(_numDestMiscRegs < TheISA::MaxMiscDestRegs); 169 _destMiscRegIdx[_numDestMiscRegs] = misc_reg; 170 _destMiscRegVal[_numDestMiscRegs] = val; 171 _numDestMiscRegs++; 172 } 173 174 /** Reads a misc. register, including any side-effects the read 175 * might have as defined by the architecture. 176 */ 177 TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx) 178 { 179 const RegId& reg = si->srcRegIdx(idx); 180 assert(reg.isMiscReg()); 181 return this->cpu->readMiscReg(reg.index(), this->threadNumber); 182 } 183 184 /** Sets a misc. register, including any side-effects the write 185 * might have as defined by the architecture. 186 */ 187 void setMiscRegOperand(const StaticInst *si, int idx, 188 const MiscReg &val) 189 { 190 const RegId& reg = si->destRegIdx(idx); 191 assert(reg.isMiscReg()); 192 setMiscReg(reg.index(), val); 193 } 194 195 /** Called at the commit stage to update the misc. registers. */ 196 void updateMiscRegs() 197 { 198 // @todo: Pretty convoluted way to avoid squashing from happening when 199 // using the TC during an instruction's execution (specifically for 200 // instructions that have side-effects that use the TC). Fix this. 201 // See cpu/o3/dyn_inst_impl.hh. 202 bool no_squash_from_TC = this->thread->noSquashFromTC; 203 this->thread->noSquashFromTC = true; 204 205 for (int i = 0; i < _numDestMiscRegs; i++) 206 this->cpu->setMiscReg( 207 _destMiscRegIdx[i], _destMiscRegVal[i], this->threadNumber); 208 209 this->thread->noSquashFromTC = no_squash_from_TC; 210 } 211 212 void forwardOldRegs() 213 { 214 215 for (int idx = 0; idx < this->numDestRegs(); idx++) { 216 PhysRegIdPtr prev_phys_reg = this->prevDestRegIdx(idx); 217 const RegId& original_dest_reg = 218 this->staticInst->destRegIdx(idx); 219 switch (original_dest_reg.classValue()) { 220 case IntRegClass: 221 this->setIntRegOperand(this->staticInst.get(), idx, 222 this->cpu->readIntReg(prev_phys_reg)); 223 break; 224 case FloatRegClass: 225 this->setFloatRegOperandBits(this->staticInst.get(), idx, 226 this->cpu->readFloatRegBits(prev_phys_reg)); 227 break; 228 case VecRegClass: 229 this->setVecRegOperand(this->staticInst.get(), idx, 230 this->cpu->readVecReg(prev_phys_reg)); 231 break; 232 case VecElemClass: 233 this->setVecElemOperand(this->staticInst.get(), idx, 234 this->cpu->readVecElem(prev_phys_reg)); 235 break; 236 case CCRegClass: 237 this->setCCRegOperand(this->staticInst.get(), idx, 238 this->cpu->readCCReg(prev_phys_reg)); 239 break; 240 case MiscRegClass: 241 // no need to forward misc reg values 242 break; 243 default: 244 panic("Unknown register class: %d", 245 (int)original_dest_reg.classValue()); 246 } 247 } 248 } 249 /** Calls hardware return from error interrupt. */ 250 Fault hwrei(); 251 /** Traps to handle specified fault. */ 252 void trap(const Fault &fault); 253 bool simPalCheck(int palFunc); 254 255 /** Emulates a syscall. */ 256 void syscall(int64_t callnum, Fault *fault); 257 258 public: 259 260 // The register accessor methods provide the index of the 261 // instruction's operand (e.g., 0 or 1), not the architectural 262 // register index, to simplify the implementation of register 263 // renaming. We find the architectural register index by indexing 264 // into the instruction's own operand index table. Note that a 265 // raw pointer to the StaticInst is provided instead of a 266 // ref-counted StaticInstPtr to redice overhead. This is fine as 267 // long as these methods don't copy the pointer into any long-term 268 // storage (which is pretty hard to imagine they would have reason 269 // to do). 270 271 IntReg readIntRegOperand(const StaticInst *si, int idx) 272 { 273 return this->cpu->readIntReg(this->_srcRegIdx[idx]); 274 } 275 276 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 277 { 278 return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]); 279 } 280 281 const VecRegContainer& 282 readVecRegOperand(const StaticInst *si, int idx) const 283 { 284 return this->cpu->readVecReg(this->_srcRegIdx[idx]); 285 } 286 287 /** 288 * Read destination vector register operand for modification. 289 */ 290 VecRegContainer& 291 getWritableVecRegOperand(const StaticInst *si, int idx) 292 { 293 return this->cpu->getWritableVecReg(this->_destRegIdx[idx]); 294 } 295 296 /** Vector Register Lane Interfaces. */ 297 /** @{ */ 298 /** Reads source vector 8bit operand. */ 299 ConstVecLane8 300 readVec8BitLaneOperand(const StaticInst *si, int idx) const 301 { 302 return cpu->template readVecLane<uint8_t>(_srcRegIdx[idx]); 303 } 304 305 /** Reads source vector 16bit operand. */ 306 ConstVecLane16 307 readVec16BitLaneOperand(const StaticInst *si, int idx) const 308 { 309 return cpu->template readVecLane<uint16_t>(_srcRegIdx[idx]); 310 } 311 312 /** Reads source vector 32bit operand. */ 313 ConstVecLane32 314 readVec32BitLaneOperand(const StaticInst *si, int idx) const 315 { 316 return cpu->template readVecLane<uint32_t>(_srcRegIdx[idx]); 317 } 318 319 /** Reads source vector 64bit operand. */ 320 ConstVecLane64 321 readVec64BitLaneOperand(const StaticInst *si, int idx) const 322 { 323 return cpu->template readVecLane<uint64_t>(_srcRegIdx[idx]); 324 } 325 326 /** Write a lane of the destination vector operand. */ 327 template <typename LD> 328 void 329 setVecLaneOperandT(const StaticInst *si, int idx, const LD& val) 330 { 331 return cpu->template setVecLane(_destRegIdx[idx], val); 332 } 333 virtual void 334 setVecLaneOperand(const StaticInst *si, int idx, 335 const LaneData<LaneSize::Byte>& val) 336 { 337 return setVecLaneOperandT(si, idx, val); 338 } 339 virtual void 340 setVecLaneOperand(const StaticInst *si, int idx, 341 const LaneData<LaneSize::TwoByte>& val) 342 { 343 return setVecLaneOperandT(si, idx, val); 344 } 345 virtual void 346 setVecLaneOperand(const StaticInst *si, int idx, 347 const LaneData<LaneSize::FourByte>& val) 348 { 349 return setVecLaneOperandT(si, idx, val); 350 } 351 virtual void 352 setVecLaneOperand(const StaticInst *si, int idx, 353 const LaneData<LaneSize::EightByte>& val) 354 { 355 return setVecLaneOperandT(si, idx, val); 356 } 357 /** @} */ 358 359 VecElem readVecElemOperand(const StaticInst *si, int idx) const 360 { 361 return this->cpu->readVecElem(this->_srcRegIdx[idx]); 362 } 363 364 CCReg readCCRegOperand(const StaticInst *si, int idx) 365 { 366 return this->cpu->readCCReg(this->_srcRegIdx[idx]); 367 } 368 369 /** @todo: Make results into arrays so they can handle multiple dest 370 * registers. 371 */ 372 void setIntRegOperand(const StaticInst *si, int idx, IntReg val) 373 { 374 this->cpu->setIntReg(this->_destRegIdx[idx], val); 375 BaseDynInst<Impl>::setIntRegOperand(si, idx, val); 376 } 377 378 void setFloatRegOperandBits(const StaticInst *si, int idx, 379 FloatRegBits val) 380 { 381 this->cpu->setFloatRegBits(this->_destRegIdx[idx], val); 382 BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val); 383 } 384 385 void 386 setVecRegOperand(const StaticInst *si, int idx, 387 const VecRegContainer& val) 388 { 389 this->cpu->setVecReg(this->_destRegIdx[idx], val); 390 BaseDynInst<Impl>::setVecRegOperand(si, idx, val); 391 } 392 393 void setVecElemOperand(const StaticInst *si, int idx, 394 const VecElem val) 395 { 396 int reg_idx = idx; 397 this->cpu->setVecElem(this->_destRegIdx[reg_idx], val); 398 BaseDynInst<Impl>::setVecElemOperand(si, idx, val); 399 } 400 401 void setCCRegOperand(const StaticInst *si, int idx, CCReg val) 402 { 403 this->cpu->setCCReg(this->_destRegIdx[idx], val); 404 BaseDynInst<Impl>::setCCRegOperand(si, idx, val); 405 } 406 407#if THE_ISA == MIPS_ISA 408 MiscReg readRegOtherThread(const RegId& misc_reg, ThreadID tid) 409 { 410 panic("MIPS MT not defined for O3 CPU.\n"); 411 return 0; 412 } 413 414 void setRegOtherThread(const RegId& misc_reg, MiscReg val, ThreadID tid) 415 { 416 panic("MIPS MT not defined for O3 CPU.\n"); 417 } 418#endif 419}; 420 421#endif // __CPU_O3_ALPHA_DYN_INST_HH__ 422 423