dyn_inst.hh revision 12622:91cce46512f2
17170Sgblack@eecs.umich.edu/* 27170Sgblack@eecs.umich.edu * Copyright (c) 2010, 2016 ARM Limited 37170Sgblack@eecs.umich.edu * Copyright (c) 2013 Advanced Micro Devices, Inc. 47170Sgblack@eecs.umich.edu * All rights reserved 57170Sgblack@eecs.umich.edu * 67170Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 77170Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 87170Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 97170Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 107170Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 117170Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 127170Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 137170Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 147170Sgblack@eecs.umich.edu * 157170Sgblack@eecs.umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 167170Sgblack@eecs.umich.edu * All rights reserved. 177170Sgblack@eecs.umich.edu * 187170Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 197170Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 207170Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 217170Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 227170Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 237170Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 247170Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 257170Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 267170Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 277170Sgblack@eecs.umich.edu * this software without specific prior written permission. 287170Sgblack@eecs.umich.edu * 297170Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 307170Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 317170Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 327170Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 337170Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 347170Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 357170Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 367170Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 377170Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 387170Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 397170Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 407170Sgblack@eecs.umich.edu * 417170Sgblack@eecs.umich.edu * Authors: Kevin Lim 427170Sgblack@eecs.umich.edu */ 437170Sgblack@eecs.umich.edu 447170Sgblack@eecs.umich.edu#ifndef __CPU_O3_DYN_INST_HH__ 457170Sgblack@eecs.umich.edu#define __CPU_O3_DYN_INST_HH__ 467170Sgblack@eecs.umich.edu 477170Sgblack@eecs.umich.edu#include <array> 487170Sgblack@eecs.umich.edu 497170Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 507170Sgblack@eecs.umich.edu#include "config/the_isa.hh" 517170Sgblack@eecs.umich.edu#include "cpu/o3/cpu.hh" 527170Sgblack@eecs.umich.edu#include "cpu/o3/isa_specific.hh" 537170Sgblack@eecs.umich.edu#include "cpu/base_dyn_inst.hh" 547170Sgblack@eecs.umich.edu#include "cpu/inst_seq.hh" 557170Sgblack@eecs.umich.edu#include "cpu/reg_class.hh" 567170Sgblack@eecs.umich.edu 577170Sgblack@eecs.umich.educlass Packet; 587170Sgblack@eecs.umich.edu 597170Sgblack@eecs.umich.edutemplate <class Impl> 607170Sgblack@eecs.umich.educlass BaseO3DynInst : public BaseDynInst<Impl> 617170Sgblack@eecs.umich.edu{ 627170Sgblack@eecs.umich.edu public: 637170Sgblack@eecs.umich.edu /** Typedef for the CPU. */ 647170Sgblack@eecs.umich.edu typedef typename Impl::O3CPU O3CPU; 657170Sgblack@eecs.umich.edu 667170Sgblack@eecs.umich.edu /** Binary machine instruction type. */ 677170Sgblack@eecs.umich.edu typedef TheISA::MachInst MachInst; 687170Sgblack@eecs.umich.edu /** Register types. */ 697170Sgblack@eecs.umich.edu typedef TheISA::IntReg IntReg; 707190Sgblack@eecs.umich.edu typedef TheISA::FloatReg FloatReg; 717190Sgblack@eecs.umich.edu typedef TheISA::FloatRegBits FloatRegBits; 727190Sgblack@eecs.umich.edu typedef TheISA::CCReg CCReg; 737190Sgblack@eecs.umich.edu using VecRegContainer = TheISA::VecRegContainer; 747190Sgblack@eecs.umich.edu using VecElem = TheISA::VecElem; 757190Sgblack@eecs.umich.edu static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg; 767190Sgblack@eecs.umich.edu 777190Sgblack@eecs.umich.edu /** Misc register type. */ 787190Sgblack@eecs.umich.edu typedef TheISA::MiscReg MiscReg; 797190Sgblack@eecs.umich.edu 807170Sgblack@eecs.umich.edu enum { 817170Sgblack@eecs.umich.edu MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs 827190Sgblack@eecs.umich.edu MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs 837190Sgblack@eecs.umich.edu }; 847190Sgblack@eecs.umich.edu 857190Sgblack@eecs.umich.edu public: 867190Sgblack@eecs.umich.edu /** BaseDynInst constructor given a binary instruction. */ 877190Sgblack@eecs.umich.edu BaseO3DynInst(const StaticInstPtr &staticInst, const StaticInstPtr 887190Sgblack@eecs.umich.edu ¯oop, TheISA::PCState pc, TheISA::PCState predPC, 897190Sgblack@eecs.umich.edu InstSeqNum seq_num, O3CPU *cpu); 907190Sgblack@eecs.umich.edu 917170Sgblack@eecs.umich.edu /** BaseDynInst constructor given a static inst pointer. */ 927170Sgblack@eecs.umich.edu BaseO3DynInst(const StaticInstPtr &_staticInst, 937170Sgblack@eecs.umich.edu const StaticInstPtr &_macroop); 947170Sgblack@eecs.umich.edu 957170Sgblack@eecs.umich.edu ~BaseO3DynInst(); 967190Sgblack@eecs.umich.edu 977170Sgblack@eecs.umich.edu /** Executes the instruction.*/ 987170Sgblack@eecs.umich.edu Fault execute(); 997170Sgblack@eecs.umich.edu 1007170Sgblack@eecs.umich.edu /** Initiates the access. Only valid for memory operations. */ 1017170Sgblack@eecs.umich.edu Fault initiateAcc(); 1027170Sgblack@eecs.umich.edu 1037170Sgblack@eecs.umich.edu /** Completes the access. Only valid for memory operations. */ 1047310Sgblack@eecs.umich.edu Fault completeAcc(PacketPtr pkt); 1057170Sgblack@eecs.umich.edu 1067170Sgblack@eecs.umich.edu private: 1077170Sgblack@eecs.umich.edu /** Initializes variables. */ 1087170Sgblack@eecs.umich.edu void initVars(); 1097170Sgblack@eecs.umich.edu 1107190Sgblack@eecs.umich.edu protected: 1117190Sgblack@eecs.umich.edu /** Explicitation of dependent names. */ 1127170Sgblack@eecs.umich.edu using BaseDynInst<Impl>::cpu; 1137190Sgblack@eecs.umich.edu using BaseDynInst<Impl>::_srcRegIdx; 1147190Sgblack@eecs.umich.edu using BaseDynInst<Impl>::_destRegIdx; 1157170Sgblack@eecs.umich.edu 1167170Sgblack@eecs.umich.edu /** Values to be written to the destination misc. registers. */ 1177190Sgblack@eecs.umich.edu std::array<MiscReg, TheISA::MaxMiscDestRegs> _destMiscRegVal; 1187170Sgblack@eecs.umich.edu 1197170Sgblack@eecs.umich.edu /** Indexes of the destination misc. registers. They are needed to defer 1207170Sgblack@eecs.umich.edu * the write accesses to the misc. registers until the commit stage, when 1217170Sgblack@eecs.umich.edu * the instruction is out of its speculative state. 1227170Sgblack@eecs.umich.edu */ 1237170Sgblack@eecs.umich.edu std::array<short, TheISA::MaxMiscDestRegs> _destMiscRegIdx; 1247170Sgblack@eecs.umich.edu 1257170Sgblack@eecs.umich.edu /** Number of destination misc. registers. */ 1267190Sgblack@eecs.umich.edu uint8_t _numDestMiscRegs; 1277190Sgblack@eecs.umich.edu 1287170Sgblack@eecs.umich.edu 1297190Sgblack@eecs.umich.edu public: 1307190Sgblack@eecs.umich.edu#if TRACING_ON 1317343Sgblack@eecs.umich.edu /** Tick records used for the pipeline activity viewer. */ 1327343Sgblack@eecs.umich.edu Tick fetchTick; // instruction fetch is completed. 1337343Sgblack@eecs.umich.edu int32_t decodeTick; // instruction enters decode phase 1347343Sgblack@eecs.umich.edu int32_t renameTick; // instruction enters rename phase 1357343Sgblack@eecs.umich.edu int32_t dispatchTick; 1367343Sgblack@eecs.umich.edu int32_t issueTick; 1377343Sgblack@eecs.umich.edu int32_t completeTick; 1387170Sgblack@eecs.umich.edu int32_t commitTick; 1397170Sgblack@eecs.umich.edu int32_t storeTick; 1407175Sgblack@eecs.umich.edu#endif 1417175Sgblack@eecs.umich.edu 1427175Sgblack@eecs.umich.edu /** Reads a misc. register, including any side-effects the read 1437175Sgblack@eecs.umich.edu * might have as defined by the architecture. 1447175Sgblack@eecs.umich.edu */ 1457175Sgblack@eecs.umich.edu MiscReg readMiscReg(int misc_reg) 1467175Sgblack@eecs.umich.edu { 1477175Sgblack@eecs.umich.edu return this->cpu->readMiscReg(misc_reg, this->threadNumber); 1487175Sgblack@eecs.umich.edu } 1497175Sgblack@eecs.umich.edu 1507175Sgblack@eecs.umich.edu /** Sets a misc. register, including any side-effects the write 1517175Sgblack@eecs.umich.edu * might have as defined by the architecture. 1527175Sgblack@eecs.umich.edu */ 1537175Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 1547175Sgblack@eecs.umich.edu { 1557175Sgblack@eecs.umich.edu /** Writes to misc. registers are recorded and deferred until the 1567175Sgblack@eecs.umich.edu * commit stage, when updateMiscRegs() is called. First, check if 1577175Sgblack@eecs.umich.edu * the misc reg has been written before and update its value to be 1587175Sgblack@eecs.umich.edu * committed instead of making a new entry. If not, make a new 1597175Sgblack@eecs.umich.edu * entry and record the write. 1607175Sgblack@eecs.umich.edu */ 1617342Sgblack@eecs.umich.edu for (int idx = 0; idx < _numDestMiscRegs; idx++) { 1627342Sgblack@eecs.umich.edu if (_destMiscRegIdx[idx] == misc_reg) { 1637342Sgblack@eecs.umich.edu _destMiscRegVal[idx] = val; 1647395Sgblack@eecs.umich.edu return; 1657175Sgblack@eecs.umich.edu } 1667342Sgblack@eecs.umich.edu } 1677342Sgblack@eecs.umich.edu 1687175Sgblack@eecs.umich.edu assert(_numDestMiscRegs < TheISA::MaxMiscDestRegs); 1697342Sgblack@eecs.umich.edu _destMiscRegIdx[_numDestMiscRegs] = misc_reg; 1707175Sgblack@eecs.umich.edu _destMiscRegVal[_numDestMiscRegs] = val; 1717175Sgblack@eecs.umich.edu _numDestMiscRegs++; 1727175Sgblack@eecs.umich.edu } 1737342Sgblack@eecs.umich.edu 1747175Sgblack@eecs.umich.edu /** Reads a misc. register, including any side-effects the read 1757395Sgblack@eecs.umich.edu * might have as defined by the architecture. 1767395Sgblack@eecs.umich.edu */ 1777175Sgblack@eecs.umich.edu TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx) 1787175Sgblack@eecs.umich.edu { 1797342Sgblack@eecs.umich.edu const RegId& reg = si->srcRegIdx(idx); 1807175Sgblack@eecs.umich.edu assert(reg.isMiscReg()); 1817395Sgblack@eecs.umich.edu return this->cpu->readMiscReg(reg.index(), this->threadNumber); 1827395Sgblack@eecs.umich.edu } 1837175Sgblack@eecs.umich.edu 1847342Sgblack@eecs.umich.edu /** Sets a misc. register, including any side-effects the write 1857342Sgblack@eecs.umich.edu * might have as defined by the architecture. 1867342Sgblack@eecs.umich.edu */ 1877342Sgblack@eecs.umich.edu void setMiscRegOperand(const StaticInst *si, int idx, 1887395Sgblack@eecs.umich.edu const MiscReg &val) 1897342Sgblack@eecs.umich.edu { 1907395Sgblack@eecs.umich.edu const RegId& reg = si->destRegIdx(idx); 1917342Sgblack@eecs.umich.edu assert(reg.isMiscReg()); 1927342Sgblack@eecs.umich.edu setMiscReg(reg.index(), val); 1937342Sgblack@eecs.umich.edu } 1947342Sgblack@eecs.umich.edu 1957175Sgblack@eecs.umich.edu /** Called at the commit stage to update the misc. registers. */ 1967175Sgblack@eecs.umich.edu void updateMiscRegs() 1977175Sgblack@eecs.umich.edu { 1987175Sgblack@eecs.umich.edu // @todo: Pretty convoluted way to avoid squashing from happening when 1997175Sgblack@eecs.umich.edu // using the TC during an instruction's execution (specifically for 2007175Sgblack@eecs.umich.edu // instructions that have side-effects that use the TC). Fix this. 2017175Sgblack@eecs.umich.edu // See cpu/o3/dyn_inst_impl.hh. 2027175Sgblack@eecs.umich.edu bool no_squash_from_TC = this->thread->noSquashFromTC; 2037175Sgblack@eecs.umich.edu this->thread->noSquashFromTC = true; 2047175Sgblack@eecs.umich.edu 2057175Sgblack@eecs.umich.edu for (int i = 0; i < _numDestMiscRegs; i++) 2067175Sgblack@eecs.umich.edu this->cpu->setMiscReg( 2077342Sgblack@eecs.umich.edu _destMiscRegIdx[i], _destMiscRegVal[i], this->threadNumber); 2087175Sgblack@eecs.umich.edu 2097343Sgblack@eecs.umich.edu this->thread->noSquashFromTC = no_squash_from_TC; 2107343Sgblack@eecs.umich.edu } 2117343Sgblack@eecs.umich.edu 2127343Sgblack@eecs.umich.edu void forwardOldRegs() 2137343Sgblack@eecs.umich.edu { 2147343Sgblack@eecs.umich.edu 2157343Sgblack@eecs.umich.edu for (int idx = 0; idx < this->numDestRegs(); idx++) { 2167170Sgblack@eecs.umich.edu PhysRegIdPtr prev_phys_reg = this->prevDestRegIdx(idx); 2177175Sgblack@eecs.umich.edu const RegId& original_dest_reg = 2187615Sminkyu.jeong@arm.com this->staticInst->destRegIdx(idx); 2197615Sminkyu.jeong@arm.com switch (original_dest_reg.classValue()) { 2207615Sminkyu.jeong@arm.com case IntRegClass: 2217615Sminkyu.jeong@arm.com this->setIntRegOperand(this->staticInst.get(), idx, 2227615Sminkyu.jeong@arm.com this->cpu->readIntReg(prev_phys_reg)); 2237615Sminkyu.jeong@arm.com break; 2247615Sminkyu.jeong@arm.com case FloatRegClass: 2257615Sminkyu.jeong@arm.com this->setFloatRegOperandBits(this->staticInst.get(), idx, 2267615Sminkyu.jeong@arm.com this->cpu->readFloatRegBits(prev_phys_reg)); 2277615Sminkyu.jeong@arm.com break; 2287615Sminkyu.jeong@arm.com case VecRegClass: 2297175Sgblack@eecs.umich.edu this->setVecRegOperand(this->staticInst.get(), idx, 2307615Sminkyu.jeong@arm.com this->cpu->readVecReg(prev_phys_reg)); 2317615Sminkyu.jeong@arm.com break; 2327615Sminkyu.jeong@arm.com case VecElemClass: 2337615Sminkyu.jeong@arm.com this->setVecElemOperand(this->staticInst.get(), idx, 2347615Sminkyu.jeong@arm.com this->cpu->readVecElem(prev_phys_reg)); 2357615Sminkyu.jeong@arm.com break; 2367615Sminkyu.jeong@arm.com case CCRegClass: 2377615Sminkyu.jeong@arm.com this->setCCRegOperand(this->staticInst.get(), idx, 2387615Sminkyu.jeong@arm.com this->cpu->readCCReg(prev_phys_reg)); 2397615Sminkyu.jeong@arm.com break; 2407615Sminkyu.jeong@arm.com case MiscRegClass: 2417615Sminkyu.jeong@arm.com // no need to forward misc reg values 2427615Sminkyu.jeong@arm.com break; 2437615Sminkyu.jeong@arm.com default: 2447615Sminkyu.jeong@arm.com panic("Unknown register class: %d", 2457615Sminkyu.jeong@arm.com (int)original_dest_reg.classValue()); 246 } 247 } 248 } 249 /** Calls hardware return from error interrupt. */ 250 Fault hwrei(); 251 /** Traps to handle specified fault. */ 252 void trap(const Fault &fault); 253 bool simPalCheck(int palFunc); 254 255 /** Emulates a syscall. */ 256 void syscall(int64_t callnum, Fault *fault); 257 258 public: 259 260 // The register accessor methods provide the index of the 261 // instruction's operand (e.g., 0 or 1), not the architectural 262 // register index, to simplify the implementation of register 263 // renaming. We find the architectural register index by indexing 264 // into the instruction's own operand index table. Note that a 265 // raw pointer to the StaticInst is provided instead of a 266 // ref-counted StaticInstPtr to redice overhead. This is fine as 267 // long as these methods don't copy the pointer into any long-term 268 // storage (which is pretty hard to imagine they would have reason 269 // to do). 270 271 IntReg readIntRegOperand(const StaticInst *si, int idx) 272 { 273 return this->cpu->readIntReg(this->_srcRegIdx[idx]); 274 } 275 276 FloatReg readFloatRegOperand(const StaticInst *si, int idx) 277 { 278 return this->cpu->readFloatReg(this->_srcRegIdx[idx]); 279 } 280 281 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 282 { 283 return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]); 284 } 285 286 const VecRegContainer& 287 readVecRegOperand(const StaticInst *si, int idx) const 288 { 289 return this->cpu->readVecReg(this->_srcRegIdx[idx]); 290 } 291 292 /** 293 * Read destination vector register operand for modification. 294 */ 295 VecRegContainer& 296 getWritableVecRegOperand(const StaticInst *si, int idx) 297 { 298 return this->cpu->getWritableVecReg(this->_destRegIdx[idx]); 299 } 300 301 /** Vector Register Lane Interfaces. */ 302 /** @{ */ 303 /** Reads source vector 8bit operand. */ 304 ConstVecLane8 305 readVec8BitLaneOperand(const StaticInst *si, int idx) const 306 { 307 return cpu->template readVecLane<uint8_t>(_srcRegIdx[idx]); 308 } 309 310 /** Reads source vector 16bit operand. */ 311 ConstVecLane16 312 readVec16BitLaneOperand(const StaticInst *si, int idx) const 313 { 314 return cpu->template readVecLane<uint16_t>(_srcRegIdx[idx]); 315 } 316 317 /** Reads source vector 32bit operand. */ 318 ConstVecLane32 319 readVec32BitLaneOperand(const StaticInst *si, int idx) const 320 { 321 return cpu->template readVecLane<uint32_t>(_srcRegIdx[idx]); 322 } 323 324 /** Reads source vector 64bit operand. */ 325 ConstVecLane64 326 readVec64BitLaneOperand(const StaticInst *si, int idx) const 327 { 328 return cpu->template readVecLane<uint64_t>(_srcRegIdx[idx]); 329 } 330 331 /** Write a lane of the destination vector operand. */ 332 template <typename LD> 333 void 334 setVecLaneOperandT(const StaticInst *si, int idx, const LD& val) 335 { 336 return cpu->template setVecLane(_destRegIdx[idx], val); 337 } 338 virtual void 339 setVecLaneOperand(const StaticInst *si, int idx, 340 const LaneData<LaneSize::Byte>& val) 341 { 342 return setVecLaneOperandT(si, idx, val); 343 } 344 virtual void 345 setVecLaneOperand(const StaticInst *si, int idx, 346 const LaneData<LaneSize::TwoByte>& val) 347 { 348 return setVecLaneOperandT(si, idx, val); 349 } 350 virtual void 351 setVecLaneOperand(const StaticInst *si, int idx, 352 const LaneData<LaneSize::FourByte>& val) 353 { 354 return setVecLaneOperandT(si, idx, val); 355 } 356 virtual void 357 setVecLaneOperand(const StaticInst *si, int idx, 358 const LaneData<LaneSize::EightByte>& val) 359 { 360 return setVecLaneOperandT(si, idx, val); 361 } 362 /** @} */ 363 364 VecElem readVecElemOperand(const StaticInst *si, int idx) const 365 { 366 return this->cpu->readVecElem(this->_srcRegIdx[idx]); 367 } 368 369 CCReg readCCRegOperand(const StaticInst *si, int idx) 370 { 371 return this->cpu->readCCReg(this->_srcRegIdx[idx]); 372 } 373 374 /** @todo: Make results into arrays so they can handle multiple dest 375 * registers. 376 */ 377 void setIntRegOperand(const StaticInst *si, int idx, IntReg val) 378 { 379 this->cpu->setIntReg(this->_destRegIdx[idx], val); 380 BaseDynInst<Impl>::setIntRegOperand(si, idx, val); 381 } 382 383 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 384 { 385 this->cpu->setFloatReg(this->_destRegIdx[idx], val); 386 BaseDynInst<Impl>::setFloatRegOperand(si, idx, val); 387 } 388 389 void setFloatRegOperandBits(const StaticInst *si, int idx, 390 FloatRegBits val) 391 { 392 this->cpu->setFloatRegBits(this->_destRegIdx[idx], val); 393 BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val); 394 } 395 396 void 397 setVecRegOperand(const StaticInst *si, int idx, 398 const VecRegContainer& val) 399 { 400 this->cpu->setVecReg(this->_destRegIdx[idx], val); 401 BaseDynInst<Impl>::setVecRegOperand(si, idx, val); 402 } 403 404 void setVecElemOperand(const StaticInst *si, int idx, 405 const VecElem val) 406 { 407 int reg_idx = idx; 408 this->cpu->setVecElem(this->_destRegIdx[reg_idx], val); 409 BaseDynInst<Impl>::setVecElemOperand(si, idx, val); 410 } 411 412 void setCCRegOperand(const StaticInst *si, int idx, CCReg val) 413 { 414 this->cpu->setCCReg(this->_destRegIdx[idx], val); 415 BaseDynInst<Impl>::setCCRegOperand(si, idx, val); 416 } 417 418#if THE_ISA == MIPS_ISA 419 MiscReg readRegOtherThread(const RegId& misc_reg, ThreadID tid) 420 { 421 panic("MIPS MT not defined for O3 CPU.\n"); 422 return 0; 423 } 424 425 void setRegOtherThread(const RegId& misc_reg, MiscReg val, ThreadID tid) 426 { 427 panic("MIPS MT not defined for O3 CPU.\n"); 428 } 429#endif 430}; 431 432#endif // __CPU_O3_ALPHA_DYN_INST_HH__ 433 434