dyn_inst.hh revision 10934:5af8f40d8f2c
1/* 2 * Copyright (c) 2010 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2004-2006 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 */ 43 44#ifndef __CPU_O3_DYN_INST_HH__ 45#define __CPU_O3_DYN_INST_HH__ 46 47#include <array> 48 49#include "arch/isa_traits.hh" 50#include "config/the_isa.hh" 51#include "cpu/o3/cpu.hh" 52#include "cpu/o3/isa_specific.hh" 53#include "cpu/base_dyn_inst.hh" 54#include "cpu/inst_seq.hh" 55#include "cpu/reg_class.hh" 56 57class Packet; 58 59template <class Impl> 60class BaseO3DynInst : public BaseDynInst<Impl> 61{ 62 public: 63 /** Typedef for the CPU. */ 64 typedef typename Impl::O3CPU O3CPU; 65 66 /** Binary machine instruction type. */ 67 typedef TheISA::MachInst MachInst; 68 /** Extended machine instruction type. */ 69 typedef TheISA::ExtMachInst ExtMachInst; 70 /** Logical register index type. */ 71 typedef TheISA::RegIndex RegIndex; 72 /** Integer register index type. */ 73 typedef TheISA::IntReg IntReg; 74 typedef TheISA::FloatReg FloatReg; 75 typedef TheISA::FloatRegBits FloatRegBits; 76 typedef TheISA::CCReg CCReg; 77 typedef TheISA::VectorReg VectorReg; 78 79 /** Misc register index type. */ 80 typedef TheISA::MiscReg MiscReg; 81 82 enum { 83 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs 84 MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs 85 }; 86 87 public: 88 /** BaseDynInst constructor given a binary instruction. */ 89 BaseO3DynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop, 90 TheISA::PCState pc, TheISA::PCState predPC, 91 InstSeqNum seq_num, O3CPU *cpu); 92 93 /** BaseDynInst constructor given a static inst pointer. */ 94 BaseO3DynInst(const StaticInstPtr &_staticInst, 95 const StaticInstPtr &_macroop); 96 97 ~BaseO3DynInst(); 98 99 /** Executes the instruction.*/ 100 Fault execute(); 101 102 /** Initiates the access. Only valid for memory operations. */ 103 Fault initiateAcc(); 104 105 /** Completes the access. Only valid for memory operations. */ 106 Fault completeAcc(PacketPtr pkt); 107 108 private: 109 /** Initializes variables. */ 110 void initVars(); 111 112 protected: 113 /** Values to be written to the destination misc. registers. */ 114 std::array<MiscReg, TheISA::MaxMiscDestRegs> _destMiscRegVal; 115 116 /** Indexes of the destination misc. registers. They are needed to defer 117 * the write accesses to the misc. registers until the commit stage, when 118 * the instruction is out of its speculative state. 119 */ 120 std::array<short, TheISA::MaxMiscDestRegs> _destMiscRegIdx; 121 122 /** Number of destination misc. registers. */ 123 uint8_t _numDestMiscRegs; 124 125 126 public: 127#if TRACING_ON 128 /** Tick records used for the pipeline activity viewer. */ 129 Tick fetchTick; // instruction fetch is completed. 130 int32_t decodeTick; // instruction enters decode phase 131 int32_t renameTick; // instruction enters rename phase 132 int32_t dispatchTick; 133 int32_t issueTick; 134 int32_t completeTick; 135 int32_t commitTick; 136 int32_t storeTick; 137#endif 138 139 /** Reads a misc. register, including any side-effects the read 140 * might have as defined by the architecture. 141 */ 142 MiscReg readMiscReg(int misc_reg) 143 { 144 return this->cpu->readMiscReg(misc_reg, this->threadNumber); 145 } 146 147 /** Sets a misc. register, including any side-effects the write 148 * might have as defined by the architecture. 149 */ 150 void setMiscReg(int misc_reg, const MiscReg &val) 151 { 152 /** Writes to misc. registers are recorded and deferred until the 153 * commit stage, when updateMiscRegs() is called. First, check if 154 * the misc reg has been written before and update its value to be 155 * committed instead of making a new entry. If not, make a new 156 * entry and record the write. 157 */ 158 for (int idx = 0; idx < _numDestMiscRegs; idx++) { 159 if (_destMiscRegIdx[idx] == misc_reg) { 160 _destMiscRegVal[idx] = val; 161 return; 162 } 163 } 164 165 assert(_numDestMiscRegs < TheISA::MaxMiscDestRegs); 166 _destMiscRegIdx[_numDestMiscRegs] = misc_reg; 167 _destMiscRegVal[_numDestMiscRegs] = val; 168 _numDestMiscRegs++; 169 } 170 171 /** Reads a misc. register, including any side-effects the read 172 * might have as defined by the architecture. 173 */ 174 TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx) 175 { 176 return this->cpu->readMiscReg( 177 si->srcRegIdx(idx) - TheISA::Misc_Reg_Base, 178 this->threadNumber); 179 } 180 181 /** Sets a misc. register, including any side-effects the write 182 * might have as defined by the architecture. 183 */ 184 void setMiscRegOperand(const StaticInst *si, int idx, 185 const MiscReg &val) 186 { 187 int misc_reg = si->destRegIdx(idx) - TheISA::Misc_Reg_Base; 188 setMiscReg(misc_reg, val); 189 } 190 191 /** Called at the commit stage to update the misc. registers. */ 192 void updateMiscRegs() 193 { 194 // @todo: Pretty convoluted way to avoid squashing from happening when 195 // using the TC during an instruction's execution (specifically for 196 // instructions that have side-effects that use the TC). Fix this. 197 // See cpu/o3/dyn_inst_impl.hh. 198 bool no_squash_from_TC = this->thread->noSquashFromTC; 199 this->thread->noSquashFromTC = true; 200 201 for (int i = 0; i < _numDestMiscRegs; i++) 202 this->cpu->setMiscReg( 203 _destMiscRegIdx[i], _destMiscRegVal[i], this->threadNumber); 204 205 this->thread->noSquashFromTC = no_squash_from_TC; 206 } 207 208 void forwardOldRegs() 209 { 210 for (int idx = 0; idx < this->numDestRegs(); idx++) { 211 PhysRegIndex prev_phys_reg = this->prevDestRegIdx(idx); 212 TheISA::RegIndex original_dest_reg = 213 this->staticInst->destRegIdx(idx); 214 switch (regIdxToClass(original_dest_reg)) { 215 case IntRegClass: 216 this->setIntRegOperand(this->staticInst.get(), idx, 217 this->cpu->readIntReg(prev_phys_reg)); 218 break; 219 case FloatRegClass: 220 this->setFloatRegOperandBits(this->staticInst.get(), idx, 221 this->cpu->readFloatRegBits(prev_phys_reg)); 222 break; 223 case CCRegClass: 224 this->setCCRegOperand(this->staticInst.get(), idx, 225 this->cpu->readCCReg(prev_phys_reg)); 226 break; 227 case VectorRegClass: 228 this->setVectorRegOperand(this->staticInst.get(), idx, 229 this->cpu->readVectorReg(prev_phys_reg)); 230 break; 231 232 case MiscRegClass: 233 // no need to forward misc reg values 234 break; 235 } 236 } 237 } 238 /** Calls hardware return from error interrupt. */ 239 Fault hwrei(); 240 /** Traps to handle specified fault. */ 241 void trap(const Fault &fault); 242 bool simPalCheck(int palFunc); 243 244 /** Emulates a syscall. */ 245 void syscall(int64_t callnum); 246 247 public: 248 249 // The register accessor methods provide the index of the 250 // instruction's operand (e.g., 0 or 1), not the architectural 251 // register index, to simplify the implementation of register 252 // renaming. We find the architectural register index by indexing 253 // into the instruction's own operand index table. Note that a 254 // raw pointer to the StaticInst is provided instead of a 255 // ref-counted StaticInstPtr to redice overhead. This is fine as 256 // long as these methods don't copy the pointer into any long-term 257 // storage (which is pretty hard to imagine they would have reason 258 // to do). 259 260 IntReg readIntRegOperand(const StaticInst *si, int idx) 261 { 262 return this->cpu->readIntReg(this->_srcRegIdx[idx]); 263 } 264 265 FloatReg readFloatRegOperand(const StaticInst *si, int idx) 266 { 267 return this->cpu->readFloatReg(this->_srcRegIdx[idx]); 268 } 269 270 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 271 { 272 return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]); 273 } 274 275 CCReg readCCRegOperand(const StaticInst *si, int idx) 276 { 277 return this->cpu->readCCReg(this->_srcRegIdx[idx]); 278 } 279 280 const VectorReg &readVectorRegOperand(const StaticInst *si, int idx) 281 { 282 return this->cpu->readVectorReg(this->_srcRegIdx[idx]); 283 } 284 285 /** @todo: Make results into arrays so they can handle multiple dest 286 * registers. 287 */ 288 void setIntRegOperand(const StaticInst *si, int idx, IntReg val) 289 { 290 this->cpu->setIntReg(this->_destRegIdx[idx], val); 291 BaseDynInst<Impl>::setIntRegOperand(si, idx, val); 292 } 293 294 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 295 { 296 this->cpu->setFloatReg(this->_destRegIdx[idx], val); 297 BaseDynInst<Impl>::setFloatRegOperand(si, idx, val); 298 } 299 300 void setFloatRegOperandBits(const StaticInst *si, int idx, 301 FloatRegBits val) 302 { 303 this->cpu->setFloatRegBits(this->_destRegIdx[idx], val); 304 BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val); 305 } 306 307 void setCCRegOperand(const StaticInst *si, int idx, CCReg val) 308 { 309 this->cpu->setCCReg(this->_destRegIdx[idx], val); 310 BaseDynInst<Impl>::setCCRegOperand(si, idx, val); 311 } 312 313 void setVectorRegOperand(const StaticInst *si, int idx, 314 const VectorReg &val) 315 { 316 this->cpu->setVectorReg(this->_destRegIdx[idx], val); 317 BaseDynInst<Impl>::setVectorRegOperand(si, idx, val); 318 } 319 320#if THE_ISA == MIPS_ISA 321 MiscReg readRegOtherThread(int misc_reg, ThreadID tid) 322 { 323 panic("MIPS MT not defined for O3 CPU.\n"); 324 return 0; 325 } 326 327 void setRegOtherThread(int misc_reg, MiscReg val, ThreadID tid) 328 { 329 panic("MIPS MT not defined for O3 CPU.\n"); 330 } 331#endif 332 333 public: 334 /** Calculates EA part of a memory instruction. Currently unused, 335 * though it may be useful in the future if we want to split 336 * memory operations into EA calculation and memory access parts. 337 */ 338 Fault calcEA() 339 { 340 return this->staticInst->eaCompInst()->execute(this, this->traceData); 341 } 342 343 /** Does the memory access part of a memory instruction. Currently unused, 344 * though it may be useful in the future if we want to split 345 * memory operations into EA calculation and memory access parts. 346 */ 347 Fault memAccess() 348 { 349 return this->staticInst->memAccInst()->execute(this, this->traceData); 350 } 351}; 352 353#endif // __CPU_O3_ALPHA_DYN_INST_HH__ 354 355