dyn_inst.hh revision 10319:4207f9bfcceb
112855Sgabeblack@google.com/* 212855Sgabeblack@google.com * Copyright (c) 2010 ARM Limited 312855Sgabeblack@google.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 412855Sgabeblack@google.com * All rights reserved 512855Sgabeblack@google.com * 612855Sgabeblack@google.com * The license below extends only to copyright in the software and shall 712855Sgabeblack@google.com * not be construed as granting a license to any other intellectual 812855Sgabeblack@google.com * property including but not limited to intellectual property relating 912855Sgabeblack@google.com * to a hardware implementation of the functionality of the software 1012855Sgabeblack@google.com * licensed hereunder. You may use the software subject to the license 1112855Sgabeblack@google.com * terms below provided that you ensure that this notice is replicated 1212855Sgabeblack@google.com * unmodified and in its entirety in all distributions of the software, 1312855Sgabeblack@google.com * modified or unmodified, in source code or in binary form. 1412855Sgabeblack@google.com * 1512855Sgabeblack@google.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 1612855Sgabeblack@google.com * All rights reserved. 1712855Sgabeblack@google.com * 1812855Sgabeblack@google.com * Redistribution and use in source and binary forms, with or without 1912855Sgabeblack@google.com * modification, are permitted provided that the following conditions are 2012855Sgabeblack@google.com * met: redistributions of source code must retain the above copyright 2112855Sgabeblack@google.com * notice, this list of conditions and the following disclaimer; 2212855Sgabeblack@google.com * redistributions in binary form must reproduce the above copyright 2312855Sgabeblack@google.com * notice, this list of conditions and the following disclaimer in the 2412855Sgabeblack@google.com * documentation and/or other materials provided with the distribution; 2512855Sgabeblack@google.com * neither the name of the copyright holders nor the names of its 2612855Sgabeblack@google.com * contributors may be used to endorse or promote products derived from 2712855Sgabeblack@google.com * this software without specific prior written permission. 2812855Sgabeblack@google.com * 2912855Sgabeblack@google.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 3012855Sgabeblack@google.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3112855Sgabeblack@google.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3212855Sgabeblack@google.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3312855Sgabeblack@google.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3412855Sgabeblack@google.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3512855Sgabeblack@google.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3612855Sgabeblack@google.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3712855Sgabeblack@google.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3812855Sgabeblack@google.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3912855Sgabeblack@google.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4012855Sgabeblack@google.com * 4112855Sgabeblack@google.com * Authors: Kevin Lim 4212855Sgabeblack@google.com */ 4312855Sgabeblack@google.com 4412855Sgabeblack@google.com#ifndef __CPU_O3_DYN_INST_HH__ 4512855Sgabeblack@google.com#define __CPU_O3_DYN_INST_HH__ 4612855Sgabeblack@google.com 4712855Sgabeblack@google.com#include "arch/isa_traits.hh" 4812855Sgabeblack@google.com#include "config/the_isa.hh" 4912855Sgabeblack@google.com#include "cpu/o3/cpu.hh" 5012855Sgabeblack@google.com#include "cpu/o3/isa_specific.hh" 5112855Sgabeblack@google.com#include "cpu/base_dyn_inst.hh" 5212855Sgabeblack@google.com#include "cpu/inst_seq.hh" 5312855Sgabeblack@google.com#include "cpu/reg_class.hh" 5412855Sgabeblack@google.com 5512855Sgabeblack@google.comclass Packet; 5612855Sgabeblack@google.com 5712855Sgabeblack@google.comtemplate <class Impl> 5812855Sgabeblack@google.comclass BaseO3DynInst : public BaseDynInst<Impl> 5912855Sgabeblack@google.com{ 6012855Sgabeblack@google.com public: 6112855Sgabeblack@google.com /** Typedef for the CPU. */ 6212855Sgabeblack@google.com typedef typename Impl::O3CPU O3CPU; 6312855Sgabeblack@google.com 6412855Sgabeblack@google.com /** Binary machine instruction type. */ 6512855Sgabeblack@google.com typedef TheISA::MachInst MachInst; 6612855Sgabeblack@google.com /** Extended machine instruction type. */ 6712855Sgabeblack@google.com typedef TheISA::ExtMachInst ExtMachInst; 6812855Sgabeblack@google.com /** Logical register index type. */ 6912855Sgabeblack@google.com typedef TheISA::RegIndex RegIndex; 7012855Sgabeblack@google.com /** Integer register index type. */ 7112855Sgabeblack@google.com typedef TheISA::IntReg IntReg; 7212855Sgabeblack@google.com typedef TheISA::FloatReg FloatReg; 7312855Sgabeblack@google.com typedef TheISA::FloatRegBits FloatRegBits; 7412855Sgabeblack@google.com typedef TheISA::CCReg CCReg; 7512855Sgabeblack@google.com 7612855Sgabeblack@google.com /** Misc register index type. */ 7712855Sgabeblack@google.com typedef TheISA::MiscReg MiscReg; 7812855Sgabeblack@google.com 7912855Sgabeblack@google.com enum { 8012855Sgabeblack@google.com MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs 8112855Sgabeblack@google.com MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs 8212855Sgabeblack@google.com }; 8312855Sgabeblack@google.com 8412855Sgabeblack@google.com public: 8512855Sgabeblack@google.com /** BaseDynInst constructor given a binary instruction. */ 8612855Sgabeblack@google.com BaseO3DynInst(StaticInstPtr staticInst, StaticInstPtr macroop, 8712855Sgabeblack@google.com TheISA::PCState pc, TheISA::PCState predPC, 8812855Sgabeblack@google.com InstSeqNum seq_num, O3CPU *cpu); 8912855Sgabeblack@google.com 9012855Sgabeblack@google.com /** BaseDynInst constructor given a static inst pointer. */ 9112855Sgabeblack@google.com BaseO3DynInst(StaticInstPtr _staticInst, StaticInstPtr _macroop); 9212855Sgabeblack@google.com 9312855Sgabeblack@google.com ~BaseO3DynInst(); 9412855Sgabeblack@google.com 9512855Sgabeblack@google.com /** Executes the instruction.*/ 9612855Sgabeblack@google.com Fault execute(); 9712855Sgabeblack@google.com 9812855Sgabeblack@google.com /** Initiates the access. Only valid for memory operations. */ 9912855Sgabeblack@google.com Fault initiateAcc(); 10012855Sgabeblack@google.com 10112855Sgabeblack@google.com /** Completes the access. Only valid for memory operations. */ 10212855Sgabeblack@google.com Fault completeAcc(PacketPtr pkt); 10312855Sgabeblack@google.com 10412855Sgabeblack@google.com private: 10512855Sgabeblack@google.com /** Initializes variables. */ 10612855Sgabeblack@google.com void initVars(); 10712855Sgabeblack@google.com 10812855Sgabeblack@google.com protected: 10912855Sgabeblack@google.com /** Values to be written to the destination misc. registers. */ 11012855Sgabeblack@google.com MiscReg _destMiscRegVal[TheISA::MaxMiscDestRegs]; 11112855Sgabeblack@google.com 11212855Sgabeblack@google.com /** Indexes of the destination misc. registers. They are needed to defer 11312855Sgabeblack@google.com * the write accesses to the misc. registers until the commit stage, when 11412855Sgabeblack@google.com * the instruction is out of its speculative state. 11512855Sgabeblack@google.com */ 11612855Sgabeblack@google.com short _destMiscRegIdx[TheISA::MaxMiscDestRegs]; 11712855Sgabeblack@google.com 11812855Sgabeblack@google.com /** Number of destination misc. registers. */ 11912855Sgabeblack@google.com uint8_t _numDestMiscRegs; 12012855Sgabeblack@google.com 12112855Sgabeblack@google.com 12212855Sgabeblack@google.com public: 12312855Sgabeblack@google.com#if TRACING_ON 12412855Sgabeblack@google.com /** Tick records used for the pipeline activity viewer. */ 12512855Sgabeblack@google.com Tick fetchTick; // instruction fetch is completed. 12612855Sgabeblack@google.com int32_t decodeTick; // instruction enters decode phase 12712855Sgabeblack@google.com int32_t renameTick; // instruction enters rename phase 12812855Sgabeblack@google.com int32_t dispatchTick; 12912855Sgabeblack@google.com int32_t issueTick; 13012855Sgabeblack@google.com int32_t completeTick; 13112855Sgabeblack@google.com int32_t commitTick; 13212855Sgabeblack@google.com int32_t storeTick; 13312855Sgabeblack@google.com#endif 13412855Sgabeblack@google.com 13512855Sgabeblack@google.com /** Reads a misc. register, including any side-effects the read 13612855Sgabeblack@google.com * might have as defined by the architecture. 13712855Sgabeblack@google.com */ 13812855Sgabeblack@google.com MiscReg readMiscReg(int misc_reg) 13912855Sgabeblack@google.com { 14012855Sgabeblack@google.com return this->cpu->readMiscReg(misc_reg, this->threadNumber); 14112855Sgabeblack@google.com } 142 143 /** Sets a misc. register, including any side-effects the write 144 * might have as defined by the architecture. 145 */ 146 void setMiscReg(int misc_reg, const MiscReg &val) 147 { 148 /** Writes to misc. registers are recorded and deferred until the 149 * commit stage, when updateMiscRegs() is called. First, check if 150 * the misc reg has been written before and update its value to be 151 * committed instead of making a new entry. If not, make a new 152 * entry and record the write. 153 */ 154 for (int idx = 0; idx < _numDestMiscRegs; idx++) { 155 if (_destMiscRegIdx[idx] == misc_reg) { 156 _destMiscRegVal[idx] = val; 157 return; 158 } 159 } 160 161 assert(_numDestMiscRegs < TheISA::MaxMiscDestRegs); 162 _destMiscRegIdx[_numDestMiscRegs] = misc_reg; 163 _destMiscRegVal[_numDestMiscRegs] = val; 164 _numDestMiscRegs++; 165 } 166 167 /** Reads a misc. register, including any side-effects the read 168 * might have as defined by the architecture. 169 */ 170 TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx) 171 { 172 return this->cpu->readMiscReg( 173 si->srcRegIdx(idx) - TheISA::Misc_Reg_Base, 174 this->threadNumber); 175 } 176 177 /** Sets a misc. register, including any side-effects the write 178 * might have as defined by the architecture. 179 */ 180 void setMiscRegOperand(const StaticInst *si, int idx, 181 const MiscReg &val) 182 { 183 int misc_reg = si->destRegIdx(idx) - TheISA::Misc_Reg_Base; 184 setMiscReg(misc_reg, val); 185 } 186 187 /** Called at the commit stage to update the misc. registers. */ 188 void updateMiscRegs() 189 { 190 // @todo: Pretty convoluted way to avoid squashing from happening when 191 // using the TC during an instruction's execution (specifically for 192 // instructions that have side-effects that use the TC). Fix this. 193 // See cpu/o3/dyn_inst_impl.hh. 194 bool no_squash_from_TC = this->thread->noSquashFromTC; 195 this->thread->noSquashFromTC = true; 196 197 for (int i = 0; i < _numDestMiscRegs; i++) 198 this->cpu->setMiscReg( 199 _destMiscRegIdx[i], _destMiscRegVal[i], this->threadNumber); 200 201 this->thread->noSquashFromTC = no_squash_from_TC; 202 } 203 204 void forwardOldRegs() 205 { 206 207 for (int idx = 0; idx < this->numDestRegs(); idx++) { 208 PhysRegIndex prev_phys_reg = this->prevDestRegIdx(idx); 209 TheISA::RegIndex original_dest_reg = 210 this->staticInst->destRegIdx(idx); 211 switch (regIdxToClass(original_dest_reg)) { 212 case IntRegClass: 213 this->setIntRegOperand(this->staticInst.get(), idx, 214 this->cpu->readIntReg(prev_phys_reg)); 215 break; 216 case FloatRegClass: 217 this->setFloatRegOperandBits(this->staticInst.get(), idx, 218 this->cpu->readFloatRegBits(prev_phys_reg)); 219 break; 220 case CCRegClass: 221 this->setCCRegOperand(this->staticInst.get(), idx, 222 this->cpu->readCCReg(prev_phys_reg)); 223 break; 224 case MiscRegClass: 225 // no need to forward misc reg values 226 break; 227 } 228 } 229 } 230 /** Calls hardware return from error interrupt. */ 231 Fault hwrei(); 232 /** Traps to handle specified fault. */ 233 void trap(Fault fault); 234 bool simPalCheck(int palFunc); 235 236 /** Emulates a syscall. */ 237 void syscall(int64_t callnum); 238 239 public: 240 241 // The register accessor methods provide the index of the 242 // instruction's operand (e.g., 0 or 1), not the architectural 243 // register index, to simplify the implementation of register 244 // renaming. We find the architectural register index by indexing 245 // into the instruction's own operand index table. Note that a 246 // raw pointer to the StaticInst is provided instead of a 247 // ref-counted StaticInstPtr to redice overhead. This is fine as 248 // long as these methods don't copy the pointer into any long-term 249 // storage (which is pretty hard to imagine they would have reason 250 // to do). 251 252 IntReg readIntRegOperand(const StaticInst *si, int idx) 253 { 254 return this->cpu->readIntReg(this->_srcRegIdx[idx]); 255 } 256 257 FloatReg readFloatRegOperand(const StaticInst *si, int idx) 258 { 259 return this->cpu->readFloatReg(this->_srcRegIdx[idx]); 260 } 261 262 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 263 { 264 return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]); 265 } 266 267 CCReg readCCRegOperand(const StaticInst *si, int idx) 268 { 269 return this->cpu->readCCReg(this->_srcRegIdx[idx]); 270 } 271 272 /** @todo: Make results into arrays so they can handle multiple dest 273 * registers. 274 */ 275 void setIntRegOperand(const StaticInst *si, int idx, IntReg val) 276 { 277 this->cpu->setIntReg(this->_destRegIdx[idx], val); 278 BaseDynInst<Impl>::setIntRegOperand(si, idx, val); 279 } 280 281 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 282 { 283 this->cpu->setFloatReg(this->_destRegIdx[idx], val); 284 BaseDynInst<Impl>::setFloatRegOperand(si, idx, val); 285 } 286 287 void setFloatRegOperandBits(const StaticInst *si, int idx, 288 FloatRegBits val) 289 { 290 this->cpu->setFloatRegBits(this->_destRegIdx[idx], val); 291 BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val); 292 } 293 294 void setCCRegOperand(const StaticInst *si, int idx, CCReg val) 295 { 296 this->cpu->setCCReg(this->_destRegIdx[idx], val); 297 BaseDynInst<Impl>::setCCRegOperand(si, idx, val); 298 } 299 300#if THE_ISA == MIPS_ISA 301 MiscReg readRegOtherThread(int misc_reg, ThreadID tid) 302 { 303 panic("MIPS MT not defined for O3 CPU.\n"); 304 return 0; 305 } 306 307 void setRegOtherThread(int misc_reg, MiscReg val, ThreadID tid) 308 { 309 panic("MIPS MT not defined for O3 CPU.\n"); 310 } 311#endif 312 313 public: 314 /** Calculates EA part of a memory instruction. Currently unused, 315 * though it may be useful in the future if we want to split 316 * memory operations into EA calculation and memory access parts. 317 */ 318 Fault calcEA() 319 { 320 return this->staticInst->eaCompInst()->execute(this, this->traceData); 321 } 322 323 /** Does the memory access part of a memory instruction. Currently unused, 324 * though it may be useful in the future if we want to split 325 * memory operations into EA calculation and memory access parts. 326 */ 327 Fault memAccess() 328 { 329 return this->staticInst->memAccInst()->execute(this, this->traceData); 330 } 331}; 332 333#endif // __CPU_O3_ALPHA_DYN_INST_HH__ 334 335