decode_impl.hh revision 9527:68154bc0e0ea
1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 */ 42 43#include "arch/types.hh" 44#include "base/trace.hh" 45#include "config/the_isa.hh" 46#include "cpu/o3/decode.hh" 47#include "cpu/inst_seq.hh" 48#include "debug/Activity.hh" 49#include "debug/Decode.hh" 50#include "debug/O3PipeView.hh" 51#include "params/DerivO3CPU.hh" 52#include "sim/full_system.hh" 53 54// clang complains about std::set being overloaded with Packet::set if 55// we open up the entire namespace std 56using std::list; 57 58template<class Impl> 59DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params) 60 : cpu(_cpu), 61 renameToDecodeDelay(params->renameToDecodeDelay), 62 iewToDecodeDelay(params->iewToDecodeDelay), 63 commitToDecodeDelay(params->commitToDecodeDelay), 64 fetchToDecodeDelay(params->fetchToDecodeDelay), 65 decodeWidth(params->decodeWidth), 66 numThreads(params->numThreads) 67{ 68 // @todo: Make into a parameter 69 skidBufferMax = (fetchToDecodeDelay + 1) * params->fetchWidth; 70} 71 72template<class Impl> 73void 74DefaultDecode<Impl>::startupStage() 75{ 76 resetStage(); 77} 78 79template<class Impl> 80void 81DefaultDecode<Impl>::resetStage() 82{ 83 _status = Inactive; 84 85 // Setup status, make sure stall signals are clear. 86 for (ThreadID tid = 0; tid < numThreads; ++tid) { 87 decodeStatus[tid] = Idle; 88 89 stalls[tid].rename = false; 90 stalls[tid].iew = false; 91 stalls[tid].commit = false; 92 } 93} 94 95template <class Impl> 96std::string 97DefaultDecode<Impl>::name() const 98{ 99 return cpu->name() + ".decode"; 100} 101 102template <class Impl> 103void 104DefaultDecode<Impl>::regStats() 105{ 106 decodeIdleCycles 107 .name(name() + ".IdleCycles") 108 .desc("Number of cycles decode is idle") 109 .prereq(decodeIdleCycles); 110 decodeBlockedCycles 111 .name(name() + ".BlockedCycles") 112 .desc("Number of cycles decode is blocked") 113 .prereq(decodeBlockedCycles); 114 decodeRunCycles 115 .name(name() + ".RunCycles") 116 .desc("Number of cycles decode is running") 117 .prereq(decodeRunCycles); 118 decodeUnblockCycles 119 .name(name() + ".UnblockCycles") 120 .desc("Number of cycles decode is unblocking") 121 .prereq(decodeUnblockCycles); 122 decodeSquashCycles 123 .name(name() + ".SquashCycles") 124 .desc("Number of cycles decode is squashing") 125 .prereq(decodeSquashCycles); 126 decodeBranchResolved 127 .name(name() + ".BranchResolved") 128 .desc("Number of times decode resolved a branch") 129 .prereq(decodeBranchResolved); 130 decodeBranchMispred 131 .name(name() + ".BranchMispred") 132 .desc("Number of times decode detected a branch misprediction") 133 .prereq(decodeBranchMispred); 134 decodeControlMispred 135 .name(name() + ".ControlMispred") 136 .desc("Number of times decode detected an instruction incorrectly" 137 " predicted as a control") 138 .prereq(decodeControlMispred); 139 decodeDecodedInsts 140 .name(name() + ".DecodedInsts") 141 .desc("Number of instructions handled by decode") 142 .prereq(decodeDecodedInsts); 143 decodeSquashedInsts 144 .name(name() + ".SquashedInsts") 145 .desc("Number of squashed instructions handled by decode") 146 .prereq(decodeSquashedInsts); 147} 148 149template<class Impl> 150void 151DefaultDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 152{ 153 timeBuffer = tb_ptr; 154 155 // Setup wire to write information back to fetch. 156 toFetch = timeBuffer->getWire(0); 157 158 // Create wires to get information from proper places in time buffer. 159 fromRename = timeBuffer->getWire(-renameToDecodeDelay); 160 fromIEW = timeBuffer->getWire(-iewToDecodeDelay); 161 fromCommit = timeBuffer->getWire(-commitToDecodeDelay); 162} 163 164template<class Impl> 165void 166DefaultDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 167{ 168 decodeQueue = dq_ptr; 169 170 // Setup wire to write information to proper place in decode queue. 171 toRename = decodeQueue->getWire(0); 172} 173 174template<class Impl> 175void 176DefaultDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 177{ 178 fetchQueue = fq_ptr; 179 180 // Setup wire to read information from fetch queue. 181 fromFetch = fetchQueue->getWire(-fetchToDecodeDelay); 182} 183 184template<class Impl> 185void 186DefaultDecode<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr) 187{ 188 activeThreads = at_ptr; 189} 190 191template <class Impl> 192void 193DefaultDecode<Impl>::drainSanityCheck() const 194{ 195 for (ThreadID tid = 0; tid < numThreads; ++tid) { 196 assert(insts[tid].empty()); 197 assert(skidBuffer[tid].empty()); 198 } 199} 200 201template<class Impl> 202bool 203DefaultDecode<Impl>::checkStall(ThreadID tid) const 204{ 205 bool ret_val = false; 206 207 if (stalls[tid].rename) { 208 DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid); 209 ret_val = true; 210 } else if (stalls[tid].iew) { 211 DPRINTF(Decode,"[tid:%i]: Stall fom IEW stage detected.\n", tid); 212 ret_val = true; 213 } else if (stalls[tid].commit) { 214 DPRINTF(Decode,"[tid:%i]: Stall fom Commit stage detected.\n", tid); 215 ret_val = true; 216 } 217 218 return ret_val; 219} 220 221template<class Impl> 222inline bool 223DefaultDecode<Impl>::fetchInstsValid() 224{ 225 return fromFetch->size > 0; 226} 227 228template<class Impl> 229bool 230DefaultDecode<Impl>::block(ThreadID tid) 231{ 232 DPRINTF(Decode, "[tid:%u]: Blocking.\n", tid); 233 234 // Add the current inputs to the skid buffer so they can be 235 // reprocessed when this stage unblocks. 236 skidInsert(tid); 237 238 // If the decode status is blocked or unblocking then decode has not yet 239 // signalled fetch to unblock. In that case, there is no need to tell 240 // fetch to block. 241 if (decodeStatus[tid] != Blocked) { 242 // Set the status to Blocked. 243 decodeStatus[tid] = Blocked; 244 245 if (toFetch->decodeUnblock[tid]) { 246 toFetch->decodeUnblock[tid] = false; 247 } else { 248 toFetch->decodeBlock[tid] = true; 249 wroteToTimeBuffer = true; 250 } 251 252 return true; 253 } 254 255 return false; 256} 257 258template<class Impl> 259bool 260DefaultDecode<Impl>::unblock(ThreadID tid) 261{ 262 // Decode is done unblocking only if the skid buffer is empty. 263 if (skidBuffer[tid].empty()) { 264 DPRINTF(Decode, "[tid:%u]: Done unblocking.\n", tid); 265 toFetch->decodeUnblock[tid] = true; 266 wroteToTimeBuffer = true; 267 268 decodeStatus[tid] = Running; 269 return true; 270 } 271 272 DPRINTF(Decode, "[tid:%u]: Currently unblocking.\n", tid); 273 274 return false; 275} 276 277template<class Impl> 278void 279DefaultDecode<Impl>::squash(DynInstPtr &inst, ThreadID tid) 280{ 281 DPRINTF(Decode, "[tid:%i]: [sn:%i] Squashing due to incorrect branch " 282 "prediction detected at decode.\n", tid, inst->seqNum); 283 284 // Send back mispredict information. 285 toFetch->decodeInfo[tid].branchMispredict = true; 286 toFetch->decodeInfo[tid].predIncorrect = true; 287 toFetch->decodeInfo[tid].mispredictInst = inst; 288 toFetch->decodeInfo[tid].squash = true; 289 toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum; 290 toFetch->decodeInfo[tid].nextPC = inst->branchTarget(); 291 toFetch->decodeInfo[tid].branchTaken = inst->pcState().branching(); 292 toFetch->decodeInfo[tid].squashInst = inst; 293 if (toFetch->decodeInfo[tid].mispredictInst->isUncondCtrl()) { 294 toFetch->decodeInfo[tid].branchTaken = true; 295 } 296 297 InstSeqNum squash_seq_num = inst->seqNum; 298 299 // Might have to tell fetch to unblock. 300 if (decodeStatus[tid] == Blocked || 301 decodeStatus[tid] == Unblocking) { 302 toFetch->decodeUnblock[tid] = 1; 303 } 304 305 // Set status to squashing. 306 decodeStatus[tid] = Squashing; 307 308 for (int i=0; i<fromFetch->size; i++) { 309 if (fromFetch->insts[i]->threadNumber == tid && 310 fromFetch->insts[i]->seqNum > squash_seq_num) { 311 fromFetch->insts[i]->setSquashed(); 312 } 313 } 314 315 // Clear the instruction list and skid buffer in case they have any 316 // insts in them. 317 while (!insts[tid].empty()) { 318 insts[tid].pop(); 319 } 320 321 while (!skidBuffer[tid].empty()) { 322 skidBuffer[tid].pop(); 323 } 324 325 // Squash instructions up until this one 326 cpu->removeInstsUntil(squash_seq_num, tid); 327} 328 329template<class Impl> 330unsigned 331DefaultDecode<Impl>::squash(ThreadID tid) 332{ 333 DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid); 334 335 if (decodeStatus[tid] == Blocked || 336 decodeStatus[tid] == Unblocking) { 337 if (FullSystem) { 338 toFetch->decodeUnblock[tid] = 1; 339 } else { 340 // In syscall emulation, we can have both a block and a squash due 341 // to a syscall in the same cycle. This would cause both signals 342 // to be high. This shouldn't happen in full system. 343 // @todo: Determine if this still happens. 344 if (toFetch->decodeBlock[tid]) 345 toFetch->decodeBlock[tid] = 0; 346 else 347 toFetch->decodeUnblock[tid] = 1; 348 } 349 } 350 351 // Set status to squashing. 352 decodeStatus[tid] = Squashing; 353 354 // Go through incoming instructions from fetch and squash them. 355 unsigned squash_count = 0; 356 357 for (int i=0; i<fromFetch->size; i++) { 358 if (fromFetch->insts[i]->threadNumber == tid) { 359 fromFetch->insts[i]->setSquashed(); 360 squash_count++; 361 } 362 } 363 364 // Clear the instruction list and skid buffer in case they have any 365 // insts in them. 366 while (!insts[tid].empty()) { 367 insts[tid].pop(); 368 } 369 370 while (!skidBuffer[tid].empty()) { 371 skidBuffer[tid].pop(); 372 } 373 374 return squash_count; 375} 376 377template<class Impl> 378void 379DefaultDecode<Impl>::skidInsert(ThreadID tid) 380{ 381 DynInstPtr inst = NULL; 382 383 while (!insts[tid].empty()) { 384 inst = insts[tid].front(); 385 386 insts[tid].pop(); 387 388 assert(tid == inst->threadNumber); 389 390 DPRINTF(Decode,"Inserting [sn:%lli] PC: %s into decode skidBuffer %i\n", 391 inst->seqNum, inst->pcState(), inst->threadNumber); 392 393 skidBuffer[tid].push(inst); 394 } 395 396 // @todo: Eventually need to enforce this by not letting a thread 397 // fetch past its skidbuffer 398 assert(skidBuffer[tid].size() <= skidBufferMax); 399} 400 401template<class Impl> 402bool 403DefaultDecode<Impl>::skidsEmpty() 404{ 405 list<ThreadID>::iterator threads = activeThreads->begin(); 406 list<ThreadID>::iterator end = activeThreads->end(); 407 408 while (threads != end) { 409 ThreadID tid = *threads++; 410 if (!skidBuffer[tid].empty()) 411 return false; 412 } 413 414 return true; 415} 416 417template<class Impl> 418void 419DefaultDecode<Impl>::updateStatus() 420{ 421 bool any_unblocking = false; 422 423 list<ThreadID>::iterator threads = activeThreads->begin(); 424 list<ThreadID>::iterator end = activeThreads->end(); 425 426 while (threads != end) { 427 ThreadID tid = *threads++; 428 429 if (decodeStatus[tid] == Unblocking) { 430 any_unblocking = true; 431 break; 432 } 433 } 434 435 // Decode will have activity if it's unblocking. 436 if (any_unblocking) { 437 if (_status == Inactive) { 438 _status = Active; 439 440 DPRINTF(Activity, "Activating stage.\n"); 441 442 cpu->activateStage(O3CPU::DecodeIdx); 443 } 444 } else { 445 // If it's not unblocking, then decode will not have any internal 446 // activity. Switch it to inactive. 447 if (_status == Active) { 448 _status = Inactive; 449 DPRINTF(Activity, "Deactivating stage.\n"); 450 451 cpu->deactivateStage(O3CPU::DecodeIdx); 452 } 453 } 454} 455 456template <class Impl> 457void 458DefaultDecode<Impl>::sortInsts() 459{ 460 int insts_from_fetch = fromFetch->size; 461 for (int i = 0; i < insts_from_fetch; ++i) { 462 insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]); 463 } 464} 465 466template<class Impl> 467void 468DefaultDecode<Impl>::readStallSignals(ThreadID tid) 469{ 470 if (fromRename->renameBlock[tid]) { 471 stalls[tid].rename = true; 472 } 473 474 if (fromRename->renameUnblock[tid]) { 475 assert(stalls[tid].rename); 476 stalls[tid].rename = false; 477 } 478 479 if (fromIEW->iewBlock[tid]) { 480 stalls[tid].iew = true; 481 } 482 483 if (fromIEW->iewUnblock[tid]) { 484 assert(stalls[tid].iew); 485 stalls[tid].iew = false; 486 } 487 488 if (fromCommit->commitBlock[tid]) { 489 stalls[tid].commit = true; 490 } 491 492 if (fromCommit->commitUnblock[tid]) { 493 assert(stalls[tid].commit); 494 stalls[tid].commit = false; 495 } 496} 497 498template <class Impl> 499bool 500DefaultDecode<Impl>::checkSignalsAndUpdate(ThreadID tid) 501{ 502 // Check if there's a squash signal, squash if there is. 503 // Check stall signals, block if necessary. 504 // If status was blocked 505 // Check if stall conditions have passed 506 // if so then go to unblocking 507 // If status was Squashing 508 // check if squashing is not high. Switch to running this cycle. 509 510 // Update the per thread stall statuses. 511 readStallSignals(tid); 512 513 // Check squash signals from commit. 514 if (fromCommit->commitInfo[tid].squash) { 515 516 DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash " 517 "from commit.\n", tid); 518 519 squash(tid); 520 521 return true; 522 } 523 524 // Check ROB squash signals from commit. 525 if (fromCommit->commitInfo[tid].robSquashing) { 526 DPRINTF(Decode, "[tid:%u]: ROB is still squashing.\n", tid); 527 528 // Continue to squash. 529 decodeStatus[tid] = Squashing; 530 531 return true; 532 } 533 534 if (checkStall(tid)) { 535 return block(tid); 536 } 537 538 if (decodeStatus[tid] == Blocked) { 539 DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n", 540 tid); 541 542 decodeStatus[tid] = Unblocking; 543 544 unblock(tid); 545 546 return true; 547 } 548 549 if (decodeStatus[tid] == Squashing) { 550 // Switch status to running if decode isn't being told to block or 551 // squash this cycle. 552 DPRINTF(Decode, "[tid:%u]: Done squashing, switching to running.\n", 553 tid); 554 555 decodeStatus[tid] = Running; 556 557 return false; 558 } 559 560 // If we've reached this point, we have not gotten any signals that 561 // cause decode to change its status. Decode remains the same as before. 562 return false; 563} 564 565template<class Impl> 566void 567DefaultDecode<Impl>::tick() 568{ 569 wroteToTimeBuffer = false; 570 571 bool status_change = false; 572 573 toRenameIndex = 0; 574 575 list<ThreadID>::iterator threads = activeThreads->begin(); 576 list<ThreadID>::iterator end = activeThreads->end(); 577 578 sortInsts(); 579 580 //Check stall and squash signals. 581 while (threads != end) { 582 ThreadID tid = *threads++; 583 584 DPRINTF(Decode,"Processing [tid:%i]\n",tid); 585 status_change = checkSignalsAndUpdate(tid) || status_change; 586 587 decode(status_change, tid); 588 } 589 590 if (status_change) { 591 updateStatus(); 592 } 593 594 if (wroteToTimeBuffer) { 595 DPRINTF(Activity, "Activity this cycle.\n"); 596 597 cpu->activityThisCycle(); 598 } 599} 600 601template<class Impl> 602void 603DefaultDecode<Impl>::decode(bool &status_change, ThreadID tid) 604{ 605 // If status is Running or idle, 606 // call decodeInsts() 607 // If status is Unblocking, 608 // buffer any instructions coming from fetch 609 // continue trying to empty skid buffer 610 // check if stall conditions have passed 611 612 if (decodeStatus[tid] == Blocked) { 613 ++decodeBlockedCycles; 614 } else if (decodeStatus[tid] == Squashing) { 615 ++decodeSquashCycles; 616 } 617 618 // Decode should try to decode as many instructions as its bandwidth 619 // will allow, as long as it is not currently blocked. 620 if (decodeStatus[tid] == Running || 621 decodeStatus[tid] == Idle) { 622 DPRINTF(Decode, "[tid:%u]: Not blocked, so attempting to run " 623 "stage.\n",tid); 624 625 decodeInsts(tid); 626 } else if (decodeStatus[tid] == Unblocking) { 627 // Make sure that the skid buffer has something in it if the 628 // status is unblocking. 629 assert(!skidsEmpty()); 630 631 // If the status was unblocking, then instructions from the skid 632 // buffer were used. Remove those instructions and handle 633 // the rest of unblocking. 634 decodeInsts(tid); 635 636 if (fetchInstsValid()) { 637 // Add the current inputs to the skid buffer so they can be 638 // reprocessed when this stage unblocks. 639 skidInsert(tid); 640 } 641 642 status_change = unblock(tid) || status_change; 643 } 644} 645 646template <class Impl> 647void 648DefaultDecode<Impl>::decodeInsts(ThreadID tid) 649{ 650 // Instructions can come either from the skid buffer or the list of 651 // instructions coming from fetch, depending on decode's status. 652 int insts_available = decodeStatus[tid] == Unblocking ? 653 skidBuffer[tid].size() : insts[tid].size(); 654 655 if (insts_available == 0) { 656 DPRINTF(Decode, "[tid:%u] Nothing to do, breaking out" 657 " early.\n",tid); 658 // Should I change the status to idle? 659 ++decodeIdleCycles; 660 return; 661 } else if (decodeStatus[tid] == Unblocking) { 662 DPRINTF(Decode, "[tid:%u] Unblocking, removing insts from skid " 663 "buffer.\n",tid); 664 ++decodeUnblockCycles; 665 } else if (decodeStatus[tid] == Running) { 666 ++decodeRunCycles; 667 } 668 669 DynInstPtr inst; 670 671 std::queue<DynInstPtr> 672 &insts_to_decode = decodeStatus[tid] == Unblocking ? 673 skidBuffer[tid] : insts[tid]; 674 675 DPRINTF(Decode, "[tid:%u]: Sending instruction to rename.\n",tid); 676 677 while (insts_available > 0 && toRenameIndex < decodeWidth) { 678 assert(!insts_to_decode.empty()); 679 680 inst = insts_to_decode.front(); 681 682 insts_to_decode.pop(); 683 684 DPRINTF(Decode, "[tid:%u]: Processing instruction [sn:%lli] with " 685 "PC %s\n", tid, inst->seqNum, inst->pcState()); 686 687 if (inst->isSquashed()) { 688 DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %s is " 689 "squashed, skipping.\n", 690 tid, inst->seqNum, inst->pcState()); 691 692 ++decodeSquashedInsts; 693 694 --insts_available; 695 696 continue; 697 } 698 699 // Also check if instructions have no source registers. Mark 700 // them as ready to issue at any time. Not sure if this check 701 // should exist here or at a later stage; however it doesn't matter 702 // too much for function correctness. 703 if (inst->numSrcRegs() == 0) { 704 inst->setCanIssue(); 705 } 706 707 // This current instruction is valid, so add it into the decode 708 // queue. The next instruction may not be valid, so check to 709 // see if branches were predicted correctly. 710 toRename->insts[toRenameIndex] = inst; 711 712 ++(toRename->size); 713 ++toRenameIndex; 714 ++decodeDecodedInsts; 715 --insts_available; 716 717#if TRACING_ON 718 if (DTRACE(O3PipeView)) { 719 inst->decodeTick = curTick() - inst->fetchTick; 720 } 721#endif 722 723 // Ensure that if it was predicted as a branch, it really is a 724 // branch. 725 if (inst->readPredTaken() && !inst->isControl()) { 726 panic("Instruction predicted as a branch!"); 727 728 ++decodeControlMispred; 729 730 // Might want to set some sort of boolean and just do 731 // a check at the end 732 squash(inst, inst->threadNumber); 733 734 break; 735 } 736 737 // Go ahead and compute any PC-relative branches. 738 if (inst->isDirectCtrl() && inst->isUncondCtrl()) { 739 ++decodeBranchResolved; 740 741 if (!(inst->branchTarget() == inst->readPredTarg())) { 742 ++decodeBranchMispred; 743 744 // Might want to set some sort of boolean and just do 745 // a check at the end 746 squash(inst, inst->threadNumber); 747 TheISA::PCState target = inst->branchTarget(); 748 749 DPRINTF(Decode, "[sn:%i]: Updating predictions: PredPC: %s\n", 750 inst->seqNum, target); 751 //The micro pc after an instruction level branch should be 0 752 inst->setPredTarg(target); 753 break; 754 } 755 } 756 } 757 758 // If we didn't process all instructions, then we will need to block 759 // and put all those instructions into the skid buffer. 760 if (!insts_to_decode.empty()) { 761 block(tid); 762 } 763 764 // Record that decode has written to the time buffer for activity 765 // tracking. 766 if (toRenameIndex) { 767 wroteToTimeBuffer = true; 768 } 769} 770