decode_impl.hh revision 9514
1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 */ 42 43#include "arch/types.hh" 44#include "base/trace.hh" 45#include "config/the_isa.hh" 46#include "cpu/o3/decode.hh" 47#include "cpu/inst_seq.hh" 48#include "debug/Activity.hh" 49#include "debug/Decode.hh" 50#include "params/DerivO3CPU.hh" 51#include "sim/full_system.hh" 52 53// clang complains about std::set being overloaded with Packet::set if 54// we open up the entire namespace std 55using std::list; 56 57template<class Impl> 58DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params) 59 : cpu(_cpu), 60 renameToDecodeDelay(params->renameToDecodeDelay), 61 iewToDecodeDelay(params->iewToDecodeDelay), 62 commitToDecodeDelay(params->commitToDecodeDelay), 63 fetchToDecodeDelay(params->fetchToDecodeDelay), 64 decodeWidth(params->decodeWidth), 65 numThreads(params->numThreads) 66{ 67 // @todo: Make into a parameter 68 skidBufferMax = (fetchToDecodeDelay + 1) * params->fetchWidth; 69} 70 71template<class Impl> 72void 73DefaultDecode<Impl>::startupStage() 74{ 75 resetStage(); 76} 77 78template<class Impl> 79void 80DefaultDecode<Impl>::resetStage() 81{ 82 _status = Inactive; 83 84 // Setup status, make sure stall signals are clear. 85 for (ThreadID tid = 0; tid < numThreads; ++tid) { 86 decodeStatus[tid] = Idle; 87 88 stalls[tid].rename = false; 89 stalls[tid].iew = false; 90 stalls[tid].commit = false; 91 } 92} 93 94template <class Impl> 95std::string 96DefaultDecode<Impl>::name() const 97{ 98 return cpu->name() + ".decode"; 99} 100 101template <class Impl> 102void 103DefaultDecode<Impl>::regStats() 104{ 105 decodeIdleCycles 106 .name(name() + ".IdleCycles") 107 .desc("Number of cycles decode is idle") 108 .prereq(decodeIdleCycles); 109 decodeBlockedCycles 110 .name(name() + ".BlockedCycles") 111 .desc("Number of cycles decode is blocked") 112 .prereq(decodeBlockedCycles); 113 decodeRunCycles 114 .name(name() + ".RunCycles") 115 .desc("Number of cycles decode is running") 116 .prereq(decodeRunCycles); 117 decodeUnblockCycles 118 .name(name() + ".UnblockCycles") 119 .desc("Number of cycles decode is unblocking") 120 .prereq(decodeUnblockCycles); 121 decodeSquashCycles 122 .name(name() + ".SquashCycles") 123 .desc("Number of cycles decode is squashing") 124 .prereq(decodeSquashCycles); 125 decodeBranchResolved 126 .name(name() + ".BranchResolved") 127 .desc("Number of times decode resolved a branch") 128 .prereq(decodeBranchResolved); 129 decodeBranchMispred 130 .name(name() + ".BranchMispred") 131 .desc("Number of times decode detected a branch misprediction") 132 .prereq(decodeBranchMispred); 133 decodeControlMispred 134 .name(name() + ".ControlMispred") 135 .desc("Number of times decode detected an instruction incorrectly" 136 " predicted as a control") 137 .prereq(decodeControlMispred); 138 decodeDecodedInsts 139 .name(name() + ".DecodedInsts") 140 .desc("Number of instructions handled by decode") 141 .prereq(decodeDecodedInsts); 142 decodeSquashedInsts 143 .name(name() + ".SquashedInsts") 144 .desc("Number of squashed instructions handled by decode") 145 .prereq(decodeSquashedInsts); 146} 147 148template<class Impl> 149void 150DefaultDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 151{ 152 timeBuffer = tb_ptr; 153 154 // Setup wire to write information back to fetch. 155 toFetch = timeBuffer->getWire(0); 156 157 // Create wires to get information from proper places in time buffer. 158 fromRename = timeBuffer->getWire(-renameToDecodeDelay); 159 fromIEW = timeBuffer->getWire(-iewToDecodeDelay); 160 fromCommit = timeBuffer->getWire(-commitToDecodeDelay); 161} 162 163template<class Impl> 164void 165DefaultDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 166{ 167 decodeQueue = dq_ptr; 168 169 // Setup wire to write information to proper place in decode queue. 170 toRename = decodeQueue->getWire(0); 171} 172 173template<class Impl> 174void 175DefaultDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 176{ 177 fetchQueue = fq_ptr; 178 179 // Setup wire to read information from fetch queue. 180 fromFetch = fetchQueue->getWire(-fetchToDecodeDelay); 181} 182 183template<class Impl> 184void 185DefaultDecode<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr) 186{ 187 activeThreads = at_ptr; 188} 189 190template <class Impl> 191void 192DefaultDecode<Impl>::drainSanityCheck() const 193{ 194 for (ThreadID tid = 0; tid < numThreads; ++tid) { 195 assert(insts[tid].empty()); 196 assert(skidBuffer[tid].empty()); 197 } 198} 199 200template<class Impl> 201bool 202DefaultDecode<Impl>::checkStall(ThreadID tid) const 203{ 204 bool ret_val = false; 205 206 if (stalls[tid].rename) { 207 DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid); 208 ret_val = true; 209 } else if (stalls[tid].iew) { 210 DPRINTF(Decode,"[tid:%i]: Stall fom IEW stage detected.\n", tid); 211 ret_val = true; 212 } else if (stalls[tid].commit) { 213 DPRINTF(Decode,"[tid:%i]: Stall fom Commit stage detected.\n", tid); 214 ret_val = true; 215 } 216 217 return ret_val; 218} 219 220template<class Impl> 221inline bool 222DefaultDecode<Impl>::fetchInstsValid() 223{ 224 return fromFetch->size > 0; 225} 226 227template<class Impl> 228bool 229DefaultDecode<Impl>::block(ThreadID tid) 230{ 231 DPRINTF(Decode, "[tid:%u]: Blocking.\n", tid); 232 233 // Add the current inputs to the skid buffer so they can be 234 // reprocessed when this stage unblocks. 235 skidInsert(tid); 236 237 // If the decode status is blocked or unblocking then decode has not yet 238 // signalled fetch to unblock. In that case, there is no need to tell 239 // fetch to block. 240 if (decodeStatus[tid] != Blocked) { 241 // Set the status to Blocked. 242 decodeStatus[tid] = Blocked; 243 244 if (toFetch->decodeUnblock[tid]) { 245 toFetch->decodeUnblock[tid] = false; 246 } else { 247 toFetch->decodeBlock[tid] = true; 248 wroteToTimeBuffer = true; 249 } 250 251 return true; 252 } 253 254 return false; 255} 256 257template<class Impl> 258bool 259DefaultDecode<Impl>::unblock(ThreadID tid) 260{ 261 // Decode is done unblocking only if the skid buffer is empty. 262 if (skidBuffer[tid].empty()) { 263 DPRINTF(Decode, "[tid:%u]: Done unblocking.\n", tid); 264 toFetch->decodeUnblock[tid] = true; 265 wroteToTimeBuffer = true; 266 267 decodeStatus[tid] = Running; 268 return true; 269 } 270 271 DPRINTF(Decode, "[tid:%u]: Currently unblocking.\n", tid); 272 273 return false; 274} 275 276template<class Impl> 277void 278DefaultDecode<Impl>::squash(DynInstPtr &inst, ThreadID tid) 279{ 280 DPRINTF(Decode, "[tid:%i]: [sn:%i] Squashing due to incorrect branch " 281 "prediction detected at decode.\n", tid, inst->seqNum); 282 283 // Send back mispredict information. 284 toFetch->decodeInfo[tid].branchMispredict = true; 285 toFetch->decodeInfo[tid].predIncorrect = true; 286 toFetch->decodeInfo[tid].mispredictInst = inst; 287 toFetch->decodeInfo[tid].squash = true; 288 toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum; 289 toFetch->decodeInfo[tid].nextPC = inst->branchTarget(); 290 toFetch->decodeInfo[tid].branchTaken = inst->pcState().branching(); 291 toFetch->decodeInfo[tid].squashInst = inst; 292 if (toFetch->decodeInfo[tid].mispredictInst->isUncondCtrl()) { 293 toFetch->decodeInfo[tid].branchTaken = true; 294 } 295 296 InstSeqNum squash_seq_num = inst->seqNum; 297 298 // Might have to tell fetch to unblock. 299 if (decodeStatus[tid] == Blocked || 300 decodeStatus[tid] == Unblocking) { 301 toFetch->decodeUnblock[tid] = 1; 302 } 303 304 // Set status to squashing. 305 decodeStatus[tid] = Squashing; 306 307 for (int i=0; i<fromFetch->size; i++) { 308 if (fromFetch->insts[i]->threadNumber == tid && 309 fromFetch->insts[i]->seqNum > squash_seq_num) { 310 fromFetch->insts[i]->setSquashed(); 311 } 312 } 313 314 // Clear the instruction list and skid buffer in case they have any 315 // insts in them. 316 while (!insts[tid].empty()) { 317 insts[tid].pop(); 318 } 319 320 while (!skidBuffer[tid].empty()) { 321 skidBuffer[tid].pop(); 322 } 323 324 // Squash instructions up until this one 325 cpu->removeInstsUntil(squash_seq_num, tid); 326} 327 328template<class Impl> 329unsigned 330DefaultDecode<Impl>::squash(ThreadID tid) 331{ 332 DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid); 333 334 if (decodeStatus[tid] == Blocked || 335 decodeStatus[tid] == Unblocking) { 336 if (FullSystem) { 337 toFetch->decodeUnblock[tid] = 1; 338 } else { 339 // In syscall emulation, we can have both a block and a squash due 340 // to a syscall in the same cycle. This would cause both signals 341 // to be high. This shouldn't happen in full system. 342 // @todo: Determine if this still happens. 343 if (toFetch->decodeBlock[tid]) 344 toFetch->decodeBlock[tid] = 0; 345 else 346 toFetch->decodeUnblock[tid] = 1; 347 } 348 } 349 350 // Set status to squashing. 351 decodeStatus[tid] = Squashing; 352 353 // Go through incoming instructions from fetch and squash them. 354 unsigned squash_count = 0; 355 356 for (int i=0; i<fromFetch->size; i++) { 357 if (fromFetch->insts[i]->threadNumber == tid) { 358 fromFetch->insts[i]->setSquashed(); 359 squash_count++; 360 } 361 } 362 363 // Clear the instruction list and skid buffer in case they have any 364 // insts in them. 365 while (!insts[tid].empty()) { 366 insts[tid].pop(); 367 } 368 369 while (!skidBuffer[tid].empty()) { 370 skidBuffer[tid].pop(); 371 } 372 373 return squash_count; 374} 375 376template<class Impl> 377void 378DefaultDecode<Impl>::skidInsert(ThreadID tid) 379{ 380 DynInstPtr inst = NULL; 381 382 while (!insts[tid].empty()) { 383 inst = insts[tid].front(); 384 385 insts[tid].pop(); 386 387 assert(tid == inst->threadNumber); 388 389 DPRINTF(Decode,"Inserting [sn:%lli] PC: %s into decode skidBuffer %i\n", 390 inst->seqNum, inst->pcState(), inst->threadNumber); 391 392 skidBuffer[tid].push(inst); 393 } 394 395 // @todo: Eventually need to enforce this by not letting a thread 396 // fetch past its skidbuffer 397 assert(skidBuffer[tid].size() <= skidBufferMax); 398} 399 400template<class Impl> 401bool 402DefaultDecode<Impl>::skidsEmpty() 403{ 404 list<ThreadID>::iterator threads = activeThreads->begin(); 405 list<ThreadID>::iterator end = activeThreads->end(); 406 407 while (threads != end) { 408 ThreadID tid = *threads++; 409 if (!skidBuffer[tid].empty()) 410 return false; 411 } 412 413 return true; 414} 415 416template<class Impl> 417void 418DefaultDecode<Impl>::updateStatus() 419{ 420 bool any_unblocking = false; 421 422 list<ThreadID>::iterator threads = activeThreads->begin(); 423 list<ThreadID>::iterator end = activeThreads->end(); 424 425 while (threads != end) { 426 ThreadID tid = *threads++; 427 428 if (decodeStatus[tid] == Unblocking) { 429 any_unblocking = true; 430 break; 431 } 432 } 433 434 // Decode will have activity if it's unblocking. 435 if (any_unblocking) { 436 if (_status == Inactive) { 437 _status = Active; 438 439 DPRINTF(Activity, "Activating stage.\n"); 440 441 cpu->activateStage(O3CPU::DecodeIdx); 442 } 443 } else { 444 // If it's not unblocking, then decode will not have any internal 445 // activity. Switch it to inactive. 446 if (_status == Active) { 447 _status = Inactive; 448 DPRINTF(Activity, "Deactivating stage.\n"); 449 450 cpu->deactivateStage(O3CPU::DecodeIdx); 451 } 452 } 453} 454 455template <class Impl> 456void 457DefaultDecode<Impl>::sortInsts() 458{ 459 int insts_from_fetch = fromFetch->size; 460 for (int i = 0; i < insts_from_fetch; ++i) { 461 insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]); 462 } 463} 464 465template<class Impl> 466void 467DefaultDecode<Impl>::readStallSignals(ThreadID tid) 468{ 469 if (fromRename->renameBlock[tid]) { 470 stalls[tid].rename = true; 471 } 472 473 if (fromRename->renameUnblock[tid]) { 474 assert(stalls[tid].rename); 475 stalls[tid].rename = false; 476 } 477 478 if (fromIEW->iewBlock[tid]) { 479 stalls[tid].iew = true; 480 } 481 482 if (fromIEW->iewUnblock[tid]) { 483 assert(stalls[tid].iew); 484 stalls[tid].iew = false; 485 } 486 487 if (fromCommit->commitBlock[tid]) { 488 stalls[tid].commit = true; 489 } 490 491 if (fromCommit->commitUnblock[tid]) { 492 assert(stalls[tid].commit); 493 stalls[tid].commit = false; 494 } 495} 496 497template <class Impl> 498bool 499DefaultDecode<Impl>::checkSignalsAndUpdate(ThreadID tid) 500{ 501 // Check if there's a squash signal, squash if there is. 502 // Check stall signals, block if necessary. 503 // If status was blocked 504 // Check if stall conditions have passed 505 // if so then go to unblocking 506 // If status was Squashing 507 // check if squashing is not high. Switch to running this cycle. 508 509 // Update the per thread stall statuses. 510 readStallSignals(tid); 511 512 // Check squash signals from commit. 513 if (fromCommit->commitInfo[tid].squash) { 514 515 DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash " 516 "from commit.\n", tid); 517 518 squash(tid); 519 520 return true; 521 } 522 523 // Check ROB squash signals from commit. 524 if (fromCommit->commitInfo[tid].robSquashing) { 525 DPRINTF(Decode, "[tid:%u]: ROB is still squashing.\n", tid); 526 527 // Continue to squash. 528 decodeStatus[tid] = Squashing; 529 530 return true; 531 } 532 533 if (checkStall(tid)) { 534 return block(tid); 535 } 536 537 if (decodeStatus[tid] == Blocked) { 538 DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n", 539 tid); 540 541 decodeStatus[tid] = Unblocking; 542 543 unblock(tid); 544 545 return true; 546 } 547 548 if (decodeStatus[tid] == Squashing) { 549 // Switch status to running if decode isn't being told to block or 550 // squash this cycle. 551 DPRINTF(Decode, "[tid:%u]: Done squashing, switching to running.\n", 552 tid); 553 554 decodeStatus[tid] = Running; 555 556 return false; 557 } 558 559 // If we've reached this point, we have not gotten any signals that 560 // cause decode to change its status. Decode remains the same as before. 561 return false; 562} 563 564template<class Impl> 565void 566DefaultDecode<Impl>::tick() 567{ 568 wroteToTimeBuffer = false; 569 570 bool status_change = false; 571 572 toRenameIndex = 0; 573 574 list<ThreadID>::iterator threads = activeThreads->begin(); 575 list<ThreadID>::iterator end = activeThreads->end(); 576 577 sortInsts(); 578 579 //Check stall and squash signals. 580 while (threads != end) { 581 ThreadID tid = *threads++; 582 583 DPRINTF(Decode,"Processing [tid:%i]\n",tid); 584 status_change = checkSignalsAndUpdate(tid) || status_change; 585 586 decode(status_change, tid); 587 } 588 589 if (status_change) { 590 updateStatus(); 591 } 592 593 if (wroteToTimeBuffer) { 594 DPRINTF(Activity, "Activity this cycle.\n"); 595 596 cpu->activityThisCycle(); 597 } 598} 599 600template<class Impl> 601void 602DefaultDecode<Impl>::decode(bool &status_change, ThreadID tid) 603{ 604 // If status is Running or idle, 605 // call decodeInsts() 606 // If status is Unblocking, 607 // buffer any instructions coming from fetch 608 // continue trying to empty skid buffer 609 // check if stall conditions have passed 610 611 if (decodeStatus[tid] == Blocked) { 612 ++decodeBlockedCycles; 613 } else if (decodeStatus[tid] == Squashing) { 614 ++decodeSquashCycles; 615 } 616 617 // Decode should try to decode as many instructions as its bandwidth 618 // will allow, as long as it is not currently blocked. 619 if (decodeStatus[tid] == Running || 620 decodeStatus[tid] == Idle) { 621 DPRINTF(Decode, "[tid:%u]: Not blocked, so attempting to run " 622 "stage.\n",tid); 623 624 decodeInsts(tid); 625 } else if (decodeStatus[tid] == Unblocking) { 626 // Make sure that the skid buffer has something in it if the 627 // status is unblocking. 628 assert(!skidsEmpty()); 629 630 // If the status was unblocking, then instructions from the skid 631 // buffer were used. Remove those instructions and handle 632 // the rest of unblocking. 633 decodeInsts(tid); 634 635 if (fetchInstsValid()) { 636 // Add the current inputs to the skid buffer so they can be 637 // reprocessed when this stage unblocks. 638 skidInsert(tid); 639 } 640 641 status_change = unblock(tid) || status_change; 642 } 643} 644 645template <class Impl> 646void 647DefaultDecode<Impl>::decodeInsts(ThreadID tid) 648{ 649 // Instructions can come either from the skid buffer or the list of 650 // instructions coming from fetch, depending on decode's status. 651 int insts_available = decodeStatus[tid] == Unblocking ? 652 skidBuffer[tid].size() : insts[tid].size(); 653 654 if (insts_available == 0) { 655 DPRINTF(Decode, "[tid:%u] Nothing to do, breaking out" 656 " early.\n",tid); 657 // Should I change the status to idle? 658 ++decodeIdleCycles; 659 return; 660 } else if (decodeStatus[tid] == Unblocking) { 661 DPRINTF(Decode, "[tid:%u] Unblocking, removing insts from skid " 662 "buffer.\n",tid); 663 ++decodeUnblockCycles; 664 } else if (decodeStatus[tid] == Running) { 665 ++decodeRunCycles; 666 } 667 668 DynInstPtr inst; 669 670 std::queue<DynInstPtr> 671 &insts_to_decode = decodeStatus[tid] == Unblocking ? 672 skidBuffer[tid] : insts[tid]; 673 674 DPRINTF(Decode, "[tid:%u]: Sending instruction to rename.\n",tid); 675 676 while (insts_available > 0 && toRenameIndex < decodeWidth) { 677 assert(!insts_to_decode.empty()); 678 679 inst = insts_to_decode.front(); 680 681 insts_to_decode.pop(); 682 683 DPRINTF(Decode, "[tid:%u]: Processing instruction [sn:%lli] with " 684 "PC %s\n", tid, inst->seqNum, inst->pcState()); 685 686 if (inst->isSquashed()) { 687 DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %s is " 688 "squashed, skipping.\n", 689 tid, inst->seqNum, inst->pcState()); 690 691 ++decodeSquashedInsts; 692 693 --insts_available; 694 695 continue; 696 } 697 698 // Also check if instructions have no source registers. Mark 699 // them as ready to issue at any time. Not sure if this check 700 // should exist here or at a later stage; however it doesn't matter 701 // too much for function correctness. 702 if (inst->numSrcRegs() == 0) { 703 inst->setCanIssue(); 704 } 705 706 // This current instruction is valid, so add it into the decode 707 // queue. The next instruction may not be valid, so check to 708 // see if branches were predicted correctly. 709 toRename->insts[toRenameIndex] = inst; 710 711 ++(toRename->size); 712 ++toRenameIndex; 713 ++decodeDecodedInsts; 714 --insts_available; 715 716#if TRACING_ON 717 inst->decodeTick = curTick() - inst->fetchTick; 718#endif 719 720 // Ensure that if it was predicted as a branch, it really is a 721 // branch. 722 if (inst->readPredTaken() && !inst->isControl()) { 723 panic("Instruction predicted as a branch!"); 724 725 ++decodeControlMispred; 726 727 // Might want to set some sort of boolean and just do 728 // a check at the end 729 squash(inst, inst->threadNumber); 730 731 break; 732 } 733 734 // Go ahead and compute any PC-relative branches. 735 if (inst->isDirectCtrl() && inst->isUncondCtrl()) { 736 ++decodeBranchResolved; 737 738 if (!(inst->branchTarget() == inst->readPredTarg())) { 739 ++decodeBranchMispred; 740 741 // Might want to set some sort of boolean and just do 742 // a check at the end 743 squash(inst, inst->threadNumber); 744 TheISA::PCState target = inst->branchTarget(); 745 746 DPRINTF(Decode, "[sn:%i]: Updating predictions: PredPC: %s\n", 747 inst->seqNum, target); 748 //The micro pc after an instruction level branch should be 0 749 inst->setPredTarg(target); 750 break; 751 } 752 } 753 } 754 755 // If we didn't process all instructions, then we will need to block 756 // and put all those instructions into the skid buffer. 757 if (!insts_to_decode.empty()) { 758 block(tid); 759 } 760 761 // Record that decode has written to the time buffer for activity 762 // tracking. 763 if (toRenameIndex) { 764 wroteToTimeBuffer = true; 765 } 766} 767